| /* SPDX-License-Identifier: GPL-2.0 */ |
| /* |
| * Copyright (c) 2021 MediaTek Inc. |
| * Author: Qiqi Wang <qiqi.wang@mediatek.com> |
| */ |
| |
| #ifndef _DT_BINDINGS_CLK_MT8696_H |
| #define _DT_BINDINGS_CLK_MT8696_H |
| |
| /* TOPCKGEN */ |
| |
| #define CLK_TOP_NULL 0 |
| #define CLK_TOP_SYSPLL_D2 1 |
| #define CLK_TOP_SYSPLL1_D2 2 |
| #define CLK_TOP_SYSPLL1_D4 3 |
| #define CLK_TOP_SYSPLL1_D8 4 |
| #define CLK_TOP_SYSPLL1_D16 5 |
| #define CLK_TOP_SYSPLL1_D32 6 |
| #define CLK_TOP_SYSPLL_D3 7 |
| #define CLK_TOP_SYSPLL2_D2 8 |
| #define CLK_TOP_SYSPLL2_D4 9 |
| #define CLK_TOP_SYSPLL2_D8 10 |
| #define CLK_TOP_SYSPLL_D5 11 |
| #define CLK_TOP_SYSPLL3_D2 12 |
| #define CLK_TOP_SYSPLL3_D4 13 |
| #define CLK_TOP_SYSPLL3_D8 14 |
| #define CLK_TOP_SYSPLL_D7 15 |
| #define CLK_TOP_SYSPLL4_D4 16 |
| #define CLK_TOP_SYSPLL4_D8 17 |
| #define CLK_TOP_UNIVPLL_D2 18 |
| #define CLK_TOP_UNIVPLL1_D2 19 |
| #define CLK_TOP_UNIVPLL1_D4 20 |
| #define CLK_TOP_UNIVPLL1_D8 21 |
| #define CLK_TOP_UNIVPLL1_D16 22 |
| #define CLK_TOP_UNIVPLL_D3 23 |
| #define CLK_TOP_UNIVPLL2_D2 24 |
| #define CLK_TOP_UNIVPLL2_D4 25 |
| #define CLK_TOP_UNIVPLL2_D8 26 |
| #define CLK_TOP_UNIVPLL2_D16 27 |
| #define CLK_TOP_UNIVPLL_D5 28 |
| #define CLK_TOP_UNIVPLL3_D2 29 |
| #define CLK_TOP_UNIVPLL3_D4 30 |
| #define CLK_TOP_UNIVPLL3_D8 31 |
| #define CLK_TOP_UNIVPLL3_D16 32 |
| #define CLK_TOP_UNIVPLL_D7 33 |
| #define CLK_TOP_UNIVPLL4_D2 34 |
| #define CLK_TOP_UNIVPLL_D26 35 |
| #define CLK_TOP_UNIVPLL_D52 36 |
| #define CLK_TOP_APLL1_D2 37 |
| #define CLK_TOP_APLL1_D4 38 |
| #define CLK_TOP_APLL1_D8 39 |
| #define CLK_TOP_APLL1_D16 40 |
| #define CLK_TOP_APLL1_D3 41 |
| #define CLK_TOP_APLL2_D2 42 |
| #define CLK_TOP_APLL2_D4 43 |
| #define CLK_TOP_APLL2_D8 44 |
| #define CLK_TOP_APLL2_D16 45 |
| #define CLK_TOP_APLL2_D3 46 |
| #define CLK_TOP_APLL3_D2 47 |
| #define CLK_TOP_APLL3_D4 48 |
| #define CLK_TOP_APLL3_D8 49 |
| #define CLK_TOP_APLL3_D16 50 |
| #define CLK_TOP_APLL3_D3 51 |
| #define CLK_TOP_APLL4_D2 52 |
| #define CLK_TOP_APLL4_D4 53 |
| #define CLK_TOP_APLL4_D8 54 |
| #define CLK_TOP_APLL4_D16 55 |
| #define CLK_TOP_APLL4_D3 56 |
| #define CLK_TOP_APLL5_D2 57 |
| #define CLK_TOP_APLL5_D4 58 |
| #define CLK_TOP_APLL5_D8 59 |
| #define CLK_TOP_APLL5_D16 60 |
| #define CLK_TOP_APLL5_D3 61 |
| #define CLK_TOP_HDMIRX_APLL_D2 62 |
| #define CLK_TOP_HDMIRX_APLL_D4 63 |
| #define CLK_TOP_HDMIRX_APLL_D8 64 |
| #define CLK_TOP_HDMIRX_APLL_D16 65 |
| #define CLK_TOP_HDMIRX_APLL_D3 66 |
| #define CLK_TOP_HDMIRX_APLL_D6 67 |
| #define CLK_TOP_OSDPLL_D2 68 |
| #define CLK_TOP_OSDPLL_D4 69 |
| #define CLK_TOP_OSDPLL_D8 70 |
| #define CLK_TOP_OSDPLL_D3 71 |
| #define CLK_TOP_OSDPLL1_D2 72 |
| #define CLK_TOP_OSDPLL1_D4 73 |
| #define CLK_TOP_OSDPLL1_D8 74 |
| #define CLK_TOP_OSDPLL1_D16 75 |
| #define CLK_TOP_ETHERPLL_500M 76 |
| #define CLK_TOP_ETHERPLL_250M 77 |
| #define CLK_TOP_ETHERPLL_125M 78 |
| #define CLK_TOP_ETHERPLL_50M 79 |
| #define CLK_TOP_VDECPLL_D2 80 |
| #define CLK_TOP_TVDPLL_D2 81 |
| #define CLK_TOP_TVDPLL_D4 82 |
| #define CLK_TOP_TVDPLL_D3 83 |
| #define CLK_TOP_TVDPLL_D6 84 |
| #define CLK_TOP_MSDCPLL_D2 85 |
| #define CLK_TOP_MSDCPLL_D4 86 |
| #define CLK_TOP_MSDCPLL_D8 87 |
| #define CLK_TOP_HDMITX_PIXEL 88 |
| #define CLK_TOP_HDMITX_PIXEL_D2 89 |
| #define CLK_TOP_HDMITX_PIXEL_D4 90 |
| #define CLK_TOP_HDMITX_PIXEL_D3 91 |
| #define CLK_TOP_HDMITX_PIXEL_D6 92 |
| #define CLK_TOP_CLKRTC_INT 93 |
| #define CLK_TOP_CLKRTC_EXT 94 |
| #define CLK_TOP_CLK26MD2 95 |
| #define CLK_TOP_DMPLL 96 |
| #define CLK_TOP_DMPLL_D2 97 |
| #define CLK_TOP_AXI_SEL 98 |
| #define CLK_TOP_SCP_SEL 99 |
| #define CLK_TOP_MEMSEL 100 |
| #define CLK_TOP_MEMREF_104_SEL 101 |
| #define CLK_TOP_MEM52M_SEL 102 |
| #define CLK_TOP_SD_SEL 103 |
| #define CLK_TOP_MMSEL 104 |
| #define CLK_TOP_VDEC_SEL 105 |
| #define CLK_TOP_VDEC_SLOW_SEL 106 |
| #define CLK_TOP_VENC_SEL 107 |
| #define CLK_TOP_MFG_SEL 108 |
| #define CLK_TOP_RSZ_SEL 109 |
| #define CLK_TOP_UART_SEL 110 |
| #define CLK_TOP_SPI_SEL 111 |
| #define CLK_TOP_USB20_SEL 112 |
| #define CLK_TOP_USB30_SEL 113 |
| #define CLK_TOP_MSDC50_0_HC_SEL 114 |
| #define CLK_TOP_MSDC50_0_SEL 115 |
| #define CLK_TOP_MSDC30_1_SEL 116 |
| #define CLK_TOP_MSDC30_2_SEL 117 |
| #define CLK_TOP_MSDC50_2_HC_SEL 118 |
| #define CLK_TOP_MSDC0P_AESSEL 119 |
| #define CLK_TOP_INTDIR_SEL 120 |
| #define CLK_TOP_AUDIO_SEL 121 |
| #define CLK_TOP_AUDIO_26MSEL 122 |
| #define CLK_TOP_AUD_INTBUSSEL 123 |
| #define CLK_TOP_APLL_SEL 124 |
| #define CLK_TOP_APLL2_SEL 125 |
| #define CLK_TOP_APLL3_SEL 126 |
| #define CLK_TOP_APLL4_SEL 127 |
| #define CLK_TOP_APLL5_SEL 128 |
| #define CLK_TOP_APLL6_SEL 129 |
| #define CLK_TOP_A1SYSHP_SEL 130 |
| #define CLK_TOP_A2SYSHP_SEL 131 |
| #define CLK_TOP_A3SYSHP_SEL 132 |
| #define CLK_TOP_A4SYSHP_SEL 133 |
| #define CLK_TOP_ASML_SEL 134 |
| #define CLK_TOP_ASMM_SEL 135 |
| #define CLK_TOP_ASMH_SEL 136 |
| #define CLK_TOP_AUD_IEC_SEL 137 |
| #define CLK_TOP_I2SO1_SEL 138 |
| #define CLK_TOP_I2SO2_SEL 139 |
| #define CLK_TOP_I2SI1_SEL 140 |
| #define CLK_TOP_I2SI2_SEL 141 |
| #define CLK_TOP_RV33_SEL 142 |
| #define CLK_TOP_STC_TOP_27MSEL 143 |
| #define CLK_TOP_OSD_SEL 144 |
| #define CLK_TOP_VDO3_SEL 145 |
| #define CLK_TOP_VDO4_SEL 146 |
| #define CLK_TOP_HD_SEL 147 |
| #define CLK_TOP_NR_SEL 148 |
| #define CLK_TOP_PE2_MAC_P0_SEL 149 |
| #define CLK_TOP_HDCP_SEL 150 |
| #define CLK_TOP_HDCP_24MSEL 151 |
| #define CLK_TOP_RTC_SEL 152 |
| #define CLK_TOP_SPINOR_SEL 153 |
| #define CLK_TOP_ETH_250MSEL 154 |
| #define CLK_TOP_ETH_125MSEL 155 |
| #define CLK_TOP_ETH_50MRMSEL 156 |
| #define CLK_TOP_I2C_SEL 157 |
| #define CLK_TOP_PWMINFRA_SEL 158 |
| #define CLK_TOP_GCPU_SEL 159 |
| #define CLK_TOP_ECC_SEL 160 |
| #define CLK_TOP_DI_SEL 161 |
| #define CLK_TOP_NFI2X_SEL 162 |
| #define CLK_TOP_SPINFI_SEL 163 |
| #define CLK_TOP_HD20_DACR_SEL 164 |
| #define CLK_TOP_HD20_HDCP_SEL 165 |
| #define CLK_TOP_HDMI_SEL 166 |
| #define CLK_TOP_NNA0_SEL 167 |
| #define CLK_TOP_HDMI_APB_SEL 168 |
| #define CLK_TOP_CUPMSEL 169 |
| #define CLK_TOP_APLL1_REF_SEL 170 |
| #define CLK_TOP_APLL2_REF_SEL 171 |
| #define CLK_TOP_APLL3_REF_SEL 172 |
| #define CLK_TOP_APLL4_REF_SEL 173 |
| #define CLK_TOP_APLL5_REF_SEL 174 |
| #define CLK_TOP_HDMIRX_APLL_SEL 175 |
| #define CLK_TOP_I2SI1_M 176 |
| #define CLK_TOP_I2SI2_M 177 |
| #define CLK_TOP_I2SO1_M 178 |
| #define CLK_TOP_I2SO2_M 179 |
| #define CLK_TOP_AUD_IEC 180 |
| #define CLK_TOP_APLL12_DIV0 181 |
| #define CLK_TOP_APLL12_DIV1 182 |
| #define CLK_TOP_APLL12_DIV2 183 |
| #define CLK_TOP_APLL12_DIV3 184 |
| #define CLK_TOP_APLL12_DIV4 185 |
| #define CLK_TOP_APLL1_D3AB 186 |
| #define CLK_TOP_APLL2_D3AB 187 |
| #define CLK_TOP_APLL3_D3AB 188 |
| #define CLK_TOP_APLL4_D3AB 189 |
| #define CLK_TOP_APLL5_D3AB 190 |
| #define CLK_TOP_HMR_APPD3AB 191 |
| #define CLK_TOP_OSDPLL_D3AB 192 |
| #define CLK_TOP_EPLLD10 193 |
| #define CLK_TOP_HMT_PX_D3 194 |
| #define CLK_TOP_TVDPLL_D3AB 195 |
| #define CLK_TOP_HMR_AXI 196 |
| #define CLK_TOP_SSUSB_TOP 197 |
| #define CLK_TOP_SSUSB_PHY 198 |
| #define CLK_TOP_SSUSB_U2_PHY 199 |
| #define CLK_TOP_NR_CLK 200 |
| |
| /* MCUCFG */ |
| |
| #define CLK_MCU_CPU_PLL_SEL 0 |
| #define CLK_MCU_BUSPLL_SEL 1 |
| #define CLK_MCU_NR_CLK 2 |
| |
| /* INFRACFG */ |
| |
| #define CLK_INFRA_DBGCLK 0 |
| #define CLK_INFRA_AUDIO 1 |
| #define CLK_INFRA_GCE 2 |
| #define CLK_INFRA_M4U 3 |
| #define CLK_INFRA_CQ_DMA 4 |
| #define CLK_INFRA_KP 5 |
| #define CLK_INFRA_IIC_AO 6 |
| #define CLK_INFRA_CEC 7 |
| #define CLK_INFRA_IIC 8 |
| #define CLK_INFRA_PWM0_AO 9 |
| #define CLK_INFRA_PWM1_AO 10 |
| #define CLK_INFRA_UART_AO 11 |
| #define CLK_INFRA_PWMAO 12 |
| #define CLK_INFRA_IPSYS 13 |
| #define CLK_INFRA2L3C 14 |
| #define CLK_INFRA_TRNG 15 |
| #define CLK_INFRA_NR_CLK 16 |
| |
| /* PERICFG */ |
| |
| #define CLK_PERI_NFI 0 |
| #define CLK_PERI_THERM 1 |
| #define CLK_PERI_PWM0 2 |
| #define CLK_PERI_PWM1 3 |
| #define CLK_PERI_PWM2 4 |
| #define CLK_PERI_PWM3 5 |
| #define CLK_PERI_PWM4 6 |
| #define CLK_PERI_PWM5 7 |
| #define CLK_PERI_PWM 8 |
| #define CLK_PERI_USB0 9 |
| #define CLK_PERI_AP_DMA 10 |
| #define CLK_PERI_MSDC30_0 11 |
| #define CLK_PERI_MSDC30_1 12 |
| #define CLK_PERI_MSDC30_2 13 |
| #define CLK_PERI_UART0 14 |
| #define CLK_PERI_UART1 15 |
| #define CLK_PERI_I2C0 16 |
| #define CLK_PERI_I2C1 17 |
| #define CLK_PERI_AUXADC 18 |
| #define CLK_PERI_SPI0 19 |
| #define CLK_PERI_FLASH 20 |
| #define CLK_PERI_SPI2 21 |
| #define CLK_PERI_SFLASH 22 |
| #define CLK_PERI_GMAC 23 |
| #define CLK_PERI_PCIE0 24 |
| #define CLK_PERI_GMAC_PCLK 25 |
| #define CLK_PERI_PTP_THERM 26 |
| #define CLK_PERI_MM_APB 27 |
| #define CLK_PERI_MSDC0_EN 28 |
| #define CLK_PERI_MSDC1_EN 29 |
| #define CLK_PERI_MSDC2_EN 30 |
| #define CLK_PERI_MSDC0_H_EN 31 |
| #define CLK_PERI_MSDC2_H_EN 32 |
| #define CLK_PERI_NR_CLK 33 |
| |
| /* APMIXEDSYS */ |
| |
| #define CLK_APMIXED_MAINPLL 0 |
| #define CLK_APMIXED_UNIVPLL 1 |
| #define CLK_APMIXED_VDECPLL 2 |
| #define CLK_APMIXED_ETHERPLL 3 |
| #define CLK_APMIXED_OSDPLL 4 |
| #define CLK_APMIXED_APLL1 5 |
| #define CLK_APMIXED_APLL2 6 |
| #define CLK_APMIXED_APLL3 7 |
| #define CLK_APMIXED_APLL4 8 |
| #define CLK_APMIXED_APLL5 9 |
| #define CLK_APMIXED_HDMIRX_APLL 10 |
| #define CLK_APMIXED_MSDCPLL 11 |
| #define CLK_APMIXED_TVDPLL 12 |
| #define CLK_APMIXED_MMPLL 13 |
| #define CLK_APMIXED_ARMPLL 14 |
| #define CLK_APMIXED_CCIPLL 15 |
| #define CLK_APMIXED_VDECPLL_27M 16 |
| #define CLK_APMIXED_NR_CLK 17 |
| |
| /* NNA */ |
| |
| #define CLK_NNA0 0 |
| #define CLK_NNA0_26MEN 1 |
| #define CLK_NNA0_PWR 2 |
| #define CLK_NNA_NR_CLK 3 |
| |
| /* ETHER */ |
| |
| #define CLK_ETH_APB_PCLKEN 0 |
| #define CLK_ETH_AXI_MCLKEN 1 |
| #define CLK_ETH_RX_I_RMIIEN 2 |
| #define CLK_ETH_TX_I_RMIIEN 3 |
| #define CLK_ETH_RX_IEN 4 |
| #define CLK_ETH_TX_IEN 5 |
| #define CLK_ETH_MAC_EXTEN 6 |
| #define CLK_ETH_NCLK_IEN 7 |
| #define CLK_ETHER_NR_CLK 8 |
| |
| /* MFGCFG */ |
| |
| #define CLK_MFG_BG3D 0 |
| #define CLK_MFG_NR_CLK 1 |
| |
| /* MMSYS */ |
| |
| #define CLK_MMCG0_SMI_COM 0 |
| #define CLK_MMCG1_SMI_L0 1 |
| #define CLK_MMCG2_DRAM_L 2 |
| #define CLK_MMCG3_FAKEG 3 |
| #define CLK_MMCG4_SMI_L4 4 |
| #define CLK_MMCG5_SMI_L1 5 |
| #define CLK_MMCG6_SMI_L5 6 |
| #define CLK_MMCG7_SMI_L6 7 |
| #define CLK_MMCG8_SMI_L7 8 |
| #define CLK_MMCG9_VDEC2IMG 9 |
| #define CLK_MMCG10_VDOUT_MM 10 |
| #define CLK_MMCG11_SMI_L3 11 |
| #define CLK_MMCG13_FMTTER 12 |
| #define CLK_MMCG14_DISP_MIX 13 |
| #define CLK_MMCG15_OSD_FBDC 14 |
| #define CLK_MMCG16_OF 15 |
| #define CLK_MMCG17_OF_FIFO 16 |
| #define CLK_MMCG18_OF_HDR 17 |
| #define CLK_MMCG19_OF_SI2MI 18 |
| #define CLK_MMCG20_HDR_ADL 19 |
| #define CLK_MMCG21_HDR_FIFO 20 |
| #define CLK_MMCG22_HDR_VDO 21 |
| #define CLK_MMCG23_RGB2HDMI 22 |
| #define CLK_MMCG25_DGI 23 |
| #define CLK_MMCG0_SD_PPF 24 |
| #define CLK_MMCG1_P2I 25 |
| #define CLK_MMCG2_VM_TOP 26 |
| #define CLK_MMCG3_HDMI_MD 27 |
| #define CLK_MMCG4_VIDEO_IN 28 |
| #define CLK_MMCG5_W2D 29 |
| #define CLK_MMCG7_OU 30 |
| #define CLK_MMCG8_OU_FIFO 31 |
| #define CLK_MMCG9_OU_HDR 32 |
| #define CLK_MMCG12_SMI_L0 33 |
| #define CLK_MM_NR_CLK 34 |
| |
| /* IMGSYS */ |
| |
| #define CLK_IMG_VDO3 0 |
| #define CLK_IMG_DISPFMT3 1 |
| #define CLK_IMG_R2R 2 |
| #define CLK_IMG_SMI_L5 3 |
| #define CLK_IMG_SMI_L6 4 |
| #define CLK_IMG_DRAMC_L8 5 |
| #define CLK_IMG_VDO4 6 |
| #define CLK_IMG_DISPFMT4 7 |
| #define CLK_IMG_IRT_DMA 8 |
| #define CLK_IMGRSZ 9 |
| #define CLK_IMG_VDO_DI 10 |
| #define CLK_IMG_DISPFMT_DI 11 |
| #define CLK_IMG_NR 12 |
| #define CLK_IMG_WR_CHANNEL 13 |
| #define CLK_IMG_MVDO_FIFO 14 |
| #define CLK_IMG_MFILM_GRAIN 15 |
| #define CLK_IMG_MHDR_VDO_FE 16 |
| #define CLK_IMG_MVDO_FE_ADL 17 |
| #define CLK_IMG_SVDO_FIFO 18 |
| #define CLK_IMG_SFILMGRAIN 19 |
| #define CLK_IMG_SHDR_VDO_FE 20 |
| #define CLK_IMG_NR_CLK 21 |
| |
| /* VDECSOC */ |
| |
| #define CLK_VDSOC_L1_SOCEN 0 |
| #define CLK_VDSOC_LSEN 1 |
| #define CLK_VDSOC_LS_ATIV 2 |
| #define CLK_VDSOC_VSEN 3 |
| #define CLK_VDSOC_VS_ATIV 4 |
| #define CLK_VDSOC_NR_CLK 5 |
| |
| /* VDECCORE */ |
| |
| #define CLK_VDEC_L1EN 0 |
| #define CLK_VDEC_LATEN 1 |
| #define CLK_VDEC_LAT_ATIV 2 |
| #define CLK_VDECEN 3 |
| #define CLK_VDEC_ATIV 4 |
| #define CLK_VDEC_NR_CLK 5 |
| |
| /* VENCSYS */ |
| |
| #define CLK_VENC_SMI_CON 0 |
| #define CLK_VENC_CON 1 |
| #define CLK_VENC_NR_CLK 2 |
| |
| #endif /* _DT_BINDINGS_CLK_MT8696_H */ |
| |
