| /* SPDX-License-Identifier: GPL-2.0 */ |
| /* |
| * Copyright (c) 2020 MediaTek Inc. |
| */ |
| |
| |
| #ifndef __DT_BINDINGS_INTERCONNECT_MTK_MT8195_EMI_H |
| #define __DT_BINDINGS_INTERCONNECT_MTK_MT8195_EMI_H |
| |
| #define MT8195_SLAVE_DDR_EMI 0 |
| #define MT8195_MASTER_MCUSYS 1 |
| #define MT8195_MASTER_GPUSYS 2 |
| #define MT8195_MASTER_MMSYS 3 |
| #define MT8195_MASTER_MM_VPU 4 |
| #define MT8195_MASTER_MM_DISP 5 |
| #define MT8195_MASTER_MM_VDEC 6 |
| #define MT8195_MASTER_MM_VENC 7 |
| #define MT8195_MASTER_MM_CAM 8 |
| #define MT8195_MASTER_MM_IMG 9 |
| #define MT8195_MASTER_MM_MDP 10 |
| #define MT8195_MASTER_VPUSYS 11 |
| #define MT8195_MASTER_VPU_0 12 |
| #define MT8195_MASTER_VPU_1 13 |
| #define MT8195_MASTER_MDLASYS 14 |
| #define MT8195_MASTER_MDLA_0 15 |
| #define MT8195_MASTER_UFS 16 |
| #define MT8195_MASTER_PCIE_0 17 |
| #define MT8195_MASTER_PCIE_1 18 |
| #define MT8195_MASTER_USB 19 |
| #define MT8195_MASTER_DBGIF 20 |
| #define MT8195_SLAVE_HRT_DDR_EMI 21 |
| #define MT8195_MASTER_HRT_MMSYS 22 |
| #define MT8195_MASTER_HRT_MM_DISP 23 |
| #define MT8195_MASTER_HRT_MM_VDEC 24 |
| #define MT8195_MASTER_HRT_MM_VENC 25 |
| #define MT8195_MASTER_HRT_MM_CAM 26 |
| #define MT8195_MASTER_HRT_MM_IMG 27 |
| #define MT8195_MASTER_HRT_MM_MDP 28 |
| #define MT8195_MASTER_HRT_DBGIF 29 |
| #define MT8195_MASTER_WIFI 30 |
| #define MT8195_MASTER_BT 31 |
| #define MT8195_MASTER_NETSYS 32 |
| #endif |
