| /* SPDX-License-Identifier: GPL-2.0 */ |
| /* |
| * Copyright (c) 2020 MediaTek Inc. |
| * Author: Qiqi Wang <qiqi.wang@mediatek.com> |
| */ |
| |
| #ifndef _DT_BINDINGS_POWER_MT8696_POWER_H |
| #define _DT_BINDINGS_POWER_MT8696_POWER_H |
| |
| #define MT8696_POWER_DOMAIN_VDEC_CORE0 0 |
| #define MT8696_POWER_DOMAIN_VENC 1 |
| #define MT8696_POWER_DOMAIN_MMSYS_TOP 2 |
| #define MT8696_POWER_DOMAIN_MMSYS_COMMON 3 |
| #define MT8696_POWER_DOMAIN_OSD_UHD 4 |
| #define MT8696_POWER_DOMAIN_HDMITX 5 |
| #define MT8696_POWER_DOMAIN_HDMIRX 6 |
| #define MT8696_POWER_DOMAIN_DISP_MAIN 7 |
| #define MT8696_POWER_DOMAIN_DISP_SUB 8 |
| #define MT8696_POWER_DOMAIN_DISP_COMMON 9 |
| #define MT8696_POWER_DOMAIN_AUDIO 10 |
| #define MT8696_POWER_DOMAIN_AUDIO_ASRC 11 |
| #define MT8696_POWER_DOMAIN_SSUSB 12 |
| #define MT8696_POWER_DOMAIN_ETHER_PCIE 13 |
| #define MT8696_POWER_DOMAIN_MFG 14 |
| #define MT8696_POWER_DOMAIN_MFG2 15 |
| #define MT8696_POWER_DOMAIN_MFG3 16 |
| #define MT8696_POWER_DOMAIN_HDMIRX_PHY 17 |
| #define MT8696_POWER_DOMAIN_VDEC_SOC 18 |
| |
| #endif /* _DT_BINDINGS_POWER_MT8696_POWER_H */ |
