blob: eccab80e3e20c30165415e1d5427127dd5da5332 [file] [log] [blame]
/*
* MARVELL BERLIN2CDP SoC device tree source
*
* Author: Jisheng Zhang <jszhang@marvell.com>
* Copyright (c) 2013 Marvell International Ltd.
* http://www.marvell.com
*
* MARVELL BERLIN2CDP SoC device nodes are listed in this file.
* BERLIN2CDP based board files can include this file and provide
* values for board specfic bindings.
*
* Note: This file does not include device nodes for all the controllers in
* BERLIN2CDP SoC. As device tree coverage for BERLIN2CDP increases,
* additional nodes can be added to this file.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/include/ "skeleton.dtsi"
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0>;
operating-points = <
/* kHz uV */
1000000 1200000
800000 1200000
600000 1200000
>;
clock-latency = <100000>;
clocks = <&cpuclk>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <1>;
};
};
memory {
name = "memory";
device_type = "memory";
reg = <0x01100000 0x13f00000>;
};
chosen {
bootargs = "console=ttyS0,115200 root=/dev/nfs nfsroot=10.37.116.100:/home/jszhang/_install,vers=3 ip=::::bg2-cdp::dhcp macaddr=00:78:73:AB:38:CF mtdparts=mv_nand:1M(block0)ro,8M(bootloader),7M(fts)ro,16M(kernel),60M(recovery),80M(backupsys)ro,16M(factory_store),400M(rootfs),32M(localstorage),300M(cache),1024M(userdata)";
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
osc: osc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
cpupll: cpupll {
compatible = "marvell,berlin2cdp-pll";
clocks = <&osc>;
#clock-cells = <0>;
reg = <0xF7920070 0x14>, <0xF7EA0634 4>;
bypass-shift = /bits/ 8 <2>;
};
syspll: syspll {
compatible = "marvell,berlin2cdp-pll";
clocks = <&osc>;
#clock-cells = <0>;
reg = <0xF7EA0200 0x14>, <0xF7EA0634 4>;
bypass-shift = /bits/ 8 <0>;
};
cpuclk: cpuclk {
compatible = "fixed-factor-clock";
clocks = <&cpupll>;
#clock-cells = <0>;
clock-div = <1>;
clock-mult = <1>;
set-rate-parent;
};
cfgclk: cfgclk {
compatible = "marvell,berlin-clk";
clocks = <&syspll>;
#clock-cells = <0>;
reg = <0xF7EA0640 4>;
};
perifclk: perifclk {
compatible = "marvell,berlin-clk";
clocks = <&syspll>;
#clock-cells = <0>;
reg = <0xF7EA0670 4>;
};
nfceccclk: nfceccclk {
compatible = "marvell,berlin-clk";
clocks = <&syspll>;
#clock-cells = <0>;
reg = <0xF7EA0688 4>;
};
sd0clk: sd0clk {
compatible = "marvell,berlin-clk";
clocks = <&syspll>;
#clock-cells = <0>;
reg = <0xF7EA068C 4>;
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges;
sw_generic1 {
compatible = "marvell,berlin-sw_generic1";
reg = <0xF7EA001C 4>;
};
timer {
compatible = "arm,armv7-timer";
interrupts = <1 13 0xf08>,
<1 14 0xf08>,
<1 11 0xf08>,
<1 10 0xf08>;
clock-frequency = <25000000>;
always-on;
};
gic:interrupt-controller@F7901000 {
compatible = "arm,cortex-a15-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0xF7901000 0x1000>, <0xF7902000 0x1000>;
};
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <0 23 4 0 24 4>;
};
ethernet@F7B90000 {
compatible = "mrvl,fastethernet";
reg = <0xF7B90000 0x10000>;
interrupts = <0 16 4>;
};
usb@F7EE0000 {
compatible = "mrvl,berlin-ehci";
reg = <0xF7ED0000 0x10000>;
interrupts = <0 11 4>;
phy-base = <0xF7B74000>;
};
sdhci@F7AB0800 {
compatible = "mrvl,berlin-sdhci";
reg = <0xF7AB0800 0x200>;
interrupts = <0 15 4>;
clocks = <&sd0clk>;
mrvl,no-hispd;
mrvl,card-wired;
mrvl,host-off-card-on;
};
sdhci@F7AB0000 {
compatible = "mrvl,berlin-sdhci";
reg = <0xF7AB0000 0x200>;
interrupts = <0 13 4>;
clocks = <&nfceccclk>;
mrvl,card-wired;
mrvl,8bit-data;
};
apb_ictl: interrupt-controller@F7E83800 {
compatible = "snps,dw-apb-ictl";
interrupts = <0 8 4>;
interrupt-controller;
#interrupt-cells = <1>;
reg = <0xF7E83800 0x30>;
ictl-nr-irqs = <32>;
};
sm_ictl: interrupt-controller@F7FCE000 {
compatible = "snps,dw-apb-ictl";
interrupts = <0 17 4>;
interrupt-controller;
#interrupt-cells = <1>;
reg = <0xF7FCE000 0x30>;
ictl-nr-irqs = <32>;
};
timer0: apbtimer@F7E82C00 {
compatible = "berlin,apb-timer";
interrupt-parent = <&apb_ictl>;
interrupts = <8>;
clock-freq = <100000000>;
reg = <0xF7E82C00 0x14>;
};
timer1: apbtimer@F7E82C8C {
compatible = "berlin,apb-timer";
clock-freq = <100000000>;
reg = <0xF7E82C8C 0x14>;
};
uart0: uart@F7FC9000 {
compatible = "snps,dw-apb-uart";
reg = <0xF7FC9000 0x100>;
interrupt-parent = <&sm_ictl>;
interrupts = <8>;
clock-frequency = <25000000>;
reg-shift = <2>;
};
uart1: uart@F7FCA000 {
compatible = "snps,dw-apb-uart";
reg = <0xF7FCA000 0x100>;
interrupt-parent = <&sm_ictl>;
interrupts = <9>;
clock-frequency = <25000000>;
reg-shift = <2>;
};
gpio0: apbgpio@F7E80400 {
compatible = "snps,dw-apb-gpio";
dev_name = "gpio_soc_0";
reg = <0xF7E80400 0x400>;
#address-cells = <1>;
#size-cells = <0>;
banka: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-bank";
gpio-controller;
reg = <0>;
#gpio-cells = <2>;
nr-gpio = <32>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&apb_ictl>;
interrupts = <0>;
};
};
gpio1: apbgpio@F7E80800 {
compatible = "snps,dw-apb-gpio";
dev_name = "gpio_soc_1";
reg = <0xF7E80800 0x400>;
#address-cells = <1>;
#size-cells = <0>;
bankb: gpio-controller@1 {
compatible = "snps,dw-apb-gpio-bank";
gpio-controller;
reg = <0>;
#gpio-cells = <2>;
nr-gpio = <32>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&apb_ictl>;
interrupts = <1>;
};
};
gpio2: apbgpio@F7E80C00 {
compatible = "snps,dw-apb-gpio";
dev_name = "gpio_soc_2";
reg = <0xF7E80C00 0x400>;
#address-cells = <1>;
#size-cells = <0>;
bankc: gpio-controller@2 {
compatible = "snps,dw-apb-gpio-bank";
gpio-controller;
reg = <0>;
#gpio-cells = <2>;
nr-gpio = <32>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&apb_ictl>;
interrupts = <2>;
};
};
gpio3: apbgpio@F7E81000 {
compatible = "snps,dw-apb-gpio";
dev_name = "gpio_soc_3";
reg = <0xF7E81000 0x400>;
#address-cells = <1>;
#size-cells = <0>;
bankd: gpio-controller@3 {
compatible = "snps,dw-apb-gpio-bank";
gpio-controller;
reg = <0>;
#gpio-cells = <2>;
nr-gpio = <32>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&apb_ictl>;
interrupts = <3>;
};
};
gpio4: apbgpio@F7FCC000 {
compatible = "snps,dw-apb-gpio";
dev_name = "gpio_sm_0";
reg = <0xF7FCC000 0x400>;
#address-cells = <1>;
#size-cells = <0>;
banke: gpio-controller@4 {
compatible = "snps,dw-apb-gpio-bank";
gpio-controller;
reg = <0>;
#gpio-cells = <2>;
nr-gpio = <32>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&sm_ictl>;
interrupts = <11>;
};
};
gpio5: apbgpio@F7FC5000 {
compatible = "snps,dw-apb-gpio";
dev_name = "gpio_sm_1";
reg = <0xF7FC5000 0x400>;
#address-cells = <1>;
#size-cells = <0>;
bankf: gpio-controller@5 {
compatible = "snps,dw-apb-gpio-bank";
gpio-controller;
reg = <0>;
#gpio-cells = <2>;
nr-gpio = <32>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&sm_ictl>;
interrupts = <4>;
};
};
i2c0: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
interrupt-parent = <&apb_ictl>;
clocks = <&cfgclk>;
reg = <0xF7E81400 0x100>;
interrupts = <4>;
};
i2c1: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
interrupt-parent = <&apb_ictl>;
clocks = <&cfgclk>;
reg = <0xF7E81800 0x100>;
interrupts = <5>;
};
i2c2: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
interrupt-parent = <&sm_ictl>;
clocks = <&osc>;
reg = <0XF7FC7000 0x100>;
interrupts = <6>;
};
i2c3: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
interrupt-parent = <&sm_ictl>;
clocks = <&osc>;
reg = <0xF7FC8000 0x100>;
interrupts = <7>;
};
watchdog@0xF7FC2000 {
compatible = "snps,dw-wdt";
reg = <0xF7FC2000 0x100>;
interrupt-parent = <&sm_ictl>;
interrupts = <1>;
clocks = <&osc>;
snps,rpl = <0x2>;
};
opp {
compatible = "marvell,berlin2cdp-opp";
};
amp{
compatible = "mrvl,berlin-amp";
interrupts = <0 35 4 0 33 4 0 34 4 0 25 4 0 29 4>;
cec{
compatible = "mrvl,berlin-cec";
interrupt-parent = <&sm_ictl>;
interrupts = <16>;
};
};
shm@29000000 {
compatible = "mrvl,berlin-shm";
reg = <0x15000000 0x0A600000>, <0x1F600000 0x00900000>;
};
nfc@F7F00000 {
compatible = "mrvl,berlin-nfc";
reg = <0xF7F00000 0x10000>, <0xF7D70000 0x10000>;
interrupts = <0 5 4>;
mrvl,nfc-dma;
mrvl,nfc-naked-cmd;
mrvl,nfc-arbi;
};
tsen@F7FCD000 {
compatible = "mrvl,berlin2cdp-tsen-adc33";
reg = <0xF7FCD014 4>,
<0xF7FCD01C 4>,
<0xF7FCD070 4>,
<0xF7FCD024 4>,
<0xF7FCD028 4>;
};
};
};