qca-ssdk/src/adpt/hppe/adpt_hppe_portctrl.c

/*
 * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
 * Permission to use, copy, modify, and/or distribute this software for
 * any purpose with or without fee is hereby granted, provided that the
 * above copyright notice and this permission notice appear in all copies.
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
 * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */


/**
 * @defgroup
 * @{
 */
#include "sw.h"
#include "hppe_portctrl_reg.h"
#include "hppe_portctrl.h"
#include "hppe_xgportctrl_reg.h"
#include "hppe_xgportctrl.h"
#include "hppe_uniphy_reg.h"
#include "hppe_uniphy.h"
#include "hppe_fdb_reg.h"
#include "hppe_fdb.h"
#include "hppe_global_reg.h"
#include "hppe_global.h"
#include "adpt.h"
#include "hsl.h"
#include "hsl_dev.h"
#include "hsl_port_prop.h"
#include "hsl_phy.h"
#include "hppe_init.h"
#include "ssdk_init.h"
#include "ssdk_dts.h"
#include "ssdk_clk.h"
#include "adpt_hppe.h"
#if defined(CPPE)
#include "adpt_cppe_portctrl.h"
#include "cppe_portctrl.h"
#endif
#include "sfp_phy.h"

#define PORT4_PCS_SEL_GMII_FROM_PCS0 1
#define PORT4_PCS_SEL_RGMII 0

#define PORT5_PCS_SEL_RGMII 0
#define PORT5_PCS_SEL_GMII_FROM_PCS0 1
#define PORT5_PCS_SEL_GMII_FROM_PCS1 2
#define PORT5_GMAC_SEL_GMAC 1
#define PORT5_GMAC_SEL_XGMAC 0

#define PORT6_PCS_SEL_RGMII 0
#define PORT6_PCS_SEL_GMII_FROM_PCS2 1
#define PORT6_GMAC_SEL_GMAC 1
#define PORT6_GMAC_SEL_XGMAC 0

#define MAC_SPEED_10M 0
#define MAC_SPEED_100M 1
#define MAC_SPEED_1000M 2
#define MAC_SPEED_10000M 3
#define MAC_SPEED_2500M 4

#define XGMAC_USXGMII_ENABLE 1
#define XGMAC_USXGMII_CLEAR 0

#define XGMAC_SPEED_SELECT_10000M 0
#define XGMAC_SPEED_SELECT_5000M 1
#define XGMAC_SPEED_SELECT_2500M 2
#define XGMAC_SPEED_SELECT_1000M 3
#define LPI_WAKEUP_TIMER	0x20
#define LPI_SLEEP_TIMER	0x100
#define PROMISCUOUS_MODE 0x1
#define PASS_CONTROL_PACKET 0x2
#define XGMAC_PAUSE_TIME	0xffff
#define CARRIER_SENSE_SIGNAL_FROM_MAC        0x0

#define PHY_PORT_TO_BM_PORT(port)	(port + 7)
#define GMAC_IPG_CHECK 0xc
#define LPI_EEE_TIMER_FREQUENCY 300  /* 300MHZ*/
#define LPI_EEE_TIMER_UNIT 256

/* This register is used to adjust the write timing for reserving
 * some bandwidth of the memory to read operation.
 */
#define GMAC_TX_THD    0x1

static a_uint32_t port_interface_mode[SW_MAX_NR_DEV][SW_MAX_NR_PORT] = {0};

static a_bool_t
_adpt_hppe_port_phy_connected (a_uint32_t dev_id, fal_port_t port_id)
{
	a_bool_t force_port = 0;

	ADPT_DEV_ID_CHECK(dev_id);

	/* force port which connect s17c or other device chip*/
	force_port = ssdk_port_feature_get(dev_id, port_id, PHY_F_FORCE);
	if (force_port == A_TRUE) {
		SSDK_DEBUG("port_id %d is a force port!\n", port_id);
		return A_FALSE;
	}
	/* sfp port which connect a sfp module*/
	if (A_TRUE == hsl_port_is_sfp(dev_id, port_id)) {
		SSDK_DEBUG("port_id %d is a SFP port!\n", port_id);
		return A_FALSE;
	}
	/* cpu port and other ethernet port */
	if ((SSDK_PHYSICAL_PORT0 == port_id) || (SSDK_PHYSICAL_PORT7 == port_id)) {
		return A_FALSE;
	} else {
		return hppe_mac_port_valid_check (dev_id, port_id);
	}
}

static sw_error_t
_adpt_phy_status_get_from_ppe(a_uint32_t dev_id, a_uint32_t port_id,
		struct port_phy_status *phy_status)
{
	sw_error_t rv = SW_OK;
	a_uint32_t reg_field = 0;

	ADPT_DEV_ID_CHECK(dev_id);

	if (port_id == SSDK_PHYSICAL_PORT5)
	{

		if (adpt_hppe_chip_revision_get(dev_id)
			== HPPE_REVISION)
		{
			rv = hppe_port_phy_status_1_port5_1_phy_status_get(dev_id,
							&reg_field);
			SW_RTN_ON_ERROR (rv);
		}
#ifdef CPPE
		else
		{
			rv = cppe_port5_pcs1_phy_status_get(dev_id,
					&reg_field);
			SW_RTN_ON_ERROR (rv);
		}
#endif
	} else if (port_id == SSDK_PHYSICAL_PORT1) {
		/*mac0 port1 as 1G sfp mode*/
		rv = hppe_port_phy_status_0_port1_phy_status_get(dev_id,
				&reg_field);
		SW_RTN_ON_ERROR (rv);
	} else if (port_id == SSDK_PHYSICAL_PORT2) {
		/*mac1 port2 as 1G sfp mode*/
		rv = hppe_port_phy_status_0_port2_phy_status_get(dev_id,
				&reg_field);
		SW_RTN_ON_ERROR (rv);
	} else if (port_id == SSDK_PHYSICAL_PORT6) {
		rv = hppe_port_phy_status_1_port6_phy_status_get(dev_id,
						&reg_field);
		SW_RTN_ON_ERROR (rv);
	} else {
		return SW_NOT_SUPPORTED;
	}

	phy_status->tx_flowctrl = A_TRUE;
	phy_status->rx_flowctrl = A_TRUE;

	if ((reg_field >> 7) & 0x1)
	{
		phy_status->link_status = PORT_LINK_UP;
		switch (reg_field & 0x7)
		{
			case MAC_SPEED_10M:
				phy_status->speed = FAL_SPEED_10;
				break;
			case MAC_SPEED_100M:
				phy_status->speed = FAL_SPEED_100;
				break;
			case MAC_SPEED_1000M:
				phy_status->speed = FAL_SPEED_1000;
				break;
			case MAC_SPEED_10000M:
				phy_status->speed = FAL_SPEED_10000;
				break;
			case MAC_SPEED_2500M:
				phy_status->speed = FAL_SPEED_2500;
				break;
			default:
				phy_status->speed = FAL_SPEED_BUTT;
				break;
		}
		phy_status->duplex = FAL_FULL_DUPLEX;
	}
	else
	{
		phy_status->link_status = PORT_LINK_DOWN;
		phy_status->speed = FAL_SPEED_BUTT;
		phy_status->duplex = FAL_DUPLEX_BUTT;
	}

	return rv;
}
#ifndef IN_PORTCONTROL_MINI
static sw_error_t
_adpt_hppe_port_xgmac_loopback_get(a_uint32_t dev_id, fal_port_t port_id,
				 a_bool_t * enable)
{
	sw_error_t rv = SW_OK;

	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
	rv = hppe_mac_rx_configuration_lm_get(dev_id, port_id, (a_uint32_t*)enable);

	return rv;
}

static sw_error_t
_adpt_hppe_port_gmac_loopback_get(a_uint32_t dev_id, fal_port_t port_id,
				 a_bool_t * enable)
{
	sw_error_t rv = SW_OK;

	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
	rv = hppe_mac_ctrl2_mac_loop_back_get(dev_id, port_id, (a_uint32_t*)enable);

	return rv;
}

static sw_error_t
_adpt_hppe_port_xgmac_loopback_set(a_uint32_t dev_id, fal_port_t port_id,
				 a_bool_t enable)
{
	sw_error_t rv = SW_OK;

	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
	rv = hppe_mac_rx_configuration_lm_set(dev_id, port_id, (a_uint32_t)enable);

	return rv;
}

static sw_error_t
_adpt_hppe_port_gmac_loopback_set(a_uint32_t dev_id, fal_port_t port_id,
				 a_bool_t enable)
{
	sw_error_t rv = SW_OK;

	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
	rv = hppe_mac_ctrl2_mac_loop_back_set(dev_id, port_id, (a_uint32_t)enable);

	return rv;
}
#endif
static sw_error_t
_adpt_hppe_port_jumbo_size_set(a_uint32_t dev_id, fal_port_t port_id,
		a_uint32_t jumbo_size)
{
	sw_error_t rv = SW_OK;

	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
	rv = hppe_mac_jumbo_size_mac_jumbo_size_set(dev_id, port_id, jumbo_size);

	return rv;
}

static sw_error_t
_adpt_xgmac_port_max_frame_size_get(a_uint32_t dev_id, fal_port_t port_id,
		a_uint32_t *max_frame)
{
	sw_error_t rv = SW_OK;

	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
	rv = hppe_mac_rx_configuration_gpsl_get(dev_id,port_id, max_frame);

	return rv;
}

static sw_error_t
_adpt_gmac_port_max_frame_size_get(a_uint32_t dev_id, fal_port_t port_id,
		a_uint32_t *max_frame)
{
	sw_error_t rv = SW_OK;

	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
	rv = hppe_mac_jumbo_size_mac_jumbo_size_get(dev_id, port_id, max_frame);

	return rv;
}

static sw_error_t
_adpt_xgmac_port_max_frame_size_set(a_uint32_t dev_id, fal_port_t port_id,
		a_uint32_t max_frame)
{
	sw_error_t rv = SW_OK;

	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
	rv |= hppe_mac_tx_configuration_jd_set(dev_id, port_id, (a_uint32_t)A_TRUE);
	rv |= hppe_mac_rx_configuration_gpsl_set(dev_id, port_id, max_frame);
	rv |= hppe_mac_rx_configuration_wd_set(dev_id, port_id, 1);
	rv |= hppe_mac_rx_configuration_gmpslce_set(dev_id, port_id, 1);
	rv |= hppe_mac_packet_filter_pr_set(dev_id, port_id, PROMISCUOUS_MODE);
	rv |= hppe_mac_packet_filter_pcf_set(dev_id, port_id, PASS_CONTROL_PACKET);

	return rv;
}

static sw_error_t
_adpt_gmac_port_max_frame_size_set(a_uint32_t dev_id, fal_port_t port_id,
		a_uint32_t max_frame)
{
	sw_error_t rv = SW_OK;

	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
	rv |= hppe_mac_ctrl2_maxfr_set(dev_id, port_id, max_frame);
	rv |= hppe_mac_ctrl2_crs_sel_set(dev_id, port_id, CARRIER_SENSE_SIGNAL_FROM_MAC);
	rv |= hppe_mac_dbg_ctrl_hihg_ipg_set(dev_id, port_id, GMAC_IPG_CHECK);
	rv |= hppe_mac_ctrl2_mac_tx_thd_set(dev_id, port_id, GMAC_TX_THD);

	return rv;
}
#ifndef IN_PORTCONTROL_MINI
static sw_error_t
_adpt_xgmac_port_rx_status_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t* port_rxmac_status)
{
	sw_error_t rv = SW_OK;
	union mac_rx_configuration_u xgmac_rx_enable;

	memset(&xgmac_rx_enable, 0, sizeof(xgmac_rx_enable));
	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
	rv = hppe_mac_rx_configuration_get(dev_id, port_id,  &xgmac_rx_enable);
	if( rv != SW_OK )
		return rv;
	*port_rxmac_status = xgmac_rx_enable.bf.re;

	return rv;
}
static sw_error_t
_adpt_gmac_port_rx_status_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t* port_rxmac_status)
{
	sw_error_t rv = SW_OK;
	union mac_enable_u gmac_rx_enable;

	memset(&gmac_rx_enable, 0, sizeof(gmac_rx_enable));
	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
	rv = hppe_mac_enable_get(dev_id, port_id, &gmac_rx_enable);
	if( rv != SW_OK )
		return rv;
	* port_rxmac_status = gmac_rx_enable.bf.rxmac_en;

	return rv;
}
#endif
static sw_error_t
_adpt_xgmac_port_rx_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
{
	sw_error_t rv = SW_OK;
	union mac_rx_configuration_u xgmac_rx_enable;

	memset(&xgmac_rx_enable, 0, sizeof(xgmac_rx_enable));
	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
	rv |=  hppe_mac_rx_configuration_get(dev_id, port_id,  &xgmac_rx_enable);

	xgmac_rx_enable.bf.acs = 1;
	xgmac_rx_enable.bf.cst = 1;
	if (A_TRUE == enable)
	{
		xgmac_rx_enable.bf.re = 1;
	}
	else {
		xgmac_rx_enable.bf.re = 0;
	}
	rv |= hppe_mac_rx_configuration_set(dev_id, port_id, &xgmac_rx_enable);

	return rv;
}

static sw_error_t
_adpt_gmac_port_rx_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
{
	sw_error_t rv = SW_OK;
	union mac_enable_u gmac_rx_enable;

	memset(&gmac_rx_enable, 0, sizeof(gmac_rx_enable));
	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
	rv |= hppe_mac_enable_get(dev_id, port_id, &gmac_rx_enable);
	if (A_TRUE == enable)
		gmac_rx_enable.bf.rxmac_en = 1;
	if (A_FALSE == enable)
		gmac_rx_enable.bf.rxmac_en = 0;
	rv |= hppe_mac_enable_set(dev_id, port_id, &gmac_rx_enable);

	return rv;
}
#ifndef IN_PORTCONTROL_MINI
static sw_error_t
_adpt_xgmac_port_tx_status_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t *port_txmac_status)
{
	sw_error_t rv = SW_OK;
	union mac_tx_configuration_u xgmac_tx_enable;

	memset(&xgmac_tx_enable, 0, sizeof(xgmac_tx_enable));
	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
	rv = hppe_mac_tx_configuration_get(dev_id, port_id,  &xgmac_tx_enable);
	if( rv != SW_OK )
		return  rv;
	*port_txmac_status = xgmac_tx_enable.bf.te;

	return SW_OK;
}

static sw_error_t
_adpt_gmac_port_tx_status_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t *port_txmac_status)
{
	sw_error_t rv = SW_OK;
	union mac_enable_u gmac_tx_enable;

	memset(&gmac_tx_enable, 0, sizeof(gmac_tx_enable));
	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
	rv = hppe_mac_enable_get(dev_id, port_id, &gmac_tx_enable);
	if( rv != SW_OK )
		return  rv;
	*port_txmac_status = gmac_tx_enable.bf.txmac_en;

	return SW_OK;
}
#endif
static sw_error_t
_adpt_xgmac_port_tx_status_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
{
	sw_error_t rv = SW_OK;
	union mac_tx_configuration_u xgmac_tx_enable;

	memset(&xgmac_tx_enable, 0, sizeof(xgmac_tx_enable));
	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
	 rv |=hppe_mac_tx_configuration_get(dev_id, port_id,  &xgmac_tx_enable);
	 if (A_TRUE == enable)
		 xgmac_tx_enable.bf.te = 1;
	 if (A_FALSE == enable)
		 xgmac_tx_enable.bf.te = 0;
	 rv |= hppe_mac_tx_configuration_set(dev_id, port_id, &xgmac_tx_enable);

	 return SW_OK;
}

static sw_error_t
_adpt_gmac_port_tx_status_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
{
	sw_error_t rv = SW_OK;
	union mac_enable_u gmac_tx_enable;

	memset(&gmac_tx_enable, 0, sizeof(gmac_tx_enable));
	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
	rv |= hppe_mac_enable_get(dev_id, port_id, &gmac_tx_enable);
	if (A_TRUE == enable)
		gmac_tx_enable.bf.txmac_en = 1;
	if (A_FALSE == enable)
		gmac_tx_enable.bf.txmac_en = 0;
	rv |= hppe_mac_enable_set(dev_id, port_id, &gmac_tx_enable);

	return SW_OK;
}

static sw_error_t
_adpt_xgmac_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t* txfc_status)
{
	sw_error_t rv = SW_OK;
	union mac_q0_tx_flow_ctrl_u xgmac_txfc_enable;

	memset(&xgmac_txfc_enable, 0, sizeof(xgmac_txfc_enable));
	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
	rv = hppe_mac_q0_tx_flow_ctrl_get(dev_id, port_id, &xgmac_txfc_enable);
	if( rv != SW_OK )
		return rv;
	*txfc_status = xgmac_txfc_enable.bf.tfe;

	return  SW_OK;
}

static sw_error_t
_adpt_gmac_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t* txfc_status)
{
	sw_error_t rv = SW_OK;
	union mac_enable_u gmac_txfc_enable;

	memset(&gmac_txfc_enable, 0, sizeof(gmac_txfc_enable));
	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
	rv = hppe_mac_enable_get(dev_id, port_id, &gmac_txfc_enable);
	if( rv != SW_OK )
		return rv;
	*txfc_status = gmac_txfc_enable.bf.tx_flow_en;

	return  SW_OK;
}

static sw_error_t
_adpt_xgmac_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id,  a_bool_t enable)
{
	sw_error_t rv = SW_OK;
	union mac_q0_tx_flow_ctrl_u xgmac_txfc_enable;

	memset(&xgmac_txfc_enable, 0, sizeof(xgmac_txfc_enable));
	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
	rv |= hppe_mac_q0_tx_flow_ctrl_get(dev_id, port_id,  &xgmac_txfc_enable);
	if (A_TRUE == enable)
	{
		xgmac_txfc_enable.bf.tfe = 1;
		xgmac_txfc_enable.bf.pt = XGMAC_PAUSE_TIME;
	}
	if (A_FALSE == enable)
		xgmac_txfc_enable.bf.tfe = 0;
	 rv |= hppe_mac_q0_tx_flow_ctrl_set(dev_id, port_id,  &xgmac_txfc_enable);

	 return SW_OK;
}

static sw_error_t
_adpt_gmac_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id,  a_bool_t enable)
{
	sw_error_t rv = SW_OK;
	union mac_enable_u gmac_txfc_enable;

	memset(&gmac_txfc_enable, 0, sizeof(gmac_txfc_enable));
	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
	rv |= hppe_mac_enable_get(dev_id, port_id, &gmac_txfc_enable);
	if (A_TRUE == enable)
		gmac_txfc_enable.bf.tx_flow_en = 1;
	if (A_FALSE == enable)
		gmac_txfc_enable.bf.tx_flow_en = 0;
	rv |= hppe_mac_enable_set(dev_id, port_id, &gmac_txfc_enable);

	return SW_OK;
}

static sw_error_t
_adpt_xgmac_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id,  a_uint32_t* rxfc_status)
{
	sw_error_t rv = SW_OK;
	union mac_rx_flow_ctrl_u xgmac_rxfc_enable;

	memset(&xgmac_rxfc_enable, 0, sizeof(xgmac_rxfc_enable));
	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
	rv = hppe_mac_rx_flow_ctrl_get(dev_id, port_id, &xgmac_rxfc_enable);
	if(rv != SW_OK)
		return rv;
	*rxfc_status = xgmac_rxfc_enable.bf.rfe;

	return  SW_OK;
}

static sw_error_t
_adpt_gmac_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t* rxfc_status)
{
	sw_error_t rv = SW_OK;
	union mac_enable_u gmac_rxfc_enable;

	memset(&gmac_rxfc_enable, 0, sizeof(gmac_rxfc_enable));
	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
	rv = hppe_mac_enable_get(dev_id, port_id, &gmac_rxfc_enable);
	if( rv != SW_OK)
		return rv;
	*rxfc_status = gmac_rxfc_enable.bf.rx_flow_en;

	return SW_OK;
}

static sw_error_t
_adpt_xgmac_port_rxfc_status_set(a_uint32_t dev_id,fal_port_t port_id, a_bool_t enable)
{
	sw_error_t rv = SW_OK;
	union mac_rx_flow_ctrl_u xgmac_rxfc_enable;

	memset(&xgmac_rxfc_enable, 0, sizeof(xgmac_rxfc_enable));
	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
	rv |= hppe_mac_rx_flow_ctrl_get(dev_id, port_id, &xgmac_rxfc_enable);
	if (A_TRUE == enable)
		xgmac_rxfc_enable.bf.rfe= 1;
	if (A_FALSE == enable)
		xgmac_rxfc_enable.bf.rfe = 0;
	rv |= hppe_mac_rx_flow_ctrl_set(dev_id, port_id, &xgmac_rxfc_enable);

	return SW_OK;
}

static sw_error_t
_adpt_gmac_port_rxfc_status_set(a_uint32_t dev_id,fal_port_t port_id, a_bool_t enable)
{
	sw_error_t rv = SW_OK;
	union mac_enable_u gmac_rxfc_enable;

	memset(&gmac_rxfc_enable, 0, sizeof(gmac_rxfc_enable));
	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
	rv |= hppe_mac_enable_get(dev_id, port_id, &gmac_rxfc_enable);
	if (A_TRUE == enable)
		gmac_rxfc_enable.bf.rx_flow_en = 1;
	if (A_FALSE == enable)
		gmac_rxfc_enable.bf.rx_flow_en = 0;
	rv |= hppe_mac_enable_set(dev_id, port_id, &gmac_rxfc_enable);

	return SW_OK;
}

#ifndef IN_PORTCONTROL_MINI
sw_error_t
adpt_hppe_port_local_loopback_get(a_uint32_t dev_id, fal_port_t port_id,
					a_bool_t * enable)
{

	sw_error_t rv = 0;
	a_uint32_t phy_id = 0;
	hsl_phy_ops_t *phy_drv;

	ADPT_DEV_ID_CHECK(dev_id);
	ADPT_NULL_POINT_CHECK(enable);

	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
	  {
		return SW_BAD_PARAM;
	  }
	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
		return SW_NOT_SUPPORTED;

	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
	if (NULL == phy_drv->phy_local_loopback_get)
		return SW_NOT_SUPPORTED;

	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
	SW_RTN_ON_ERROR (rv);

	rv = phy_drv->phy_local_loopback_get (dev_id, phy_id, enable);

	return rv;

}
#endif
sw_error_t
adpt_hppe_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id)
{

	sw_error_t rv = 0;
	a_uint32_t phy_id;
	hsl_phy_ops_t *phy_drv;

	ADPT_DEV_ID_CHECK(dev_id);

	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
	  {
		return SW_BAD_PARAM;
	  }
	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
		return SW_NOT_SUPPORTED;

	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
	if (NULL == phy_drv->phy_restart_autoneg)
		return SW_NOT_SUPPORTED;

	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
	SW_RTN_ON_ERROR (rv);

	rv = phy_drv->phy_restart_autoneg (dev_id, phy_id);
	return rv;

}
sw_error_t
adpt_hppe_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
				fal_port_duplex_t duplex)
{
	union mac_enable_u mac_enable;
	sw_error_t rv = 0;
	a_uint32_t phy_id = 0;
	hsl_phy_ops_t *phy_drv;

	memset(&mac_enable, 0, sizeof(mac_enable));
	ADPT_DEV_ID_CHECK(dev_id);

	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU))
	  {
		return SW_BAD_PARAM;
	  }
	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
		return SW_NOT_SUPPORTED;

	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
	if (NULL == phy_drv->phy_duplex_set)
		return SW_NOT_SUPPORTED;

	if (FAL_DUPLEX_BUTT <= duplex)
	{
		return SW_BAD_PARAM;
	}
	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
	SW_RTN_ON_ERROR (rv);

	rv = phy_drv->phy_duplex_set (dev_id, phy_id, duplex);
	SW_RTN_ON_ERROR (rv);

#if 0
	port_id = port_id - 1;
	hppe_mac_enable_get(dev_id, port_id, &mac_enable);

	if (FAL_HALF_DUPLEX == duplex)
		mac_enable.bf.duplex = 0;
	if (FAL_FULL_DUPLEX == duplex)
		mac_enable.bf.duplex = 1;

	hppe_mac_enable_set(dev_id, port_id, &mac_enable);

#endif

	return rv;
}
#ifndef IN_PORTCONTROL_MINI
sw_error_t
adpt_hppe_port_rxmac_status_get(a_uint32_t dev_id, fal_port_t port_id,
				      a_bool_t * enable)
{
	sw_error_t rv = SW_OK;
	a_uint32_t port_rxmac_status = 0, port_mac_type;

	ADPT_DEV_ID_CHECK(dev_id);
	ADPT_NULL_POINT_CHECK(enable);

	port_mac_type = qca_hppe_port_mac_type_get(dev_id, port_id);
	if (port_mac_type == PORT_XGMAC_TYPE)
		_adpt_xgmac_port_rx_status_get( dev_id, port_id, &port_rxmac_status);
	else if (port_mac_type == PORT_GMAC_TYPE)
		 _adpt_gmac_port_rx_status_get( dev_id, port_id, &port_rxmac_status);
	else
		return SW_BAD_VALUE;

	if (port_rxmac_status)
		*enable = A_TRUE;
	else
		*enable = A_FALSE;

	return rv;
}

sw_error_t
adpt_hppe_port_cdt(a_uint32_t dev_id, fal_port_t port_id,
		a_uint32_t mdi_pair, fal_cable_status_t * cable_status,
		a_uint32_t * cable_len)
{

	sw_error_t rv = 0;
	a_uint32_t phy_id = 0;
	hsl_phy_ops_t *phy_drv;

	ADPT_DEV_ID_CHECK(dev_id);
	ADPT_NULL_POINT_CHECK(cable_status);
	ADPT_NULL_POINT_CHECK(cable_len);

	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
	  {
		return SW_BAD_PARAM;
	  }
	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
		return SW_NOT_SUPPORTED;

	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
	if (NULL == phy_drv->phy_cdt)
		return SW_NOT_SUPPORTED;

	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
	SW_RTN_ON_ERROR (rv);

	rv = phy_drv->phy_cdt (dev_id, phy_id, mdi_pair, cable_status, cable_len);

	return rv;

}
#endif
sw_error_t
adpt_hppe_port_txmac_status_set(a_uint32_t dev_id, fal_port_t port_id,
				      a_bool_t enable)
{
	a_uint32_t port_mac_type;

	ADPT_DEV_ID_CHECK(dev_id);

	port_mac_type =qca_hppe_port_mac_type_get(dev_id, port_id);
	if (port_mac_type == PORT_XGMAC_TYPE)
		_adpt_xgmac_port_tx_status_set( dev_id, port_id, enable);
	else if (port_mac_type == PORT_GMAC_TYPE)
		_adpt_gmac_port_tx_status_set( dev_id, port_id, enable);
	else
		return SW_BAD_VALUE;

	return SW_OK;
}
#ifndef IN_PORTCONTROL_MINI
sw_error_t
adpt_hppe_port_combo_fiber_mode_set(a_uint32_t dev_id,
						  a_uint32_t port_id,
						  fal_port_fiber_mode_t mode)
{

	sw_error_t rv = 0;
	a_uint32_t phy_id = 0;
	hsl_phy_ops_t *phy_drv;

	ADPT_DEV_ID_CHECK(dev_id);

	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
	  {
		return SW_BAD_PARAM;
	  }
	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
		return SW_NOT_SUPPORTED;

	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
	if (NULL == phy_drv->phy_combo_fiber_mode_set)
		return SW_NOT_SUPPORTED;

	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
	SW_RTN_ON_ERROR (rv);

	rv = phy_drv->phy_combo_fiber_mode_set (dev_id, phy_id, mode);

	return rv;

}
sw_error_t
adpt_hppe_port_combo_medium_status_get(a_uint32_t dev_id,
						     a_uint32_t port_id,
						     fal_port_medium_t *
						     medium)
{

	sw_error_t rv = 0;
	a_uint32_t phy_id = 0;
	hsl_phy_ops_t *phy_drv;

	ADPT_DEV_ID_CHECK(dev_id);
	ADPT_NULL_POINT_CHECK(medium);

	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
	  {
		return SW_BAD_PARAM;
	  }
	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
		return SW_NOT_SUPPORTED;

	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
	if (NULL == phy_drv->phy_combo_medium_status_get)
		return SW_NOT_SUPPORTED;

	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
	SW_RTN_ON_ERROR (rv);

	rv = phy_drv->phy_combo_medium_status_get (dev_id, phy_id, medium);

	return rv;

}

sw_error_t
adpt_hppe_port_magic_frame_mac_set(a_uint32_t dev_id, fal_port_t port_id,
				   fal_mac_addr_t * mac)
{
	sw_error_t rv;
	a_uint32_t phy_id = 0;
	hsl_phy_ops_t *phy_drv;

	ADPT_DEV_ID_CHECK(dev_id);
	ADPT_NULL_POINT_CHECK(mac);

	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
	  {
		return SW_BAD_PARAM;
	  }
	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
		return SW_NOT_SUPPORTED;

	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
	if (NULL == phy_drv->phy_magic_frame_mac_set)
		return SW_NOT_SUPPORTED;

	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
	SW_RTN_ON_ERROR (rv);

	rv = phy_drv->phy_magic_frame_mac_set (dev_id, phy_id,mac);

	return rv;

}
sw_error_t
adpt_hppe_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id,
			  a_bool_t enable)
{
	sw_error_t rv = 0;
	a_uint32_t phy_id = 0;
	hsl_phy_ops_t *phy_drv;

	ADPT_DEV_ID_CHECK(dev_id);

	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
	  {
		return SW_BAD_PARAM;
	  }
	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
		return SW_NOT_SUPPORTED;

	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
	if (NULL == phy_drv->phy_powersave_set)
		return SW_NOT_SUPPORTED;

	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
	SW_RTN_ON_ERROR (rv);

	rv = phy_drv->phy_powersave_set (dev_id, phy_id, enable);

	return rv;

}
sw_error_t
adpt_hppe_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id,
			  a_bool_t enable)
{

	sw_error_t rv = 0;
	a_uint32_t phy_id = 0;
	hsl_phy_ops_t *phy_drv;

	ADPT_DEV_ID_CHECK(dev_id);

	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
	  {
		return SW_BAD_PARAM;
	  }
	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
		return SW_NOT_SUPPORTED;

	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
	if (NULL == phy_drv->phy_hibernation_set)
		return SW_NOT_SUPPORTED;

	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
	SW_RTN_ON_ERROR (rv);

	rv = phy_drv->phy_hibernation_set (dev_id, phy_id, enable);

	return rv;

}

sw_error_t
adpt_hppe_port_mru_set(a_uint32_t dev_id, fal_port_t port_id,
		fal_mru_ctrl_t *ctrl)
{
	ADPT_DEV_ID_CHECK(dev_id);
	ADPT_NULL_POINT_CHECK(ctrl);

	hppe_mru_mtu_ctrl_tbl_mru_set(dev_id, port_id, ctrl->mru_size);
	hppe_mru_mtu_ctrl_tbl_mru_cmd_set(dev_id, port_id, (a_uint32_t)ctrl->action);

	return SW_OK;
}

sw_error_t
adpt_ppe_port_mru_set(a_uint32_t dev_id, fal_port_t port_id,
		fal_mru_ctrl_t *ctrl)
{
	a_uint32_t chip_ver = 0;

	ADPT_DEV_ID_CHECK(dev_id);
	ADPT_NULL_POINT_CHECK(ctrl);

	chip_ver = adpt_hppe_chip_revision_get(dev_id);
	if (chip_ver == CPPE_REVISION) {
#if defined(CPPE)
		return adpt_cppe_port_mru_set(dev_id, port_id, ctrl);
#endif
	} else {
		return adpt_hppe_port_mru_set(dev_id, port_id, ctrl);
	}

	return SW_NOT_SUPPORTED;
}

sw_error_t
adpt_hppe_port_mtu_set(a_uint32_t dev_id, fal_port_t port_id,
		fal_mtu_ctrl_t *ctrl)
{
	union mru_mtu_ctrl_tbl_u mru_mtu_ctrl_tbl;

	memset(&mru_mtu_ctrl_tbl, 0, sizeof(mru_mtu_ctrl_tbl));
	ADPT_DEV_ID_CHECK(dev_id);
	ADPT_NULL_POINT_CHECK(ctrl);

	hppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &mru_mtu_ctrl_tbl);
	mru_mtu_ctrl_tbl.bf.mtu = ctrl->mtu_size;
	mru_mtu_ctrl_tbl.bf.mtu_cmd = (a_uint32_t)ctrl->action;
	hppe_mru_mtu_ctrl_tbl_set(dev_id, port_id, &mru_mtu_ctrl_tbl);

	if ((port_id >= SSDK_PHYSICAL_PORT0) && (port_id <= SSDK_PHYSICAL_PORT7))
	{
		hppe_mc_mtu_ctrl_tbl_mtu_set(dev_id, port_id, ctrl->mtu_size);
		hppe_mc_mtu_ctrl_tbl_mtu_cmd_set(dev_id, port_id, (a_uint32_t)ctrl->action);
	}

	return SW_OK;
}

sw_error_t
adpt_ppe_port_mtu_set(a_uint32_t dev_id, fal_port_t port_id,
		fal_mtu_ctrl_t *ctrl)
{
	a_uint32_t chip_ver = 0;

	ADPT_DEV_ID_CHECK(dev_id);
	ADPT_NULL_POINT_CHECK(ctrl);

	chip_ver = adpt_hppe_chip_revision_get(dev_id);
	if (chip_ver == CPPE_REVISION) {
#if defined(CPPE)
		return adpt_cppe_port_mtu_set(dev_id, port_id, ctrl);
#endif
	} else {
		return adpt_hppe_port_mtu_set(dev_id, port_id, ctrl);
	}

	return SW_NOT_SUPPORTED;
}
#endif

sw_error_t
adpt_hppe_port_max_frame_size_set(a_uint32_t dev_id, fal_port_t port_id,
		a_uint32_t max_frame)
{
	a_uint32_t port_mac_type = 0;
	sw_error_t rv = SW_OK;

	ADPT_DEV_ID_CHECK(dev_id);

	if (max_frame > SSDK_MAX_FRAME_SIZE) {
		return SW_BAD_VALUE;
	}

	port_mac_type =qca_hppe_port_mac_type_get(dev_id, port_id);
	if (port_mac_type == PORT_XGMAC_TYPE)
		rv |= _adpt_xgmac_port_max_frame_size_set( dev_id, port_id, max_frame);
	else if (port_mac_type == PORT_GMAC_TYPE)
	{
		/*for gmac, rxtoolong have counters when package length is longer than jumbo size and shorter than max frame size,
		   when package length is longer than max frame size, the rxbadbyte have counters.*/
		rv |= _adpt_hppe_port_jumbo_size_set(dev_id, port_id, max_frame);
		rv |= _adpt_gmac_port_max_frame_size_set( dev_id, port_id, max_frame);
	}
	else
		return SW_BAD_VALUE;

	return rv;
}

sw_error_t
adpt_ppe_port_max_frame_size_set(a_uint32_t dev_id, fal_port_t port_id,
		a_uint32_t max_frame)
{
#ifdef CPPE
	if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION &&
		port_id == SSDK_PHYSICAL_PORT6)
	{
		return adpt_cppe_lpbk_max_frame_size_set(dev_id, port_id, max_frame);
	}
#endif
	return adpt_hppe_port_max_frame_size_set(dev_id, port_id, max_frame);
}

#ifndef IN_PORTCONTROL_MINI
sw_error_t
adpt_hppe_port_8023az_get(a_uint32_t dev_id, fal_port_t port_id,
				a_bool_t * enable)
{

	sw_error_t rv = 0;
	a_uint32_t phy_id = 0;
	hsl_phy_ops_t *phy_drv;

	ADPT_DEV_ID_CHECK(dev_id);
	ADPT_NULL_POINT_CHECK(enable);

	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
	  {
		return SW_BAD_PARAM;
	  }
	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
		return SW_NOT_SUPPORTED;

	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
	if (NULL == phy_drv->phy_8023az_get)
		return SW_NOT_SUPPORTED;

	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
	SW_RTN_ON_ERROR (rv);

	rv = phy_drv->phy_8023az_get (dev_id, phy_id, enable);

	return rv;

}
#endif
sw_error_t
adpt_hppe_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id,
				     a_bool_t * enable)
{
	sw_error_t rv = SW_OK;
	a_uint32_t rxfc_status = 0, port_mac_type;

	ADPT_DEV_ID_CHECK(dev_id);
	ADPT_NULL_POINT_CHECK(enable);

	port_mac_type =qca_hppe_port_mac_type_get(dev_id, port_id);
	if (port_mac_type == PORT_XGMAC_TYPE)
		_adpt_xgmac_port_rxfc_status_get( dev_id, port_id, &rxfc_status);
	else if (port_mac_type == PORT_GMAC_TYPE)
		_adpt_gmac_port_rxfc_status_get( dev_id, port_id, &rxfc_status);
	else
		return SW_BAD_VALUE;

	if (rxfc_status)
		*enable = A_TRUE;
	else
		*enable = A_FALSE;

	return rv;
}

sw_error_t
adpt_hppe_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id,
				     a_bool_t * enable)
{
	a_uint32_t txfc_status = 0, port_mac_type;

	ADPT_DEV_ID_CHECK(dev_id);
	ADPT_NULL_POINT_CHECK(enable);

	port_mac_type =qca_hppe_port_mac_type_get(dev_id, port_id);
	if (port_mac_type == PORT_XGMAC_TYPE)
		_adpt_xgmac_port_txfc_status_get( dev_id, port_id, &txfc_status);
	else if (port_mac_type == PORT_GMAC_TYPE)
		_adpt_gmac_port_txfc_status_get( dev_id, port_id, &txfc_status);
	else
		return SW_BAD_VALUE;

	if (txfc_status)
		*enable = A_TRUE;
	else
		*enable = A_FALSE;

	return SW_OK;
}
#ifndef IN_PORTCONTROL_MINI
sw_error_t
adpt_hppe_port_remote_loopback_set(a_uint32_t dev_id, fal_port_t port_id,
					 a_bool_t enable)
{

	sw_error_t rv = 0;
	a_uint32_t phy_id = 0;
	hsl_phy_ops_t *phy_drv;

	ADPT_DEV_ID_CHECK(dev_id);

	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
	  {
		return SW_BAD_PARAM;
	  }
	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
		return SW_NOT_SUPPORTED;

	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
	if (NULL == phy_drv->phy_remote_loopback_set)
		return SW_NOT_SUPPORTED;

	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
	SW_RTN_ON_ERROR (rv);

	rv = phy_drv->phy_remote_loopback_set (dev_id, phy_id, enable);

	return rv;

}
#endif
sw_error_t
adpt_hppe_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
					a_bool_t * status)
{

	a_uint32_t phy_id = 0;
	sw_error_t rv = 0;
	hsl_phy_ops_t *phy_drv;

	ADPT_DEV_ID_CHECK(dev_id);
	ADPT_NULL_POINT_CHECK(status);

	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
	  {
		return SW_BAD_PARAM;
	  }
	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
		return SW_NOT_SUPPORTED;

	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
	if (NULL == phy_drv->phy_autoneg_status_get)
		return SW_NOT_SUPPORTED;

	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
	SW_RTN_ON_ERROR (rv);

	*status = phy_drv->phy_autoneg_status_get (dev_id, phy_id);

	return SW_OK;

}
#ifndef IN_PORTCONTROL_MINI
sw_error_t
adpt_hppe_port_txmac_status_get(a_uint32_t dev_id, fal_port_t port_id,
				      a_bool_t * enable)
{
	sw_error_t rv = SW_OK;
	a_uint32_t port_txmac_status = 0, port_mac_type;

	ADPT_DEV_ID_CHECK(dev_id);
	ADPT_NULL_POINT_CHECK(enable);

	port_mac_type =qca_hppe_port_mac_type_get(dev_id, port_id);
	if (port_mac_type == PORT_XGMAC_TYPE)
		_adpt_xgmac_port_tx_status_get( dev_id, port_id, &port_txmac_status);
	else if (port_mac_type == PORT_GMAC_TYPE)
		_adpt_gmac_port_tx_status_get( dev_id, port_id, &port_txmac_status);
	else
		return SW_BAD_VALUE;

	if (port_txmac_status)
		*enable = A_TRUE;
	else
		*enable = A_FALSE;

	return rv;
}

sw_error_t
adpt_hppe_port_mdix_get(a_uint32_t dev_id, fal_port_t port_id,
			      fal_port_mdix_mode_t * mode)
{

	sw_error_t rv = 0;
	a_uint32_t phy_id = 0;
	hsl_phy_ops_t *phy_drv;

	ADPT_DEV_ID_CHECK(dev_id);
	ADPT_NULL_POINT_CHECK(mode);

	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
	  {
		return SW_BAD_PARAM;
	  }
	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
		return SW_NOT_SUPPORTED;

	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
	if (NULL == phy_drv->phy_mdix_get)
		return SW_NOT_SUPPORTED;

	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
	SW_RTN_ON_ERROR (rv);

	rv = phy_drv->phy_mdix_get (dev_id, phy_id, mode);

	return rv;

}

sw_error_t
adpt_hppe_ports_link_status_get(a_uint32_t dev_id, a_uint32_t * status)
{

	sw_error_t rv = 0;
	a_uint32_t port_id;
	a_uint32_t phy_id;
	hsl_dev_t *pdev = NULL;
	hsl_phy_ops_t *phy_drv;
	struct port_phy_status phy_status = {0};

	ADPT_DEV_ID_CHECK(dev_id);
	ADPT_NULL_POINT_CHECK(status);

	pdev = hsl_dev_ptr_get(dev_id);
	if (pdev == NULL)
		return SW_NOT_INITIALIZED;

	*status = 0x0;
	for (port_id = 0; port_id < SW_MAX_NR_PORT; port_id++)
	{
		/* for those ports without PHY device should be sfp port */
		if (A_FALSE == _adpt_hppe_port_phy_connected(dev_id, port_id))
		{
			if (hsl_port_prop_check(dev_id, port_id, HSL_PP_CPU) ||
				hsl_port_prop_check(dev_id, port_id, HSL_PP_INNER))
			{
				*status |= (0x1 << port_id);
			}
			else
			{
				if(!hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
				{
					continue;
				}
				rv = _adpt_phy_status_get_from_ppe(dev_id,
					port_id, &phy_status);
				SW_RTN_ON_ERROR (rv);

				if (phy_status.link_status == PORT_LINK_UP)
				{
					*status |= (0x1 << port_id);
				}
				else
				{
					*status &= ~(0x1 << port_id);
				}
			}
		}
		else
		{
			SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
			if (NULL == phy_drv->phy_link_status_get)
			{
				return SW_NOT_SUPPORTED;
			}
			rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
			SW_RTN_ON_ERROR(rv);

			if (A_TRUE == phy_drv->phy_link_status_get (dev_id, phy_id))
			{
				*status |= (0x1 << port_id);
			}
			else
			{
				*status &= ~(0x1 << port_id);
			}
		}
	}
	return SW_OK;

}

sw_error_t
adpt_hppe_port_mac_loopback_set(a_uint32_t dev_id, fal_port_t port_id,
				 a_bool_t enable)
{
	sw_error_t rv = SW_OK;
	a_uint32_t port_mac_type = 0;

	ADPT_DEV_ID_CHECK(dev_id);
	port_mac_type = qca_hppe_port_mac_type_get(dev_id, port_id);
	if (port_mac_type == PORT_XGMAC_TYPE)
		rv = _adpt_hppe_port_xgmac_loopback_set( dev_id, port_id, enable);
	else if(port_mac_type == PORT_GMAC_TYPE)
		rv =  _adpt_hppe_port_gmac_loopback_set( dev_id, port_id, enable);
	else
		return SW_BAD_VALUE;

	return rv;
}

sw_error_t
adpt_hppe_port_phy_id_get(a_uint32_t dev_id, fal_port_t port_id,
		      a_uint16_t * org_id, a_uint16_t * rev_id)
{
	sw_error_t rv = 0;
	a_uint32_t phy_id = 0;
	hsl_phy_ops_t *phy_drv;
	a_uint32_t phy_data;

	ADPT_DEV_ID_CHECK(dev_id);
	ADPT_NULL_POINT_CHECK(org_id);
	ADPT_NULL_POINT_CHECK(rev_id);

	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
	{
		return SW_BAD_PARAM;
	}
	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
		return SW_NOT_SUPPORTED;

	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
	if (NULL == phy_drv->phy_id_get)
		return SW_NOT_SUPPORTED;

	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
	SW_RTN_ON_ERROR (rv);

	rv = phy_drv->phy_id_get (dev_id, phy_id, &phy_data);
	SW_RTN_ON_ERROR (rv);

	*org_id = (phy_data >> 16) & 0xffff;
	*rev_id = phy_data & 0xffff;

	return rv;

}
sw_error_t
adpt_hppe_port_mru_get(a_uint32_t dev_id, fal_port_t port_id,
		fal_mru_ctrl_t *ctrl)
{
	sw_error_t rv = SW_OK;
	union mru_mtu_ctrl_tbl_u mru_mtu_ctrl_tbl;

	memset(&mru_mtu_ctrl_tbl, 0, sizeof(mru_mtu_ctrl_tbl));
	ADPT_DEV_ID_CHECK(dev_id);
	ADPT_NULL_POINT_CHECK(ctrl);

	rv = hppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &mru_mtu_ctrl_tbl);

	if( rv != SW_OK )
		return rv;

	ctrl->mru_size = mru_mtu_ctrl_tbl.bf.mru;
	ctrl->action = (fal_fwd_cmd_t)mru_mtu_ctrl_tbl.bf.mru_cmd;

	return SW_OK;
}

sw_error_t
adpt_ppe_port_mru_get(a_uint32_t dev_id, fal_port_t port_id,
		fal_mru_ctrl_t *ctrl)
{
	a_uint32_t chip_ver = 0;

	ADPT_DEV_ID_CHECK(dev_id);
	ADPT_NULL_POINT_CHECK(ctrl);

	chip_ver = adpt_hppe_chip_revision_get(dev_id);
	if (chip_ver == CPPE_REVISION) {
#if defined(CPPE)
		return adpt_cppe_port_mru_get(dev_id, port_id, ctrl);
#endif
	} else {
		return adpt_hppe_port_mru_get(dev_id, port_id, ctrl);
	}

	return SW_NOT_SUPPORTED;
}
#endif

sw_error_t
adpt_hppe_port_power_on(a_uint32_t dev_id, fal_port_t port_id)
{

	sw_error_t rv = 0;
	a_uint32_t phy_id = 0;
	hsl_phy_ops_t *phy_drv;

	ADPT_DEV_ID_CHECK(dev_id);

	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
	  {
		return SW_BAD_PARAM;
	  }
	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
		return SW_NOT_SUPPORTED;

	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
	if (NULL == phy_drv->phy_power_on)
		return SW_NOT_SUPPORTED;

	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
	SW_RTN_ON_ERROR (rv);

	rv = phy_drv->phy_power_on(dev_id, phy_id);

	return rv;

}
sw_error_t
adpt_hppe_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
			       fal_port_speed_t speed)
{
	sw_error_t rv = 0;
	a_uint32_t phy_id = 0;
	hsl_phy_ops_t *phy_drv;

	ADPT_DEV_ID_CHECK(dev_id);

	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU))
	  {
		return SW_BAD_PARAM;
	  }
	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
		return SW_NOT_SUPPORTED;

	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
	if (NULL == phy_drv->phy_speed_set)
		return SW_NOT_SUPPORTED;

	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
	SW_RTN_ON_ERROR (rv);

	rv = phy_drv->phy_speed_set (dev_id, phy_id, speed);
	SW_RTN_ON_ERROR (rv);

	return rv;
}
sw_error_t
adpt_hppe_port_interface_mode_get(a_uint32_t dev_id, fal_port_t port_id,
			      fal_port_interface_mode_t * mode)
{
	sw_error_t rv = 0;
	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_EXCL_CPU))
	{
		return SW_BAD_PARAM;
	}
	*mode = port_interface_mode[dev_id][port_id];

	return rv;
}

sw_error_t
adpt_hppe_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
				fal_port_duplex_t * pduplex)
{
	sw_error_t rv = 0;
	a_uint32_t phy_id = 0;
	hsl_phy_ops_t *phy_drv;
	struct port_phy_status phy_status = {0};

	ADPT_DEV_ID_CHECK(dev_id);
	ADPT_NULL_POINT_CHECK(pduplex);

	if (port_id == SSDK_PHYSICAL_PORT0 || port_id == SSDK_PHYSICAL_PORT7)
	{
		*pduplex = FAL_FULL_DUPLEX;
		return SW_OK;
	}

	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU))
	{
		return SW_BAD_PARAM;
	}

	/* for those ports without PHY device should be sfp port */
	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
	{

		rv = _adpt_phy_status_get_from_ppe(dev_id,
			port_id, &phy_status);
		SW_RTN_ON_ERROR (rv);
		*pduplex = phy_status.duplex;

	}
	else
	{
		SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
		if (NULL == phy_drv->phy_duplex_get)
			return SW_NOT_SUPPORTED;

		rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
		SW_RTN_ON_ERROR (rv);
		rv = phy_drv->phy_duplex_get (dev_id, phy_id, pduplex);
		SW_RTN_ON_ERROR (rv);
	}

	return rv;
}

sw_error_t
adpt_hppe_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
				     a_uint32_t * autoadv)
{

	sw_error_t rv = 0;
	a_uint32_t phy_id;
	hsl_phy_ops_t *phy_drv;

	ADPT_DEV_ID_CHECK(dev_id);
	ADPT_NULL_POINT_CHECK(autoadv);

	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
	  {
		return SW_BAD_PARAM;
	  }
	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
		return SW_NOT_SUPPORTED;

	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
	if (NULL == phy_drv->phy_autoneg_adv_get)
		return SW_NOT_SUPPORTED;

	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
	SW_RTN_ON_ERROR (rv);

	*autoadv = 0;
	rv = phy_drv->phy_autoneg_adv_get (dev_id, phy_id, autoadv);
	SW_RTN_ON_ERROR (rv);

	return SW_OK;

}
#ifndef IN_PORTCONTROL_MINI
sw_error_t
adpt_hppe_port_mdix_status_get(a_uint32_t dev_id, fal_port_t port_id,
				     fal_port_mdix_status_t * mode)
{

	sw_error_t rv = 0;
	a_uint32_t phy_id = 0;
	hsl_phy_ops_t *phy_drv;

	ADPT_DEV_ID_CHECK(dev_id);
	ADPT_NULL_POINT_CHECK(mode);

	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
	  {
		return SW_BAD_PARAM;
	  }
	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
		return SW_NOT_SUPPORTED;

	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
	if (NULL == phy_drv->phy_mdix_status_get)
		return SW_NOT_SUPPORTED;

	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
	SW_RTN_ON_ERROR (rv);

	rv = phy_drv->phy_mdix_status_get (dev_id, phy_id, mode);

	return rv;

}
#endif
sw_error_t
adpt_hppe_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id,
				     a_bool_t * status)
{

	sw_error_t rv = 0;
	a_uint32_t phy_id;
	hsl_phy_ops_t *phy_drv;
	struct port_phy_status phy_status = {0};

	ADPT_DEV_ID_CHECK(dev_id);
	ADPT_NULL_POINT_CHECK(status);

	if (port_id == SSDK_PHYSICAL_PORT0 || port_id == SSDK_PHYSICAL_PORT7)
	{
		*status = A_TRUE;
		return SW_OK;
	}
	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU))
	{
		return SW_BAD_PARAM;
	}

	/* for those ports without PHY device should be sfp port */
	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
	{
		rv = _adpt_phy_status_get_from_ppe(dev_id,
			port_id, &phy_status);
		SW_RTN_ON_ERROR (rv);
		*status = (a_bool_t) phy_status.link_status;
	}
	else
	{
		SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
		if (NULL == phy_drv->phy_link_status_get)
			return SW_NOT_SUPPORTED;

		rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
		SW_RTN_ON_ERROR (rv);

		if (A_TRUE == phy_drv->phy_link_status_get (dev_id, phy_id))
		{
			*status = A_TRUE;
		}
		else
		{
			*status = A_FALSE;
		}
	}

	return SW_OK;

}
#ifndef IN_PORTCONTROL_MINI
sw_error_t
adpt_hppe_port_8023az_set(a_uint32_t dev_id, fal_port_t port_id,
				a_bool_t enable)
{

	sw_error_t rv = 0;
	a_uint32_t phy_id = 0;
	hsl_phy_ops_t *phy_drv;

	ADPT_DEV_ID_CHECK(dev_id);

	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
	  {
		return SW_BAD_PARAM;
	  }
	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
		return SW_NOT_SUPPORTED;

	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
	if (NULL == phy_drv->phy_8023az_set)
		return SW_NOT_SUPPORTED;

	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
	SW_RTN_ON_ERROR (rv);

	rv = phy_drv->phy_8023az_set (dev_id, phy_id, enable);

	return rv;

}
sw_error_t
adpt_hppe_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id,
			  a_bool_t * enable)
{

	sw_error_t rv = 0;
	a_uint32_t phy_id = 0;
	hsl_phy_ops_t *phy_drv;

	ADPT_DEV_ID_CHECK(dev_id);
	ADPT_NULL_POINT_CHECK(enable);

	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
	  {
		return SW_BAD_PARAM;
	  }
	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
		return SW_NOT_SUPPORTED;

	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
	if (NULL == phy_drv->phy_powersave_get)
		return SW_NOT_SUPPORTED;

	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
	SW_RTN_ON_ERROR (rv);

	rv = phy_drv->phy_powersave_get (dev_id, phy_id, enable);

	return rv;

}

sw_error_t
adpt_hppe_port_combo_prefer_medium_get(a_uint32_t dev_id,
						     a_uint32_t port_id,
						     fal_port_medium_t *
						     medium)
{
	sw_error_t rv = 0;
	a_uint32_t phy_id = 0;
	hsl_phy_ops_t *phy_drv;

	ADPT_DEV_ID_CHECK(dev_id);
	ADPT_NULL_POINT_CHECK(medium);

	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
	  {
		return SW_BAD_PARAM;
	  }
	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
		return SW_NOT_SUPPORTED;

	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
	if (NULL == phy_drv->phy_combo_prefer_medium_get)
		return SW_NOT_SUPPORTED;

	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
	SW_RTN_ON_ERROR (rv);

	rv = phy_drv->phy_combo_prefer_medium_get (dev_id, phy_id, medium);

	return rv;

}
#endif
sw_error_t
adpt_hppe_port_max_frame_size_get(a_uint32_t dev_id, fal_port_t port_id,
		a_uint32_t *max_frame)
{
	sw_error_t rv = SW_OK;
	a_uint32_t port_mac_type = 0;

	ADPT_DEV_ID_CHECK(dev_id);
	ADPT_NULL_POINT_CHECK(max_frame);

	port_mac_type =qca_hppe_port_mac_type_get(dev_id, port_id);
	if (port_mac_type == PORT_XGMAC_TYPE)
	{
		rv = _adpt_xgmac_port_max_frame_size_get( dev_id, port_id, max_frame);
	}
	else if (port_mac_type == PORT_GMAC_TYPE)
	{
		rv = _adpt_gmac_port_max_frame_size_get( dev_id, port_id, max_frame);
	}
	else
	{
		return SW_BAD_VALUE;
	}

	return rv;
}

sw_error_t
adpt_ppe_port_max_frame_size_get(a_uint32_t dev_id, fal_port_t port_id,
		a_uint32_t *max_frame)
{
#ifdef CPPE
	if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION &&
		port_id == SSDK_PHYSICAL_PORT6)
	{
		return adpt_cppe_lpbk_max_frame_size_get(dev_id, port_id, max_frame);
	}
#endif
	return adpt_hppe_port_max_frame_size_get(dev_id, port_id, max_frame);

}

#ifndef IN_PORTCONTROL_MINI
sw_error_t
adpt_hppe_port_combo_prefer_medium_set(a_uint32_t dev_id,
					     a_uint32_t port_id,
					     fal_port_medium_t medium)
{

	sw_error_t rv = 0;
	a_uint32_t phy_id = 0;
	hsl_phy_ops_t *phy_drv;

	ADPT_DEV_ID_CHECK(dev_id);

	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
	  {
		return SW_BAD_PARAM;
	  }
	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
		return SW_NOT_SUPPORTED;

	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
	if (NULL == phy_drv->phy_combo_prefer_medium_set)
		return SW_NOT_SUPPORTED;

	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
	SW_RTN_ON_ERROR (rv);

	rv = phy_drv->phy_combo_prefer_medium_set (dev_id, phy_id, medium);

	return rv;

}
#endif
sw_error_t
adpt_hppe_port_power_off(a_uint32_t dev_id, fal_port_t port_id)
{

	sw_error_t rv = 0;
	a_uint32_t phy_id = 0;
	hsl_phy_ops_t *phy_drv;

	ADPT_DEV_ID_CHECK(dev_id);

	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
	  {
		return SW_BAD_PARAM;
	  }
	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
		return SW_NOT_SUPPORTED;

	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
	if (NULL == phy_drv->phy_power_off)
		return SW_NOT_SUPPORTED;

	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
	SW_RTN_ON_ERROR (rv);

	rv = phy_drv->phy_power_off(dev_id, phy_id);

	return rv;

}
sw_error_t
adpt_hppe_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id,
				     a_bool_t enable)
{
	sw_error_t rv = SW_OK;
	a_uint32_t port_mac_type;
	struct qca_phy_priv *priv = ssdk_phy_priv_data_get(dev_id);
	adpt_api_t *p_adpt_api;

	ADPT_DEV_ID_CHECK(dev_id);

	if (!priv)
		return SW_FAIL;

	if ((port_id < SSDK_PHYSICAL_PORT1) || (port_id > SSDK_PHYSICAL_PORT6))
		return SW_BAD_VALUE;

	port_mac_type =qca_hppe_port_mac_type_get(dev_id, port_id);
	if (port_mac_type == PORT_XGMAC_TYPE)
		rv = _adpt_xgmac_port_txfc_status_set( dev_id, port_id, enable);
	else if (port_mac_type == PORT_GMAC_TYPE)
		rv = _adpt_gmac_port_txfc_status_set( dev_id, port_id, enable);
	else
		return SW_BAD_VALUE;

	if (rv != SW_OK)
		return rv;

	priv->port_old_tx_flowctrl[port_id - 1] = enable;

	/*keep bm status same with port*/
	p_adpt_api = adpt_api_ptr_get(dev_id);
	if (p_adpt_api && p_adpt_api->adpt_port_bm_ctrl_set)
		rv = p_adpt_api->adpt_port_bm_ctrl_set(dev_id,
					PHY_PORT_TO_BM_PORT(port_id),
					enable);

	return rv;
}

sw_error_t
adpt_hppe_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id,
				     a_bool_t enable)
{
	sw_error_t rv = SW_OK;
	a_uint32_t port_mac_type;
	struct qca_phy_priv *priv = ssdk_phy_priv_data_get(dev_id);

	ADPT_DEV_ID_CHECK(dev_id);

	if (!priv)
		return SW_FAIL;

	if ((port_id < SSDK_PHYSICAL_PORT1) || (port_id > SSDK_PHYSICAL_PORT6))
		return SW_BAD_VALUE;

	port_mac_type =qca_hppe_port_mac_type_get(dev_id, port_id);
	if(port_mac_type == PORT_XGMAC_TYPE)
		rv = _adpt_xgmac_port_rxfc_status_set( dev_id, port_id, enable);
	else if (port_mac_type == PORT_GMAC_TYPE)
		rv = _adpt_gmac_port_rxfc_status_set( dev_id, port_id, enable);
	else
		return SW_BAD_VALUE;

	if (rv != SW_OK)
		return rv;

	priv->port_old_rx_flowctrl[port_id - 1] = enable;

	return SW_OK;
}

#ifndef IN_PORTCONTROL_MINI
sw_error_t
adpt_hppe_port_counter_set(a_uint32_t dev_id, fal_port_t port_id,
		   a_bool_t enable)
{

	sw_error_t rv = 0;
	a_uint32_t phy_id = 0;
	hsl_phy_ops_t *phy_drv;

	ADPT_DEV_ID_CHECK(dev_id);

	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
	  {
		return SW_BAD_PARAM;
	  }
	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
		return SW_NOT_SUPPORTED;

	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
	if (NULL == phy_drv->phy_counter_set)
		return SW_NOT_SUPPORTED;

	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
	SW_RTN_ON_ERROR (rv);

	rv = phy_drv->phy_counter_set (dev_id, phy_id, enable);

	return rv;
}
sw_error_t
adpt_hppe_port_combo_fiber_mode_get(a_uint32_t dev_id,
						  a_uint32_t port_id,
						  fal_port_fiber_mode_t * mode)
{
	sw_error_t rv = 0;
	a_uint32_t phy_id = 0;
	hsl_phy_ops_t *phy_drv;

	ADPT_DEV_ID_CHECK(dev_id);
	ADPT_NULL_POINT_CHECK(mode);

	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
	  {
	  	return SW_BAD_PARAM;
	  }
	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
		return SW_NOT_SUPPORTED;

	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
	if (NULL == phy_drv->phy_combo_fiber_mode_get)
		return SW_NOT_SUPPORTED;

	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
	SW_RTN_ON_ERROR (rv);

	rv = phy_drv->phy_combo_fiber_mode_get (dev_id, phy_id, mode);

	return rv;

}

sw_error_t
adpt_hppe_port_local_loopback_set(a_uint32_t dev_id,
						fal_port_t port_id,
						a_bool_t enable)
{

	sw_error_t rv = 0;
	a_uint32_t phy_id = 0;
	hsl_phy_ops_t *phy_drv;

	ADPT_DEV_ID_CHECK(dev_id);

	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
	  {
		return SW_BAD_PARAM;
	  }
	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
		return SW_NOT_SUPPORTED;

	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
	if (NULL == phy_drv->phy_local_loopback_set)
		return SW_NOT_SUPPORTED;

	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
	SW_RTN_ON_ERROR (rv);

	rv = phy_drv->phy_local_loopback_set (dev_id, phy_id, enable);

	return rv;

}
sw_error_t
adpt_hppe_port_wol_status_set(a_uint32_t dev_id, fal_port_t port_id,
			      a_bool_t enable)
{

	sw_error_t rv = 0;
	a_uint32_t phy_id = 0;
	hsl_phy_ops_t *phy_drv;

	ADPT_DEV_ID_CHECK(dev_id);

	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
	{
		return SW_BAD_PARAM;
	}
	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
		return SW_NOT_SUPPORTED;

	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
	if (NULL == phy_drv->phy_wol_status_set)
		return SW_NOT_SUPPORTED;

	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
	SW_RTN_ON_ERROR (rv);

	rv = phy_drv->phy_wol_status_set (dev_id, phy_id, enable);

	return rv;


}
sw_error_t
adpt_hppe_port_magic_frame_mac_get(a_uint32_t dev_id, fal_port_t port_id,
				   fal_mac_addr_t * mac)
{

	sw_error_t rv;
	a_uint32_t phy_id = 0;
	hsl_phy_ops_t *phy_drv;

	ADPT_DEV_ID_CHECK(dev_id);
	ADPT_NULL_POINT_CHECK(mac);

	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
	  {
		return SW_BAD_PARAM;
	  }
	if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
		return SW_NOT_SUPPORTED;

	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
	if (NULL == phy_drv->phy_magic_frame_mac_get)
		return SW_NOT_SUPPORTED;

	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
	SW_RTN_ON_ERROR (rv);

	rv = phy_drv->phy_magic_frame_mac_get (dev_id, phy_id,mac);

	return rv;

}

sw_error_t
adpt_hppe_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id,
				  a_bool_t * enable)
{
	sw_error_t rv = SW_OK;
	a_bool_t txfc_enable, rxfc_enable;

#if defined(CPPE)
	if ((adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) &&
		(port_id == SSDK_PHYSICAL_PORT6)) {
		return adpt_cppe_switch_port_loopback_flowctrl_get(dev_id,
				port_id, enable);
	}
#endif
	rv = adpt_hppe_port_txfc_status_get(dev_id, port_id,  &txfc_enable);
	rv |= adpt_hppe_port_rxfc_status_get(dev_id, port_id,  &rxfc_enable);
	if(rv != SW_OK)
		return rv;
	*enable = txfc_enable & rxfc_enable;

	return SW_OK;
}
#endif
sw_error_t
adpt_hppe_port_rxmac_status_set(a_uint32_t dev_id, fal_port_t port_id,
				      a_bool_t enable)
{
	a_uint32_t port_mac_type;

	ADPT_DEV_ID_CHECK(dev_id);

	port_mac_type =qca_hppe_port_mac_type_get(dev_id, port_id);
	if (port_mac_type == PORT_XGMAC_TYPE)
		_adpt_xgmac_port_rx_status_set(dev_id, port_id, enable);
	else if (port_mac_type == PORT_GMAC_TYPE)
		_adpt_gmac_port_rx_status_set(dev_id, port_id, enable);
	else
		return SW_BAD_VALUE;

	return SW_OK;
}
#ifndef IN_PORTCONTROL_MINI
sw_error_t
adpt_hppe_port_counter_get(a_uint32_t dev_id, fal_port_t port_id,
		   a_bool_t * enable)
{

	sw_error_t rv;
	a_uint32_t phy_id = 0;
	hsl_phy_ops_t *phy_drv;

	ADPT_DEV_ID_CHECK(dev_id);
	ADPT_NULL_POINT_CHECK(enable);

	 if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
	   {
		return SW_BAD_PARAM;
	   }
	 if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id))
		 return SW_NOT_SUPPORTED;

	 SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
	 if (NULL == phy_drv->phy_counter_get)
		return SW_NOT_SUPPORTED;

	 rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
	 SW_RTN_ON_ERROR (rv);

	 rv = phy_drv->phy_counter_get (dev_id, phy_id, enable);

	 return rv;

}
#endif

static sw_error_t
_adpt_hppe_port_interface_mode_set(a_uint32_t dev_id, fal_port_t port_id,
			      fal_port_interface_mode_t mode)
{
	sw_error_t rv = SW_OK;

	ADPT_DEV_ID_CHECK(dev_id);
	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_EXCL_CPU) &&
		mode != PORT_INTERFACE_MODE_MAX)
	{
		return SW_BAD_PARAM;
	}

	port_interface_mode[dev_id][port_id] = mode;

	return rv;
}

sw_error_t
adpt_hppe_port_interface_mode_set(a_uint32_t dev_id, fal_port_t port_id,
			      fal_port_interface_mode_t mode)
{
	sw_error_t rv = SW_OK;
	struct qca_phy_priv *priv;

	priv = ssdk_phy_priv_data_get(dev_id);
	SW_RTN_ON_NULL(priv);
	qca_mac_sw_sync_work_stop(priv);

	rv = _adpt_hppe_port_interface_mode_set(dev_id, port_id, mode);

	return rv;
}

static sw_error_t
_adpt_hppe_gmac_speed_set(a_uint32_t dev_id, a_uint32_t port_id, fal_port_speed_t speed)
{
	sw_error_t rv = SW_OK;
	union mac_speed_u mac_speed;

	memset(&mac_speed, 0, sizeof(mac_speed));
	ADPT_DEV_ID_CHECK(dev_id);

	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
	hppe_mac_speed_get(dev_id, port_id, &mac_speed);

	if(FAL_SPEED_10 == speed)
		mac_speed.bf.mac_speed = MAC_SPEED_10M;
	else if(FAL_SPEED_100 == speed)
		mac_speed.bf.mac_speed = MAC_SPEED_100M;
	else if(FAL_SPEED_1000 == speed || FAL_SPEED_2500 == speed)
		mac_speed.bf.mac_speed = MAC_SPEED_1000M;

	rv = hppe_mac_speed_set(dev_id, port_id, &mac_speed);

	return rv;
}

static sw_error_t
_adpt_hppe_xgmac_speed_set(a_uint32_t dev_id, a_uint32_t port_id, fal_port_speed_t speed)
{
	sw_error_t rv = SW_OK;
	union mac_tx_configuration_u mac_tx_configuration;
	a_uint32_t mode = 0;

	memset(&mac_tx_configuration, 0, sizeof(mac_tx_configuration));
	ADPT_DEV_ID_CHECK(dev_id);

	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
	hppe_mac_tx_configuration_get(dev_id, port_id, &mac_tx_configuration);

	if(FAL_SPEED_1000 == speed)
	{
		mac_tx_configuration.bf.uss= XGMAC_USXGMII_CLEAR;
		mac_tx_configuration.bf.ss= XGMAC_SPEED_SELECT_1000M;
	}
	else if(FAL_SPEED_10000 == speed)
	{
		if (port_id == SSDK_PHYSICAL_PORT0)
		{
			mode = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE1);
		}
		else
		{
			mode = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE2);
		}
		if (mode == PORT_WRAPPER_USXGMII)
		{
			mac_tx_configuration.bf.uss= XGMAC_USXGMII_ENABLE;
			mac_tx_configuration.bf.ss= XGMAC_SPEED_SELECT_10000M;
		}
		else
		{
			mac_tx_configuration.bf.uss= XGMAC_USXGMII_CLEAR;
			mac_tx_configuration.bf.ss= XGMAC_SPEED_SELECT_10000M;
		}
	}
	else if(FAL_SPEED_5000 == speed)
	{
		mac_tx_configuration.bf.uss= XGMAC_USXGMII_ENABLE;
		mac_tx_configuration.bf.ss= XGMAC_SPEED_SELECT_5000M;
	}
	else if(FAL_SPEED_2500 == speed)
	{
		if (port_id == SSDK_PHYSICAL_PORT0)
		{
			mode = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE1);
		}
		else
		{
			mode = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE2);
		}
		if (mode == PORT_WRAPPER_USXGMII)
		{
			mac_tx_configuration.bf.uss= XGMAC_USXGMII_ENABLE;
			mac_tx_configuration.bf.ss= XGMAC_SPEED_SELECT_2500M;
		}
		else
		{
			mac_tx_configuration.bf.uss= XGMAC_USXGMII_CLEAR;
			mac_tx_configuration.bf.ss= XGMAC_SPEED_SELECT_2500M;
		}
	}
	else if(FAL_SPEED_100 == speed)
	{
		mac_tx_configuration.bf.uss= XGMAC_USXGMII_CLEAR;
		mac_tx_configuration.bf.ss= XGMAC_SPEED_SELECT_1000M;
	}
	else if(FAL_SPEED_10 == speed)
	{
		mac_tx_configuration.bf.uss= XGMAC_USXGMII_CLEAR;
		mac_tx_configuration.bf.ss= XGMAC_SPEED_SELECT_1000M;
	}

	rv = hppe_mac_tx_configuration_set(dev_id, port_id, &mac_tx_configuration);

	return rv;
}

static sw_error_t
_adpt_hppe_gmac_duplex_set(a_uint32_t dev_id, a_uint32_t port_id, fal_port_duplex_t duplex)
{
	sw_error_t rv = SW_OK;
	union mac_enable_u mac_enable;

	memset(&mac_enable, 0, sizeof(mac_enable));
	ADPT_DEV_ID_CHECK(dev_id);

	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
	hppe_mac_enable_get(dev_id, port_id, &mac_enable);

	if (FAL_FULL_DUPLEX == duplex)
		mac_enable.bf.duplex = 1;
	else
		mac_enable.bf.duplex = 0;

	rv = hppe_mac_enable_set(dev_id, port_id, &mac_enable);

	return rv;
}

sw_error_t
adpt_hppe_port_mac_duplex_set(a_uint32_t dev_id, a_uint32_t port_id, fal_port_duplex_t duplex)
{
	sw_error_t rv = SW_OK;
	a_uint32_t port_mac_type;

	port_mac_type = qca_hppe_port_mac_type_get(dev_id, port_id);
	if (port_mac_type == PORT_XGMAC_TYPE)
	{
		return rv;
	}
	else if (port_mac_type == PORT_GMAC_TYPE)
	{
		rv = _adpt_hppe_gmac_duplex_set(dev_id, port_id, duplex);
	}
	else
	{
		return SW_BAD_VALUE;
	}

	return rv;
}

static sw_error_t
_adpt_hppe_port_mux_mac_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t port_type)
{
	sw_error_t rv = SW_OK;
	union port_mux_ctrl_u port_mux_ctrl;
	a_uint32_t mode0, mode1;

	memset(&port_mux_ctrl, 0, sizeof(port_mux_ctrl));
	ADPT_DEV_ID_CHECK(dev_id);

	rv = hppe_port_mux_ctrl_get(dev_id, &port_mux_ctrl);
	port_mux_ctrl.bf.port4_pcs_sel = PORT4_PCS_SEL_GMII_FROM_PCS0;

	if (port_id == HPPE_MUX_PORT1)
	{
		if (port_type == PORT_GMAC_TYPE)
		{
			mode0 = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE0);
			mode1 = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE1);
			if ((mode0 == PORT_WRAPPER_PSGMII) ||
				(mode0 == PORT_WRAPPER_PSGMII_FIBER) ||
				(mode0 == PORT_WRAPPER_SGMII4_RGMII4) ||
				(mode0 == PORT_WRAPPER_SGMII_CHANNEL4))
			{
				port_mux_ctrl.bf.port5_pcs_sel = PORT5_PCS_SEL_GMII_FROM_PCS0;
				port_mux_ctrl.bf.port5_gmac_sel = PORT5_GMAC_SEL_GMAC;
			}
			if (mode1 == PORT_WRAPPER_SGMII0_RGMII4 ||
					mode1 == PORT_WRAPPER_SGMII_CHANNEL0 ||
					mode1 == PORT_WRAPPER_SGMII_PLUS ||
					mode1 == PORT_WRAPPER_SGMII_FIBER)
			{
				port_mux_ctrl.bf.port5_pcs_sel = PORT5_PCS_SEL_GMII_FROM_PCS1;
				port_mux_ctrl.bf.port5_gmac_sel = PORT5_GMAC_SEL_GMAC;
			}
		}
		else if (port_type == PORT_XGMAC_TYPE)
		{
			port_mux_ctrl.bf.port5_pcs_sel = PORT5_PCS_SEL_GMII_FROM_PCS1;
			port_mux_ctrl.bf.port5_gmac_sel = PORT5_GMAC_SEL_XGMAC;
		}
		else
			return SW_NOT_SUPPORTED;
	}
	else if (port_id == HPPE_MUX_PORT2)
	{
		if (port_type == PORT_GMAC_TYPE)
		{
			port_mux_ctrl.bf.port6_pcs_sel = PORT6_PCS_SEL_GMII_FROM_PCS2;
			port_mux_ctrl.bf.port6_gmac_sel = PORT6_GMAC_SEL_GMAC;
		}
		else if (port_type == PORT_XGMAC_TYPE)
		{
			port_mux_ctrl.bf.port6_pcs_sel = PORT6_PCS_SEL_GMII_FROM_PCS2;
			port_mux_ctrl.bf.port6_gmac_sel = PORT6_GMAC_SEL_XGMAC;
		}
		else
			return SW_NOT_SUPPORTED;
	}
	else
		return SW_OK;

	rv = hppe_port_mux_ctrl_set(dev_id, &port_mux_ctrl);

	return rv;
}

static sw_error_t
adpt_hppe_port_xgmac_promiscuous_mode_set(a_uint32_t dev_id,
	a_uint32_t port_id)
{
	sw_error_t rv = 0;

	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);

	rv = hppe_mac_packet_filter_pr_set(dev_id, port_id, PROMISCUOUS_MODE);

	SW_RTN_ON_ERROR (rv);

	rv = hppe_mac_packet_filter_pcf_set(dev_id, port_id, PASS_CONTROL_PACKET);

	return rv;
}
static sw_error_t
adpt_hppe_port_speed_change_mac_reset(a_uint32_t dev_id, a_uint32_t port_id)
{
	a_uint32_t uniphy_index = 0, mode = 0;
	a_uint32_t rxfc_status = 0, txfc_status = 0;
	sw_error_t rv = 0;

	if (port_id == HPPE_MUX_PORT1) {
		uniphy_index = SSDK_UNIPHY_INSTANCE1;
	} else if (port_id == HPPE_MUX_PORT2) {
		uniphy_index = SSDK_UNIPHY_INSTANCE2;
	} else {
		return SW_OK;
	}
	mode = ssdk_dt_global_get_mac_mode(dev_id, uniphy_index);
	if (mode == PORT_WRAPPER_USXGMII) {
		ssdk_port_mac_clock_reset(dev_id, port_id);
		/*restore xgmac's pr and pcf setting after reset operation*/
		rv = adpt_hppe_port_xgmac_promiscuous_mode_set(dev_id,
			port_id);
		SW_RTN_ON_ERROR(rv);
		/*flowctrl need to be configured when reset XGMAC*/
		rv = _adpt_xgmac_port_rxfc_status_get(dev_id, port_id,
			&rxfc_status);
		SW_RTN_ON_ERROR(rv);
		rv = _adpt_xgmac_port_rxfc_status_set(dev_id, port_id,
			rxfc_status);
		SW_RTN_ON_ERROR(rv);

		rv = _adpt_xgmac_port_txfc_status_get(dev_id, port_id,
			&txfc_status);
		SW_RTN_ON_ERROR(rv);
		rv = _adpt_xgmac_port_txfc_status_set(dev_id, port_id,
			txfc_status);
	}
	return rv;
}
static sw_error_t
adpt_hppe_port_interface_mode_switch_mac_reset(a_uint32_t dev_id,
	a_uint32_t port_id)
{
	a_uint32_t uniphy_index = 0, mode = 0;
	sw_error_t rv = 0;
	phy_type_t phy_type;
	a_uint32_t port_mac_type;

	phy_type = hsl_phy_type_get(dev_id, port_id);
	if (phy_type != AQUANTIA_PHY_CHIP && phy_type != SFP_PHY_CHIP) {
		return SW_OK;
	}

	if (port_id == HPPE_MUX_PORT1) {
		uniphy_index = SSDK_UNIPHY_INSTANCE1;
	} else if (port_id == HPPE_MUX_PORT2) {
		uniphy_index = SSDK_UNIPHY_INSTANCE2;
	} else {
		return SW_OK;
	}

	mode = ssdk_dt_global_get_mac_mode(dev_id, uniphy_index);
	if ((mode == PORT_WRAPPER_USXGMII) ||
		(mode == PORT_WRAPPER_SGMII_CHANNEL0) ||
		(mode == PORT_WRAPPER_SGMII0_RGMII4) ||
		(mode == PORT_WRAPPER_SGMII_FIBER) ||
		(mode == PORT_WRAPPER_10GBASE_R) ||
		(mode == PORT_WRAPPER_SGMII_PLUS)) {
		ssdk_port_mac_clock_reset(dev_id, port_id);
		port_mac_type = qca_hppe_port_mac_type_get(dev_id, port_id);
		if (port_mac_type == PORT_XGMAC_TYPE) {
			/*restore xgmac's pr and pcf setting after reset operation*/
			rv = adpt_hppe_port_xgmac_promiscuous_mode_set(dev_id,
			port_id);
		}
	}
	return rv;
}

sw_error_t
adpt_hppe_port_mac_speed_set(a_uint32_t dev_id, a_uint32_t port_id,
				fal_port_speed_t speed)
{
	sw_error_t rv = SW_OK;
	a_uint32_t port_mac_type;

	port_mac_type = qca_hppe_port_mac_type_get(dev_id, port_id);
	if (port_mac_type == PORT_XGMAC_TYPE)
	{
		rv = _adpt_hppe_xgmac_speed_set(dev_id, port_id, speed);

	}
	else if (port_mac_type == PORT_GMAC_TYPE)
	{
		rv = _adpt_hppe_gmac_speed_set(dev_id, port_id, speed);
	}
	else
	{
		return SW_BAD_VALUE;
	}
	return rv;
}
static sw_error_t
_adpt_hppe_port_mux_set(a_uint32_t dev_id, fal_port_t port_id,
	a_uint32_t mode1, a_uint32_t mode2)
{
	a_uint32_t  mode = 0, port_type;
	sw_error_t rv = SW_OK;

	port_type = qca_hppe_port_mac_type_get(dev_id, port_id);
	if (port_type == PORT_GMAC_TYPE)
	{
		rv = adpt_hppe_port_mac_speed_set(dev_id, port_id, FAL_SPEED_1000);
		rv = adpt_hppe_port_mac_duplex_set(dev_id, port_id, FAL_FULL_DUPLEX);
	}
	else if (port_type == PORT_XGMAC_TYPE)
	{
		if (port_id == HPPE_MUX_PORT1)
			mode = mode1;
		else if (port_id == HPPE_MUX_PORT2)
			mode = mode2;
		else
			return SW_NOT_SUPPORTED;
		if (mode == PORT_WRAPPER_SGMII_PLUS)
		{
			rv = adpt_hppe_port_mac_speed_set(dev_id, port_id, FAL_SPEED_2500);
			rv = adpt_hppe_port_mac_duplex_set(dev_id, port_id, FAL_FULL_DUPLEX);
		}
		else
		{
			rv = adpt_hppe_port_mac_speed_set(dev_id, port_id, FAL_SPEED_10000);
			rv = adpt_hppe_port_mac_duplex_set(dev_id, port_id, FAL_FULL_DUPLEX);
		}
	}
	if ((port_type == PORT_GMAC_TYPE) ||(port_type == PORT_XGMAC_TYPE)) {
		if (adpt_hppe_chip_revision_get(dev_id) == HPPE_REVISION) {
		 	rv = _adpt_hppe_port_mux_mac_set(dev_id, port_id, port_type);
		} else if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) {
#if defined(CPPE)
			rv = _adpt_cppe_port_mux_mac_set(dev_id, port_id, port_type);
#endif
		}
	}

	if (port_id >= HPPE_MUX_PORT1) {
		if (port_type == PORT_GMAC_TYPE) {
			rv = _adpt_xgmac_port_txfc_status_set( dev_id, port_id, A_FALSE);
			SW_RTN_ON_ERROR(rv);
			rv = _adpt_xgmac_port_rxfc_status_set( dev_id, port_id, A_FALSE);
			SW_RTN_ON_ERROR(rv);
		} else if (port_type == PORT_XGMAC_TYPE) {
			rv = _adpt_gmac_port_txfc_status_set( dev_id, port_id, A_FALSE);
			SW_RTN_ON_ERROR(rv);
			rv = _adpt_gmac_port_rxfc_status_set( dev_id, port_id, A_FALSE);
			SW_RTN_ON_ERROR(rv);
		} else {
			return SW_NOT_SUPPORTED;
		}
		rv = adpt_hppe_port_interface_mode_switch_mac_reset(dev_id, port_id);
	}

	return rv;
}

sw_error_t
adpt_hppe_port_mux_mac_type_set(a_uint32_t dev_id, fal_port_t port_id,
	a_uint32_t mode0, a_uint32_t mode1, a_uint32_t mode2)
{
	sw_error_t rv = SW_OK;
	a_uint32_t mode_tmp;

	/*init the port interface mode before set it according to three mac modes*/
	rv = _adpt_hppe_port_interface_mode_set(dev_id, port_id, PORT_INTERFACE_MODE_MAX);
	SW_RTN_ON_ERROR(rv);

	switch (mode0) {
		case PORT_WRAPPER_PSGMII_FIBER:
			if(port_id >= SSDK_PHYSICAL_PORT1  && port_id <= SSDK_PHYSICAL_PORT5)
			{
				qca_hppe_port_mac_type_set(dev_id, port_id, PORT_GMAC_TYPE);
				if (port_id == SSDK_PHYSICAL_PORT5) {
					_adpt_hppe_port_interface_mode_set(dev_id,
							SSDK_PHYSICAL_PORT5, PHY_PSGMII_FIBER);
				} else {
					_adpt_hppe_port_interface_mode_set(dev_id,
							port_id, PHY_PSGMII_BASET);
				}
			}
			break;
		case PORT_WRAPPER_PSGMII:
			if((port_id >= SSDK_PHYSICAL_PORT1 && port_id <= SSDK_PHYSICAL_PORT4) ||
					(port_id == SSDK_PHYSICAL_PORT5 &&
					 mode1 == PORT_WRAPPER_MAX))
			{
				qca_hppe_port_mac_type_set(dev_id, port_id, PORT_GMAC_TYPE);
				_adpt_hppe_port_interface_mode_set(dev_id, port_id, PHY_PSGMII_BASET);
			}
			break;
		case PORT_WRAPPER_QSGMII:
			if(port_id >= SSDK_PHYSICAL_PORT1 && port_id <= SSDK_PHYSICAL_PORT4)
			{
				qca_hppe_port_mac_type_set(dev_id, port_id, PORT_GMAC_TYPE);
				_adpt_hppe_port_interface_mode_set(dev_id, port_id, PORT_QSGMII);
			}
			break;
		case PORT_WRAPPER_SGMII0_RGMII4:
		case PORT_WRAPPER_SGMII_CHANNEL0:
		case PORT_WRAPPER_SGMII_FIBER:
#ifdef CPPE
		case PORT_WRAPPER_SGMII_PLUS:
			if(adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION
				&& port_id == SSDK_PHYSICAL_PORT4)
			{
				qca_hppe_port_mac_type_set(dev_id, port_id,
					PORT_GMAC_TYPE);
				if((mode0 == PORT_WRAPPER_SGMII0_RGMII4 ||
					mode0 == PORT_WRAPPER_SGMII_CHANNEL0))
				{
					if(hsl_port_prop_check (dev_id, port_id,
						HSL_PP_EXCL_CPU))
					{
						_adpt_hppe_port_interface_mode_set(dev_id, port_id,
							PHY_SGMII_BASET);
					}
					else
					{
						SSDK_ERROR("Port bitmap is incorrect when port 4"
							"support sgmii for CPPE\n");
						return SW_NOT_SUPPORTED;
					}
				}
				else if(mode0 == PORT_WRAPPER_SGMII_PLUS)
				{
					_adpt_hppe_port_interface_mode_set(dev_id, port_id,
						PORT_SGMII_PLUS);
				}
				else
				{
					SSDK_ERROR("CPPE doesn't support mode0 : %x\n",
						mode0);
					return SW_NOT_SUPPORTED;
				}
				break;
			}
#endif
			if(port_id == SSDK_PHYSICAL_PORT1)
			{
				qca_hppe_port_mac_type_set(dev_id, SSDK_PHYSICAL_PORT1,
						PORT_GMAC_TYPE);
				if(mode0 == PORT_WRAPPER_SGMII_FIBER)
				{
					_adpt_hppe_port_interface_mode_set(dev_id,
							SSDK_PHYSICAL_PORT1, PORT_SGMII_FIBER);
				}
				else
				{
					_adpt_hppe_port_interface_mode_set(dev_id,
							SSDK_PHYSICAL_PORT1, PHY_SGMII_BASET);
				}
			}
			break;
		case PORT_WRAPPER_SGMII1_RGMII4:
		case PORT_WRAPPER_SGMII_CHANNEL1:
			if(port_id == SSDK_PHYSICAL_PORT2)
			{
				qca_hppe_port_mac_type_set(dev_id, SSDK_PHYSICAL_PORT2,
						PORT_GMAC_TYPE);
				_adpt_hppe_port_interface_mode_set(dev_id,
						SSDK_PHYSICAL_PORT2, PHY_SGMII_BASET);
			}
			break;
		case PORT_WRAPPER_SGMII4_RGMII4:
		case PORT_WRAPPER_SGMII_CHANNEL4:
			if(port_id == SSDK_PHYSICAL_PORT5)
			{
				qca_hppe_port_mac_type_set(dev_id, SSDK_PHYSICAL_PORT5,
						PORT_GMAC_TYPE);
				_adpt_hppe_port_interface_mode_set(dev_id,
						SSDK_PHYSICAL_PORT5, PHY_SGMII_BASET);
			}
			break;
		default:
			break;
	}
	if(port_id == SSDK_PHYSICAL_PORT5 ||port_id == SSDK_PHYSICAL_PORT6)
	{
		if(port_id == SSDK_PHYSICAL_PORT5)
			mode_tmp = mode1;
		else
			mode_tmp = mode2;

		switch(mode_tmp)
		{
			case PORT_WRAPPER_SGMII_CHANNEL0:
			case PORT_WRAPPER_SGMII0_RGMII4:
			case PORT_WRAPPER_SGMII_FIBER:
				qca_hppe_port_mac_type_set(dev_id, port_id, PORT_GMAC_TYPE);
				if(mode_tmp == PORT_WRAPPER_SGMII_FIBER)
				{
					_adpt_hppe_port_interface_mode_set(dev_id, port_id,
						PORT_SGMII_FIBER);
				}
				else
				{
					_adpt_hppe_port_interface_mode_set(dev_id, port_id,
						PHY_SGMII_BASET);
				}
				break;
			case PORT_WRAPPER_SGMII_PLUS:
				if (ssdk_port_feature_get(dev_id, port_id, PHY_F_QGMAC)) {
					qca_hppe_port_mac_type_set(dev_id, port_id,
							PORT_GMAC_TYPE);
				} else {
					qca_hppe_port_mac_type_set(dev_id, port_id,
							PORT_XGMAC_TYPE);
				}
				_adpt_hppe_port_interface_mode_set(dev_id, port_id, PORT_SGMII_PLUS);
				break;
			case PORT_WRAPPER_USXGMII:
				qca_hppe_port_mac_type_set(dev_id, port_id, PORT_XGMAC_TYPE);
				_adpt_hppe_port_interface_mode_set(dev_id, port_id, PORT_USXGMII);
				break;
			case PORT_WRAPPER_10GBASE_R:
				qca_hppe_port_mac_type_set(dev_id, port_id, PORT_XGMAC_TYPE);
				_adpt_hppe_port_interface_mode_set(dev_id, port_id, PORT_10GBASE_R);
				break;
			default:
				break;
		}
	}

	rv = _adpt_hppe_port_mux_set(dev_id, port_id,mode1, mode2);

	return rv;
}

static sw_error_t
_adpt_hppe_instance0_mode_get(a_uint32_t dev_id, a_uint32_t *mode0)
{
	a_uint32_t port_id = 0;

	for(port_id = SSDK_PHYSICAL_PORT1; port_id <= SSDK_PHYSICAL_PORT5; port_id++)
	{
		if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_EXCL_CPU))
		{
			continue;
		}
		SSDK_DEBUG("port_id:%d, port_interface_mode:%d\n", port_id,
			port_interface_mode[dev_id][port_id]);
		if(port_interface_mode[dev_id][port_id] == PHY_PSGMII_BASET)
		{
			if(*mode0 != PORT_WRAPPER_MAX && *mode0 != PORT_WRAPPER_PSGMII)
			{
				SSDK_ERROR("when the port_interface_mode of port %d is %d, "
					"mode0:%d cannot be supported\n",
					port_id, port_interface_mode[dev_id][port_id], *mode0);
				return SW_NOT_SUPPORTED;
			}
			*mode0 = PORT_WRAPPER_PSGMII;
		}

		if(port_interface_mode[dev_id][port_id] == PHY_PSGMII_FIBER &&
			port_id == SSDK_PHYSICAL_PORT5)
		{
			*mode0 = PORT_WRAPPER_PSGMII_FIBER;
		}

		if(port_interface_mode[dev_id][port_id] == PORT_QSGMII)
		{
			if((*mode0 != PORT_WRAPPER_MAX && *mode0 != PORT_WRAPPER_QSGMII) ||
				port_id == SSDK_PHYSICAL_PORT5)
			{
				SSDK_ERROR("when the port_interface_mode of port %d is %d, "
					"mode0:%d cannot be supported\n",
					port_id, port_interface_mode[dev_id][port_id], *mode0);
				return SW_NOT_SUPPORTED;
			}
			*mode0 = PORT_WRAPPER_QSGMII;
		}

		if(port_interface_mode[dev_id][port_id] == PHY_SGMII_BASET ||
			port_interface_mode[dev_id][port_id] == PORT_SGMII_FIBER)
		{
			if(*mode0 !=PORT_WRAPPER_MAX)
			{
				if(port_id != SSDK_PHYSICAL_PORT5)
				{
					SSDK_ERROR("when the port_interface_mode of port %d is %d, "
						"mode0:%d cannot be supported\n",
						port_id, port_interface_mode[dev_id][port_id],
						*mode0);
					return SW_NOT_SUPPORTED;
				}
				else
				{
					return SW_OK;
				}
			}
			switch(port_id)
			{
				case SSDK_PHYSICAL_PORT1:
					if(port_interface_mode[dev_id][port_id] == PORT_SGMII_FIBER)
					{
						*mode0 = PORT_WRAPPER_SGMII_FIBER;
					}
					else
					{
						*mode0 = PORT_WRAPPER_SGMII_CHANNEL0;
					}
					break;
				case SSDK_PHYSICAL_PORT2:
					*mode0 = PORT_WRAPPER_SGMII_CHANNEL1;
					break;
#ifdef CPPE
				case SSDK_PHYSICAL_PORT4:
					if(adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION)
					{
						*mode0 = PORT_WRAPPER_SGMII_CHANNEL0;
					}
					break;
#endif
				case SSDK_PHYSICAL_PORT5:
					if(ssdk_dt_global_get_mac_mode(dev_id,
						SSDK_UNIPHY_INSTANCE1) == PORT_WRAPPER_MAX)
					{
						*mode0 = PORT_WRAPPER_SGMII_CHANNEL4;
					}
					break;
				default:
					SSDK_ERROR("port %d doesn't support "
						"port_interface_mode %d\n",
						port_id, port_interface_mode[dev_id][port_id]);
					return SW_NOT_SUPPORTED;
			}
		}
		if(port_id != SSDK_PHYSICAL_PORT5 &&
				(port_interface_mode[dev_id][port_id] == PORT_SGMII_PLUS ||
				 port_interface_mode[dev_id][port_id] ==PORT_USXGMII ||
				 port_interface_mode[dev_id][port_id] == PORT_10GBASE_R))
		{
#ifdef CPPE
			if(port_interface_mode[dev_id][port_id] == PORT_SGMII_PLUS
				&& adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION
				&& port_id == SSDK_PHYSICAL_PORT4)
			{
				*mode0 = PORT_WRAPPER_SGMII_PLUS;
				continue;
			}
#endif
			SSDK_ERROR("port %d doesn't support port_interface_mode %d\n",
				port_id, port_interface_mode[dev_id][port_id]);
			return SW_NOT_SUPPORTED;
		}
	}

	return SW_OK;
}

static sw_error_t
_adpt_hppe_instance1_mode_get(a_uint32_t dev_id, a_uint32_t port_id,  a_uint32_t *mode)
{
	if ((A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_EXCL_CPU)) ||
		A_TRUE == hsl_port_prop_check (dev_id, port_id, HSL_PP_INNER))
	{
		return SW_OK;
	}
	SSDK_DEBUG("port_id:%x: %x\n", port_id, port_interface_mode[dev_id][port_id]);
	switch(port_interface_mode[dev_id][port_id])
	{
		case PHY_SGMII_BASET:
			*mode = PORT_WRAPPER_SGMII_CHANNEL0;
			break;
		case PORT_SGMII_PLUS:
			*mode = PORT_WRAPPER_SGMII_PLUS;
			break;
		case PORT_USXGMII:
			*mode = PORT_WRAPPER_USXGMII;
			break;
		case PORT_10GBASE_R:
			*mode = PORT_WRAPPER_10GBASE_R;
			break;
		case PORT_SGMII_FIBER:
			*mode = PORT_WRAPPER_SGMII_FIBER;
			break;
		case PHY_PSGMII_BASET:
		case PHY_PSGMII_FIBER:
			if(port_id == SSDK_PHYSICAL_PORT6)
			{
				SSDK_ERROR("port %d doesn't support port_interface_mode %d\n",
					port_id, port_interface_mode[dev_id][port_id]);
				return SW_NOT_SUPPORTED;
			}
			*mode = PORT_INTERFACE_MODE_MAX;
			break;
		case PORT_INTERFACE_MODE_MAX:
			break;
		default:
			SSDK_ERROR("port %d doesn't support port_interface_mode %d\n",
				port_id, port_interface_mode[dev_id][port_id]);
			return SW_NOT_SUPPORTED;
	}

	return SW_OK;
}

static sw_error_t
_adpt_hppe_instance_mode_get(a_uint32_t dev_id, a_uint32_t uniphy_index,
	a_uint32_t *interface_mode)
{
	sw_error_t rv = SW_OK;

	switch(uniphy_index)
	{
		case SSDK_UNIPHY_INSTANCE0:
			rv = _adpt_hppe_instance0_mode_get(dev_id, interface_mode);
			SW_RTN_ON_ERROR(rv);
			break;
		case SSDK_UNIPHY_INSTANCE1:
			rv =_adpt_hppe_instance1_mode_get(dev_id, SSDK_PHYSICAL_PORT5,
				interface_mode);
			SW_RTN_ON_ERROR(rv);
			break;
		case SSDK_UNIPHY_INSTANCE2:
			rv =_adpt_hppe_instance1_mode_get(dev_id, SSDK_PHYSICAL_PORT6,
				interface_mode);
			SW_RTN_ON_ERROR(rv);
			break;
		default:
			return SW_NOT_SUPPORTED;
	}

	return rv;
}

extern sw_error_t
adpt_hppe_uniphy_mode_set(a_uint32_t dev_id, a_uint32_t index, a_uint32_t mode);

static sw_error_t
_adpt_hppe_port_interface_mode_phy_config(a_uint32_t dev_id, a_uint32_t port_id,
	fal_port_interface_mode_t mode)
{
	sw_error_t rv;
	a_uint32_t phy_id = 0;
	hsl_phy_ops_t *phy_drv;

	ADPT_DEV_ID_CHECK(dev_id);

	if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY))
	{
		SSDK_ERROR("port %d is not in bitmap\n", port_id);
		return SW_BAD_PARAM;
	}
	SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id));
	if (NULL == phy_drv->phy_interface_mode_set)
	{
		SSDK_ERROR("the phy_interface_mode_set api is null for port %d\n",
			port_id);
		return SW_NOT_SUPPORTED;
	}

	rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id);
	SW_RTN_ON_ERROR (rv);
	SSDK_DEBUG("port_id:%d, phy_id:%d, mode:%d\n", port_id, phy_id, mode);
	rv = phy_drv->phy_interface_mode_set (dev_id, phy_id,mode);

	return rv;
}

static sw_error_t _adpt_hppe_port_mac_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable)
{
	sw_error_t rv = SW_OK;

	rv = adpt_hppe_port_txmac_status_set(dev_id, port_id, enable);
	SW_RTN_ON_ERROR(rv);
	rv = adpt_hppe_port_rxmac_status_set(dev_id, port_id, enable);

	return rv;
}

static sw_error_t
_adpt_hppe_port_phyaddr_update(a_uint32_t dev_id, a_uint32_t port_id,
	a_uint32_t mode)
{
	sw_error_t rv = SW_OK;
	a_uint32_t phy_addr = 0, mode0 = PORT_WRAPPER_MAX;
	ssdk_port_phyinfo *port_phyinfo = NULL;

	if(port_id != SSDK_PHYSICAL_PORT5)
	{
		return rv;
	}
	if(mode == PORT_WRAPPER_10GBASE_R)
	{
		port_phyinfo = ssdk_port_phyinfo_get(dev_id, port_id);
		if (!port_phyinfo)
		{
			SSDK_ERROR("port_phyinfo of port%d is null\n", port_id);
			return SW_FAIL;
		}
		phy_addr = port_phyinfo->phy_addr;
		qca_ssdk_phy_address_set(dev_id, port_id, phy_addr);
		hsl_port_phy_access_type_set(dev_id, port_id, PHY_I2C_ACCESS);
		SSDK_DEBUG("port %x phy_addr is %x\n", port_id, phy_addr);
	}
	else
	{
		mode0 = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE0);
		if((mode0 == PORT_WRAPPER_PSGMII || mode0 == PORT_WRAPPER_PSGMII_FIBER) &&
			mode == PORT_WRAPPER_MAX)
		{
			rv = hsl_port_prop_get_phyid (dev_id, SSDK_PHYSICAL_PORT4, &phy_addr);
			SW_RTN_ON_ERROR (rv);
			phy_addr++;
			qca_ssdk_phy_address_set(dev_id, port_id, phy_addr);
			hsl_port_phy_access_type_set(dev_id, port_id, PHY_MDIO_ACCESS);
			SSDK_DEBUG("port %x phy_addr is %x\n", port_id, phy_addr);
		}
	}

	return rv;
}

static sw_error_t
_adpt_hppe_sfp_copper_phydriver_switch(a_uint32_t dev_id, a_uint32_t port_id,
	a_uint32_t mode)
{
	sw_error_t rv = SW_OK;

	rv = _adpt_hppe_port_phyaddr_update(dev_id, port_id, mode);
	SW_RTN_ON_ERROR(rv);
	rv = hsl_phydriver_update(dev_id, port_id, mode);

	return rv;
}

static sw_error_t
_adpt_hppe_port_phy_config(a_uint32_t dev_id, a_uint32_t index, a_uint32_t mode)
{
	sw_error_t rv = SW_OK;

	switch(mode)
	{
		case PORT_WRAPPER_PSGMII:
			/*interface mode changed form psgmii+usxgmii to psgmii+10gbase-r+usxgmii, cannot
			use port 5 to configure malibu*/
			rv = _adpt_hppe_port_interface_mode_phy_config(dev_id,
				SSDK_PHYSICAL_PORT4, PHY_PSGMII_BASET);
			break;
		case PORT_WRAPPER_PSGMII_FIBER:
			rv = _adpt_hppe_port_interface_mode_phy_config(dev_id,
				SSDK_PHYSICAL_PORT4, PHY_PSGMII_FIBER);
			break;
		case PORT_WRAPPER_SGMII_CHANNEL4:
			rv = _adpt_hppe_port_interface_mode_phy_config(dev_id,
				SSDK_PHYSICAL_PORT5, PHY_SGMII_BASET);
			break;
		case PORT_WRAPPER_QSGMII:
			rv = _adpt_hppe_port_interface_mode_phy_config(dev_id,
				SSDK_PHYSICAL_PORT4, PORT_QSGMII);
			break;
		case PORT_WRAPPER_SGMII_CHANNEL0:
#ifdef CPPE
			if(index == SSDK_UNIPHY_INSTANCE0 &&
				adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION &&
				(hsl_port_prop_check (dev_id, SSDK_PHYSICAL_PORT4,
					HSL_PP_EXCL_CPU)))
			{
					rv = _adpt_hppe_port_interface_mode_phy_config(dev_id,
						SSDK_PHYSICAL_PORT4, PHY_SGMII_BASET);
			}
#endif
			if(index == SSDK_UNIPHY_INSTANCE1)
			{
				rv = _adpt_hppe_port_interface_mode_phy_config(dev_id,
					SSDK_PHYSICAL_PORT5, PHY_SGMII_BASET);
			}
			if(index == SSDK_UNIPHY_INSTANCE2)
			{
				rv = _adpt_hppe_port_interface_mode_phy_config(dev_id,
					SSDK_PHYSICAL_PORT6, PHY_SGMII_BASET);
			}
			break;
		case PORT_WRAPPER_USXGMII:
			if(index == SSDK_UNIPHY_INSTANCE1)
			{
				rv = _adpt_hppe_port_interface_mode_phy_config(dev_id,
					SSDK_PHYSICAL_PORT5, PORT_USXGMII);
			}
			if(index == SSDK_UNIPHY_INSTANCE2)
			{
				rv = _adpt_hppe_port_interface_mode_phy_config(dev_id,
					SSDK_PHYSICAL_PORT6, PORT_USXGMII);
			}
			break;
		case PORT_WRAPPER_SGMII_PLUS:
#ifdef CPPE
			if(index == SSDK_UNIPHY_INSTANCE0 &&
				adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION)
			{
				rv = _adpt_hppe_port_interface_mode_phy_config(dev_id,
					SSDK_PHYSICAL_PORT4, PORT_SGMII_PLUS);
			}
#endif
			if(index == SSDK_UNIPHY_INSTANCE1)
			{
				rv = _adpt_hppe_port_interface_mode_phy_config(dev_id,
					SSDK_PHYSICAL_PORT5, PORT_SGMII_PLUS);
			}
			if(index == SSDK_UNIPHY_INSTANCE2)
			{
				rv = _adpt_hppe_port_interface_mode_phy_config(dev_id,
					SSDK_PHYSICAL_PORT6, PORT_SGMII_PLUS);
			}
			break;
		default:
			break;
	}

	return rv;
}

static sw_error_t
adpt_hppe_port_mac_uniphy_phy_config(a_uint32_t dev_id, a_uint32_t mode_index,
	a_uint32_t mode[], a_bool_t force_switch)
{
	sw_error_t rv = SW_OK;
	a_uint32_t port_id = 0, port_id_from = 0, port_id_end = 0;

	if(mode_index == SSDK_UNIPHY_INSTANCE0)
	{
		switch (mode[SSDK_UNIPHY_INSTANCE0])
		{
			case PORT_WRAPPER_PSGMII:
			case PORT_WRAPPER_PSGMII_FIBER:
				port_id_from = SSDK_PHYSICAL_PORT1;
				/*qsgmii+10gbase-r+usxgmii --> psgmii+10gbase-r+usxgmii*/
				if(mode[SSDK_UNIPHY_INSTANCE1] != PORT_WRAPPER_MAX)
				{
					port_id_end = SSDK_PHYSICAL_PORT4;
				}
				else
				{
					port_id_end = SSDK_PHYSICAL_PORT5;
				}
				break;
			case PORT_WRAPPER_QSGMII:
				port_id_from = SSDK_PHYSICAL_PORT1;
				port_id_end = SSDK_PHYSICAL_PORT4;
				break;
			case PORT_WRAPPER_SGMII0_RGMII4:
			case PORT_WRAPPER_SGMII_CHANNEL0:
			case PORT_WRAPPER_SGMII_FIBER:
#ifdef CPPE
			case PORT_WRAPPER_SGMII_PLUS:
				if(adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION)
				{
					a_uint32_t mode_tmp = 0