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diff --git a/arch/arm/dts/meson-c2-c325x-2rs4.dts b/arch/arm/dts/meson-c2-c325x-2rs4.dts deleted file mode 100644 index d96b261..0000000 --- a/arch/arm/dts/meson-c2-c325x-2rs4.dts +++ /dev/null
@@ -1,95 +0,0 @@ -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione <carlo@endlessm.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "meson-c2-c325x-2rs4.dtsi" - -/ { - compatible = "amlogic,af400", "amlogic,c305x", "amlogic,meson-c2"; - model = "Google 2RS4 Board"; -}; - -/* This UART is brought out to the DB9 connector */ -&uart_a { - status = "okay"; -}; - -&uart_b { - status = "okay"; -}; - -&saradc { - status = "okay"; -}; - -&i2c3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_master_pins1>; - clock-frequency = <400000>; /* max supported freq */ -}; - -&i2c4 { - status= "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_master_pins1>; - clock-frequency = <400000>; /* 400K, b/159627458 */ -}; - -ðmac { - status = "okay"; - internal_phy = <0>; - pinctrl-0 = <&external_eth_rmii_pins>; - pinctrl-names = "external_eth_rmii_pins"; - mc_val = <0x1624>; -}; -&pinctrl_periphs { - bl_pwm_off_pins:bl_pwm_off_pin { - mux { - groups = "GPIOH_5"; - function = "gpio_periphs"; - output-high; - }; - }; -}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-c2-c325x-2rs4.dtsi b/arch/arm/dts/meson-c2-c325x-2rs4.dtsi deleted file mode 100644 index 2442995..0000000 --- a/arch/arm/dts/meson-c2-c325x-2rs4.dtsi +++ /dev/null
@@ -1,266 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. - * Based on meson-gx-p23x-q20x.dtsi: - * - Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione <carlo@endlessm.com> - * - Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -/* Common DTSI for devices which are based on the P212 reference board. */ - -#include "meson-c2-c305x.dtsi" - -/ { - aliases { - serial0 = &uart_b; - serial1 = &uart_a; - spi0 = &spifc; - spi1 = &spicc0; - spi2 = &spicc1; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; -}; - -ðmac { - status = "okay"; - internal_phy = <1>; - mc_val = <0x4be04>; - /*mc_val = <0x1621>;*/ -}; - -&ir { - status = "disabled"; - /* pinctrl-0 = <&remote_input_ao_pins>; */ - /* pinctrl-names = "default"; */ -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; -}; - -/* Wireless SDIO Module */ -&sd_emmc_a { - status = "disabled"; - /*pinctrl-0 = <&sdio_pins>;*/ - /*pinctrl-names = "default";*/ - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <100000000>; - - non-removable; - disable-wp; - card_type = <3>; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_pins &to_sduart_pins>; - pinctrl-names = "sd_all_pins", "sd_uart"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <100000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; - cd-inverted; - - card_type = <5>; - - init_co_phase = <2>; - init_tx_phase = <0>; - - hs_co_phase = <2>; - hs_to_phase = <0>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>; - pinctrl-names = "default"; - - bus-width = <8>; - cap-sd-highspeed; - cap-mmc-highspeed; - mmc-hs200-1_8v; - max-frequency = <167000000>; - non-removable; - disable-wp; - /* mmc-ddr-1_8v; */ - card_type = <1>; - - init_co_phase = <2>; - init_tx_phase = <0>; - - hs_co_phase = <2>; - hs_to_phase = <0>; - - hs2_co_phase = <2>; - hs2_to_phase = <0>; - - hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* nand */ -&nand { - status = "okay"; - pinctrl-names = "default", "nand_cs_only"; - pinctrl-0 = <&all_nand_pins>; - pinctrl-1 = <&nand_cs_pins>; -}; - -&dwc3 { - status = "okay"; - dr_mode = "host"; -}; - -&usb2_phy_v2 { - status = "okay"; - portnum = <1>; - phy20-reset-level-bit = <4>; - usb-reset-bit = <3>; - u2-ctrl-sleep-shift = <24>; - u2-hhi-mem-pd-shift = <0x0>; - u2-hhi-mem-pd-mask = <0x3>; - u2-ctrl-iso-shift = <24>; - pll-setting-1 = <0x09400414>; - pll-setting-2 = <0x927E0000>; - pll-setting-3 = <0xac5f69e5>; - pll-setting-4 = <0xfe18>; - pll-setting-5 = <0x8000fff>; - pll-setting-6 = <0x78000>; - pll-setting-7 = <0xe0004>; - pll-setting-8 = <0xe000c>; -}; - -&usb3_phy_v2 { - status = "okay"; - portnum = <0>; - gpio-vbus-power = "GPIOD_9"; - gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>; -}; - -&pwm_ef { - status = "okay"; - /* pinctrl-0 = <&pwm_e_pins>; */ - /* pinctrl-names = "default"; */ -}; - -/* This is connected to the Bluetooth module: */ -&uart_a { - status = "okay"; - /* pinctrl-0 = <&a_uart_pins>; */ - /* pinctrl-names = "default"; */ - uart-has-rtscts; -}; - -&spifc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spifc_pins>; - max-frequency = <24000000>; - max-cs = <2>; - /* 512M */ - clocks = <&clkc CLKID_FCLK_DIV2>, - <&clkc CLKID_SPIFC_MUX>, - <&clkc CLKID_SPIFC_DIV>, - <&clkc CLKID_SPIFC_GATE>, - <&clkc CLKID_SPIFC_XTAL_GATE>; - clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate"; -}; - -&spicc0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spicc0_pins1>; - cs-gpios = <&gpio GPIOA_8 0>, - <&gpio GPIOA_9 0>; -}; - -&spicc1 { - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&spicc1_pins1>; - cs-gpios = <&gpio GPIOA_14 0>; -};
diff --git a/arch/arm/dts/meson-c2-c325x-bla4.dts b/arch/arm/dts/meson-c2-c325x-bla4.dts deleted file mode 100644 index 7ab3160..0000000 --- a/arch/arm/dts/meson-c2-c325x-bla4.dts +++ /dev/null
@@ -1,95 +0,0 @@ -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione <carlo@endlessm.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "meson-c2-c325x-bla4.dtsi" - -/ { - compatible = "amlogic,af400", "amlogic,c305x", "amlogic,meson-c2"; - model = "Google BLA4 Board"; -}; - -/* This UART is brought out to the DB9 connector */ -&uart_a { - status = "okay"; -}; - -&uart_b { - status = "okay"; -}; - -&saradc { - status = "okay"; -}; - -&i2c3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_master_pins2>; - clock-frequency = <400000>; /* max supported freq */ -}; - -&i2c4 { - status= "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_master_pins1>; - clock-frequency = <400000>; /* 400K, b/159627458 */ -}; - -ðmac { - status = "okay"; - internal_phy = <0>; - pinctrl-0 = <&external_eth_rmii_pins>; - pinctrl-names = "external_eth_rmii_pins"; - mc_val = <0x1624>; -}; -&pinctrl_periphs { - bl_pwm_off_pins:bl_pwm_off_pin { - mux { - groups = "GPIOH_5"; - function = "gpio_periphs"; - output-high; - }; - }; -}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-c2-c325x-bla4.dtsi b/arch/arm/dts/meson-c2-c325x-bla4.dtsi deleted file mode 100644 index 2442995..0000000 --- a/arch/arm/dts/meson-c2-c325x-bla4.dtsi +++ /dev/null
@@ -1,266 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. - * Based on meson-gx-p23x-q20x.dtsi: - * - Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione <carlo@endlessm.com> - * - Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -/* Common DTSI for devices which are based on the P212 reference board. */ - -#include "meson-c2-c305x.dtsi" - -/ { - aliases { - serial0 = &uart_b; - serial1 = &uart_a; - spi0 = &spifc; - spi1 = &spicc0; - spi2 = &spicc1; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; -}; - -ðmac { - status = "okay"; - internal_phy = <1>; - mc_val = <0x4be04>; - /*mc_val = <0x1621>;*/ -}; - -&ir { - status = "disabled"; - /* pinctrl-0 = <&remote_input_ao_pins>; */ - /* pinctrl-names = "default"; */ -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; -}; - -/* Wireless SDIO Module */ -&sd_emmc_a { - status = "disabled"; - /*pinctrl-0 = <&sdio_pins>;*/ - /*pinctrl-names = "default";*/ - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <100000000>; - - non-removable; - disable-wp; - card_type = <3>; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_pins &to_sduart_pins>; - pinctrl-names = "sd_all_pins", "sd_uart"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <100000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; - cd-inverted; - - card_type = <5>; - - init_co_phase = <2>; - init_tx_phase = <0>; - - hs_co_phase = <2>; - hs_to_phase = <0>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>; - pinctrl-names = "default"; - - bus-width = <8>; - cap-sd-highspeed; - cap-mmc-highspeed; - mmc-hs200-1_8v; - max-frequency = <167000000>; - non-removable; - disable-wp; - /* mmc-ddr-1_8v; */ - card_type = <1>; - - init_co_phase = <2>; - init_tx_phase = <0>; - - hs_co_phase = <2>; - hs_to_phase = <0>; - - hs2_co_phase = <2>; - hs2_to_phase = <0>; - - hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* nand */ -&nand { - status = "okay"; - pinctrl-names = "default", "nand_cs_only"; - pinctrl-0 = <&all_nand_pins>; - pinctrl-1 = <&nand_cs_pins>; -}; - -&dwc3 { - status = "okay"; - dr_mode = "host"; -}; - -&usb2_phy_v2 { - status = "okay"; - portnum = <1>; - phy20-reset-level-bit = <4>; - usb-reset-bit = <3>; - u2-ctrl-sleep-shift = <24>; - u2-hhi-mem-pd-shift = <0x0>; - u2-hhi-mem-pd-mask = <0x3>; - u2-ctrl-iso-shift = <24>; - pll-setting-1 = <0x09400414>; - pll-setting-2 = <0x927E0000>; - pll-setting-3 = <0xac5f69e5>; - pll-setting-4 = <0xfe18>; - pll-setting-5 = <0x8000fff>; - pll-setting-6 = <0x78000>; - pll-setting-7 = <0xe0004>; - pll-setting-8 = <0xe000c>; -}; - -&usb3_phy_v2 { - status = "okay"; - portnum = <0>; - gpio-vbus-power = "GPIOD_9"; - gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>; -}; - -&pwm_ef { - status = "okay"; - /* pinctrl-0 = <&pwm_e_pins>; */ - /* pinctrl-names = "default"; */ -}; - -/* This is connected to the Bluetooth module: */ -&uart_a { - status = "okay"; - /* pinctrl-0 = <&a_uart_pins>; */ - /* pinctrl-names = "default"; */ - uart-has-rtscts; -}; - -&spifc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spifc_pins>; - max-frequency = <24000000>; - max-cs = <2>; - /* 512M */ - clocks = <&clkc CLKID_FCLK_DIV2>, - <&clkc CLKID_SPIFC_MUX>, - <&clkc CLKID_SPIFC_DIV>, - <&clkc CLKID_SPIFC_GATE>, - <&clkc CLKID_SPIFC_XTAL_GATE>; - clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate"; -}; - -&spicc0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spicc0_pins1>; - cs-gpios = <&gpio GPIOA_8 0>, - <&gpio GPIOA_9 0>; -}; - -&spicc1 { - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&spicc1_pins1>; - cs-gpios = <&gpio GPIOA_14 0>; -};
diff --git a/arch/arm/dts/meson-c2-c325x-xua4.dts b/arch/arm/dts/meson-c2-c325x-xua4.dts deleted file mode 100644 index 5f0c2bd..0000000 --- a/arch/arm/dts/meson-c2-c325x-xua4.dts +++ /dev/null
@@ -1,95 +0,0 @@ -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione <carlo@endlessm.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "meson-c2-c325x-xua4.dtsi" - -/ { - compatible = "amlogic,af400", "amlogic,c305x", "amlogic,meson-c2"; - model = "Google XUA4 Board"; -}; - -/* This UART is brought out to the DB9 connector */ -&uart_a { - status = "okay"; -}; - -&uart_b { - status = "okay"; -}; - -&saradc { - status = "okay"; -}; - -&i2c3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_master_pins2>; - clock-frequency = <400000>; /* max supported freq */ -}; - -&i2c4 { - status= "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_master_pins1>; - clock-frequency = <400000>; /* 400K, b/159627458 */ -}; - -ðmac { - status = "okay"; - internal_phy = <0>; - pinctrl-0 = <&external_eth_rmii_pins>; - pinctrl-names = "external_eth_rmii_pins"; - mc_val = <0x1624>; -}; -&pinctrl_periphs { - bl_pwm_off_pins:bl_pwm_off_pin { - mux { - groups = "GPIOH_5"; - function = "gpio_periphs"; - output-high; - }; - }; -}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-c2-c325x-xua4.dtsi b/arch/arm/dts/meson-c2-c325x-xua4.dtsi deleted file mode 100644 index 2442995..0000000 --- a/arch/arm/dts/meson-c2-c325x-xua4.dtsi +++ /dev/null
@@ -1,266 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. - * Based on meson-gx-p23x-q20x.dtsi: - * - Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione <carlo@endlessm.com> - * - Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -/* Common DTSI for devices which are based on the P212 reference board. */ - -#include "meson-c2-c305x.dtsi" - -/ { - aliases { - serial0 = &uart_b; - serial1 = &uart_a; - spi0 = &spifc; - spi1 = &spicc0; - spi2 = &spicc1; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; -}; - -ðmac { - status = "okay"; - internal_phy = <1>; - mc_val = <0x4be04>; - /*mc_val = <0x1621>;*/ -}; - -&ir { - status = "disabled"; - /* pinctrl-0 = <&remote_input_ao_pins>; */ - /* pinctrl-names = "default"; */ -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; -}; - -/* Wireless SDIO Module */ -&sd_emmc_a { - status = "disabled"; - /*pinctrl-0 = <&sdio_pins>;*/ - /*pinctrl-names = "default";*/ - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <100000000>; - - non-removable; - disable-wp; - card_type = <3>; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_pins &to_sduart_pins>; - pinctrl-names = "sd_all_pins", "sd_uart"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <100000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; - cd-inverted; - - card_type = <5>; - - init_co_phase = <2>; - init_tx_phase = <0>; - - hs_co_phase = <2>; - hs_to_phase = <0>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>; - pinctrl-names = "default"; - - bus-width = <8>; - cap-sd-highspeed; - cap-mmc-highspeed; - mmc-hs200-1_8v; - max-frequency = <167000000>; - non-removable; - disable-wp; - /* mmc-ddr-1_8v; */ - card_type = <1>; - - init_co_phase = <2>; - init_tx_phase = <0>; - - hs_co_phase = <2>; - hs_to_phase = <0>; - - hs2_co_phase = <2>; - hs2_to_phase = <0>; - - hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* nand */ -&nand { - status = "okay"; - pinctrl-names = "default", "nand_cs_only"; - pinctrl-0 = <&all_nand_pins>; - pinctrl-1 = <&nand_cs_pins>; -}; - -&dwc3 { - status = "okay"; - dr_mode = "host"; -}; - -&usb2_phy_v2 { - status = "okay"; - portnum = <1>; - phy20-reset-level-bit = <4>; - usb-reset-bit = <3>; - u2-ctrl-sleep-shift = <24>; - u2-hhi-mem-pd-shift = <0x0>; - u2-hhi-mem-pd-mask = <0x3>; - u2-ctrl-iso-shift = <24>; - pll-setting-1 = <0x09400414>; - pll-setting-2 = <0x927E0000>; - pll-setting-3 = <0xac5f69e5>; - pll-setting-4 = <0xfe18>; - pll-setting-5 = <0x8000fff>; - pll-setting-6 = <0x78000>; - pll-setting-7 = <0xe0004>; - pll-setting-8 = <0xe000c>; -}; - -&usb3_phy_v2 { - status = "okay"; - portnum = <0>; - gpio-vbus-power = "GPIOD_9"; - gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>; -}; - -&pwm_ef { - status = "okay"; - /* pinctrl-0 = <&pwm_e_pins>; */ - /* pinctrl-names = "default"; */ -}; - -/* This is connected to the Bluetooth module: */ -&uart_a { - status = "okay"; - /* pinctrl-0 = <&a_uart_pins>; */ - /* pinctrl-names = "default"; */ - uart-has-rtscts; -}; - -&spifc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spifc_pins>; - max-frequency = <24000000>; - max-cs = <2>; - /* 512M */ - clocks = <&clkc CLKID_FCLK_DIV2>, - <&clkc CLKID_SPIFC_MUX>, - <&clkc CLKID_SPIFC_DIV>, - <&clkc CLKID_SPIFC_GATE>, - <&clkc CLKID_SPIFC_XTAL_GATE>; - clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate"; -}; - -&spicc0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spicc0_pins1>; - cs-gpios = <&gpio GPIOA_8 0>, - <&gpio GPIOA_9 0>; -}; - -&spicc1 { - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&spicc1_pins1>; - cs-gpios = <&gpio GPIOA_14 0>; -};
diff --git a/board/amlogic/Kconfig b/board/amlogic/Kconfig index 60b7709..a05ea96 100644 --- a/board/amlogic/Kconfig +++ b/board/amlogic/Kconfig
@@ -513,54 +513,6 @@ help Select C2 VENUS BX config -config C2_BLA4_P0 - bool "C2_BLA4_P0" - select TARGET_C2_BLA4_P0 - help - Select C2 BLA4 P0 config - -config C2_BLA4_P1 - bool "C2_BLA4_P1" - select TARGET_C2_BLA4_P1 - help - Select C2 BLA4 P1 config - -config C2_BLA4_P2 - bool "C2_BLA4_P2" - select TARGET_C2_BLA4_P2 - help - Select C2 BLA4 P2 config - -config C2_BLA4_BX - bool "C2_BLA4_BX" - select TARGET_C2_BLA4_BX - help - Select C2 BLA4 BX config - -config C2_2RS4_P1 - bool "C2_2RS4_P1" - select TARGET_C2_2RS4_P1 - help - Select C2 2RS4 P1 config - -config C2_2RS4_P2 - bool "C2_2RS4_P2" - select TARGET_C2_2RS4_P2 - help - Select C2 2RS4 P2 config - -config C2_XUA4_P1 - bool "C2_XUA4_P1" - select TARGET_C2_XUA4_P1 - help - Select C2 XUA4 P1 config - -config C2_XUA4_BX - bool "C2_XUA4_BX" - select TARGET_C2_XUA4_BX - help - Select C2 XUA4 BX config - endchoice config TARGET_C2_SKT @@ -616,38 +568,6 @@ bool "C2 VENUS BX board" depends on C2_VENUS_BX -config TARGET_C2_BLA4_P0 - bool "C2 BLA4 P0 board" - depends on C2_BLA4_P0 - -config TARGET_C2_BLA4_P1 - bool "C2 BLA4 P1 board" - depends on C2_BLA4_P1 - -config TARGET_C2_BLA4_P2 - bool "C2 BLA4 P2 board" - depends on C2_BLA4_P2 - -config TARGET_C2_BLA4_BX - bool "C2 BLA4 BX board" - depends on C2_BLA4_BX - -config TARGET_C2_2RS4_P1 - bool "C2 2RS4 P1 board" - depends on C2_2RS4_P1 - -config TARGET_C2_2RS4_P2 - bool "C2 2RS4 P2 board" - depends on C2_2RS4_P2 - -config TARGET_C2_XUA4_P1 - bool "C2 XUA4 P1 board" - depends on C2_XUA4_P1 - -config TARGET_C2_XUA4_BX - bool "C2 XUA4 BX board" - depends on C2_XUA4_BX - endif if MESON_G12A @@ -738,22 +658,6 @@ source "board/amlogic/c2_venus_bx/Kconfig" -source "board/amlogic/c2_bla4_p0/Kconfig" - -source "board/amlogic/c2_bla4_p1/Kconfig" - -source "board/amlogic/c2_bla4_p2/Kconfig" - -source "board/amlogic/c2_bla4_bx/Kconfig" - -source "board/amlogic/c2_2rs4_p1/Kconfig" - -source "board/amlogic/c2_2rs4_p2/Kconfig" - -source "board/amlogic/c2_xua4_p1/Kconfig" - -source "board/amlogic/c2_xua4_bx/Kconfig" - source "board/amlogic/g12a_u200_v1/Kconfig" source "board/amlogic/g12b_w400_v1/Kconfig"
diff --git a/board/amlogic/c2_2rs4_p1/Kconfig b/board/amlogic/c2_2rs4_p1/Kconfig deleted file mode 100644 index 05e3f8f..0000000 --- a/board/amlogic/c2_2rs4_p1/Kconfig +++ /dev/null
@@ -1,37 +0,0 @@ -if TARGET_C2_2RS4_P1 - -config SYS_SOC - default "c2" - -config SYS_BOARD - default "c2_2rs4_p1" - -config SYS_VENDOR - default "amlogic" - -config SYS_CONFIG_NAME - default "c2_2rs4_p1" - -config DTB_BIND_KERNEL - bool "load dtb from boot part but not flash rsv" - default n - -config CMD_PLLTEST - bool "support plltest command" - default y - help - support plltest command - -config I2C_REGULATOR - bool "use i2c regulator to configure vddee" - default n - -config DDR_WINDOWING_BOOT - bool "enable/disable ddr windowing boot" - default n - -config LED_AW210XX - bool "enable/disable AW210XX LED" - default y - -endif
diff --git a/board/amlogic/c2_2rs4_p1/Makefile b/board/amlogic/c2_2rs4_p1/Makefile deleted file mode 100644 index 0403c0c..0000000 --- a/board/amlogic/c2_2rs4_p1/Makefile +++ /dev/null
@@ -1 +0,0 @@ -obj-y += $(BOARD).o
diff --git a/board/amlogic/c2_2rs4_p1/aml-user-key.sig b/board/amlogic/c2_2rs4_p1/aml-user-key.sig deleted file mode 100644 index 0f89a75..0000000 --- a/board/amlogic/c2_2rs4_p1/aml-user-key.sig +++ /dev/null Binary files differ
diff --git a/board/amlogic/c2_2rs4_p1/c2_2rs4_p1.c b/board/amlogic/c2_2rs4_p1/c2_2rs4_p1.c deleted file mode 100644 index e345687..0000000 --- a/board/amlogic/c2_2rs4_p1/c2_2rs4_p1.c +++ /dev/null
@@ -1,287 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2024 Amlogic, Inc. All rights reserved. - */ - -#include <common.h> -#include <asm/io.h> -#include <malloc.h> -#include <errno.h> -#include <environment.h> -#include <fdt_support.h> -#include <linux/libfdt.h> -#include <amlogic/cpu_id.h> -#include <asm/arch/secure_apb.h> -#include <asm/arch/pinctrl_init.h> -#include <linux/sizes.h> -#include <asm-generic/gpio.h> -#include <dm.h> -#include <asm/armv8/mmu.h> -#include <amlogic/aml_v3_burning.h> -#include <amlogic/aml_v2_burning.h> -#include <amlogic/leds-aw210xx.h> -#include <linux/mtd/partitions.h> - -DECLARE_GLOBAL_DATA_PTR; - -int serial_set_pin_port(unsigned long port_base) -{ - return 0; -} - -int dram_init(void) -{ - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -unsigned int get_dram_size(void) -{ - // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 -#if defined(CONFIG_SYS_MEM_TOP_HIDE) - return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; -#else - return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); -#endif /* CONFIG_SYS_MEM_TOP_HIDE */ -} - - -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = get_dram_size(); - return 0; -} - -/* secondary_boot_func - * this function should be write with asm, here, is is only for compiling pass - * */ -void secondary_boot_func(void) -{ -} - -int board_eth_init(bd_t *bis) -{ - return 0; -} - -int active_clk(void) -{ - struct udevice *clk = NULL; - int err; - - err = uclass_get_device_by_name(UCLASS_CLK, - "xtal-clk", &clk); - if (err) { - pr_err("Can't find xtal-clk clock (%d)\n", err); - return err; - } - err = uclass_get_device_by_name(UCLASS_CLK, - "clock-controller@0", &clk); - if (err) { - pr_err("Can't find clock-controller@0 clock (%d)\n", err); - return err; - } - - return 0; -} - -void board_init_mem(void) { - /* config bootm low size, make sure whole dram/psram space can be used */ - phys_size_t ram_size; - char *env_tmp; - env_tmp = env_get("bootm_size"); - if (!env_tmp) { - ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); - env_set_hex("bootm_low", 0); - env_set_hex("bootm_size", ram_size); - } -} - -int board_init(void) -{ - unsigned int value; - - printf("board init\n"); - - /* set GPIOB_3 to low before emmc init */ - value = readl(PADCTRL_PIN_MUX_REG3); - /* set to gpio pin */ - writel(value & ~(0xf << 12), PADCTRL_PIN_MUX_REG3); - value = readl(PADCTRL_GPIOB_OEN); - /* enable gpio output */ - writel(value & ~(0x1 << 3), PADCTRL_GPIOB_OEN); - value = readl(PADCTRL_GPIOB_O); - /* set output value to low */ - writel(value & ~(0x1 << 3), PADCTRL_GPIOB_O); - udelay(20000); - - //Please keep try usb boot first in board_init, as other init before usb may cause burning failure -#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) - if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2))) - { aml_v3_factory_usb_burning(0, gd->bd); } -#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) - - pinctrl_devices_active(PIN_CONTROLLER_NUM); - active_clk(); - - // set to white by default - sys_led_init(WHITE); - return 0; -} - -int board_late_init(void) -{ - board_init_mem(); - -#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard - aml_try_factory_sdcard_burning(0, gd->bd); -#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE - //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003' -#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) - if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2)) - { aml_v3_factory_usb_burning(0, gd->bd); } -#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) - - return 0; -} - - -phys_size_t get_effective_memsize(void) -{ -#ifdef UBOOT_RUN_IN_SRAM - return 0x180000; /* SRAM 1.5MB */ -#else - // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 -#if defined(CONFIG_SYS_MEM_TOP_HIDE) - return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; -#else - return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); -#endif /* CONFIG_SYS_MEM_TOP_HIDE */ -#endif /* UBOOT_RUN_IN_SRAM */ -} - -static struct mm_region bd_mem_map[] = { - { - .virt = 0x00000000UL, - .phys = 0x00000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = bd_mem_map; - -int mach_cpu_init(void) { - printf("\nmach_cpu_init\n"); - return 0; -} - -int ft_board_setup(void *blob, bd_t *bd) -{ - /* eg: bl31/32 rsv */ - return 0; -} - - -int do_get_hw_id(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) -{ - unsigned int hw_id = 0, ret = 0; - char hw_id_str[8] = {0}; // eg: 0x0A - - /* - * HWID_4 : GPIOD_9 - * HWID_3 : GPIOD_8 - * HWID_2 : GPIOD_7 - * HWID_1 : GPIOD_6 - * HWID_0 : GPIOD_5 - * - */ - /* disable gpio pull */ - ret = readl(PADCTRL_GPIOD_PULL_EN); - writel(ret & (~(0x1F << 5)), PADCTRL_GPIOD_PULL_EN); - - /* pin mux to gpio pin */ - /* GPIOD_5, GPIOD_6, GPIOD_7 */ - ret = readl(PADCTRL_PIN_MUX_REG0); - writel(ret & (~(0xFFF << 20)), PADCTRL_PIN_MUX_REG0); - /* GPIOD_8, GPIOD_9 */ - ret = readl(PADCTRL_PIN_MUX_REG1); - writel(ret & (~(0xFF << 0)), PADCTRL_PIN_MUX_REG1); - - /* enable input */ - ret = readl(PADCTRL_GPIOD_OEN); - writel(ret | (0x1F << 5), PADCTRL_GPIOD_OEN); - - /* read hw id */ - ret = readl(PADCTRL_GPIOD_I); - hw_id = (ret >> 5) & 0x1F; - - snprintf(hw_id_str, sizeof(hw_id_str), "0x%02x", hw_id); - env_set("hw_id", hw_id_str); - return 0; -} - -U_BOOT_CMD( - get_hw_id, 1, 0, do_get_hw_id, "get HW_ID and env_set 'hw_id'\n", "get_hw_id" -); - -/* partition table */ -/* partition table for spinand flash */ -#ifdef CONFIG_SPI_NAND -static const struct mtd_partition spinand_partitions[] = { - { - .name = "logo", - .offset = 0, - .size = 2 * SZ_1M, - }, - { - .name = "recovery", - .offset = 0, - .size = 16 * SZ_1M, - }, - { - .name = "boot", - .offset = 0, - .size = 16 * SZ_1M, - }, - { - .name = "system", - .offset = 0, - .size = 64 * SZ_1M, - }, - /* last partition get the rest capacity */ - { - .name = "data", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - } -}; -struct mtd_partition *get_partition_table(int *partitions) -{ - *partitions = ARRAY_SIZE(spinand_partitions); - return spinand_partitions; -} -#endif /* CONFIG_SPI_NAND */ - -int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;} - -int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;} - -void __attribute__((weak)) set_working_fdt_addr(ulong addr) {} - -int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;} - -void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c2_2rs4_p1/firmware/timing.c b/board/amlogic/c2_2rs4_p1/firmware/timing.c deleted file mode 100755 index ec2f8ee..0000000 --- a/board/amlogic/c2_2rs4_p1/firmware/timing.c +++ /dev/null
@@ -1,1095 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2024 Amlogic, Inc. All rights reserved. - */ - -#include <asm/arch/secure_apb.h> -#include <asm/arch/timing.h> -#include <asm/arch/ddr_define.h> - -/* board clk defines */ -#define CPU_CLK 1512 -#define TIMMING_MAX_CONFIG 1 -#define ENABLE_DDR3 0 -#define ENABLE_LPDDR4 1 - -ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = { -#if ENABLE_DDR3 -{ - .cfg_board_common_setting.timming_magic = 0, - .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, - .cfg_board_common_setting.timming_struct_version = 0, - .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), - .cfg_board_common_setting.timming_struct_real_size = 0, //0 - .cfg_board_common_setting.fast_boot = {0}, - .cfg_board_common_setting.ddr_func = 0, - .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, - .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR3, - .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0, - .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, - .cfg_board_common_setting.dram_cs0_base_add = 0, - .cfg_board_common_setting.dram_cs1_base_add = 0, - .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB, - .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, - .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, - .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE, - .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, - .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, - .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, - .cfg_board_common_setting.org_tdqs2dq = 0, - .cfg_board_common_setting.reserve1_test_function = {0}, - .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT, - .cfg_board_common_setting.ac_pinmux = - { - 0, 0, 0, 1, 2, 3, 0, 1, - 2, 3, 4, 5, 6, 7, 8, 9, - 10, 11, 12, 13, 14, 15, 0, 0, - 0, 0, 20, 21, 22, 0, 0, 25, - 26, 27, 0 - }, - .cfg_board_common_setting.ddr_dqs_swap = 0, - .cfg_board_common_setting.ddr_dq_remap = { - 0, 1, 2, 3, 4, 5, 6, 7, - 8, 9, 10, 11, 12, 13, 14, 15, - 16, 17, 18, 19, 20, 21, 22, 23, - 24, 25, 26, 27, 28, 29, 30, 31, - 32, 33, 34, 35, - }, //d0-d31 dm0 dm1 dm2 dm3 - .cfg_board_common_setting.ddr_vddee_setting = {0}, - .cfg_board_SI_setting_ps[0].DRAMFreq = 912, - .cfg_board_SI_setting_ps[0].PllBypassEn = 0, - .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM, - .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[0].reserve2 = 0, - .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, - .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, - .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, - .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, - .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { - 128, 128, 128 - 20, 128, 128, 128, 128, 128, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, - }, //total 36 - - .cfg_ddr_training_delay_ps[0].ac_trace_delay = { - 128, 128, 128 - 20, 128, 128, 128, 128, 128, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, - }, //total 36 - .cfg_ddr_training_delay_ps[0].write_dqs_delay = { - 128 - 1, 128 - 1, 128 + 48, 128 + 58, 128 + 32, 128 + 32, 128 + 32, 128 + 32 - }, - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay = { - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, - 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, - 128 + 128, 128 + 128, 128 + 128, 128 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - }, - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay = { - 896, 896, 896, 896, 896, 896, 896, 896 - }, //total 8 - .cfg_ddr_training_delay_ps[0].read_dqs_delay = { - 64, 64, 50, 40, 64, 64, 64, 64 - }, //total 8 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay = { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 - }, //total 72 - .cfg_ddr_training_delay_ps[0].soc_bit_vref = { - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32 + 5, 32, 32 + 5, - 32, 32 + 5, 32, 32 + 5 - }, - .cfg_ddr_training_delay_ps[0].dram_bit_vref = { - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32 - }, //total 36 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[0] = 0x0000007d,// 125 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[1] = 0x00000091,// 145 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[2] = 0x00000091,// 145 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[3] = 0x0000009b,// 155 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[4] = 0x000000a0,// 160 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[5] = 0x000000a0,// 160 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[6] = 0x000000a0,// 160 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[7] = 0x000000a0,// 160 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0] = 0x000000c2,// 194 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1] = 0x000000b0,// 176 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2] = 0x000000af,// 175 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3] = 0x000000b0,// 176 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4] = 0x000000c0,// 192 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5] = 0x000000c3,// 195 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6] = 0x000000b4,// 180 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7] = 0x000000be,// 190 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8] = 0x000000ba,// 186 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9] = 0x000000c1,// 193 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10] = 0x000000d5,// 213 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11] = 0x000000c1,// 193 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12] = 0x000000d0,// 208 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13] = 0x000000cc,// 204 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14] = 0x000000c3,// 195 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15] = 0x000000be,// 190 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16] = 0x000000c0,// 192 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17] = 0x000000c8,// 200 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18] = 0x000000e0,// 224 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19] = 0x000000e5,// 229 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20] = 0x000000e2,// 226 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21] = 0x000000ec,// 236 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22] = 0x000000ec,// 236 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23] = 0x000000e7,// 231 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24] = 0x000000e4,// 228 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25] = 0x000000e9,// 233 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26] = 0x000000e6,// 230 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27] = 0x000000eb,// 235 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28] = 0x000000f5,// 245 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29] = 0x000000e7,// 231 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30] = 0x000000fd,// 253 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31] = 0x000000e8,// 232 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32] = 0x000000e4,// 228 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33] = 0x000000ee,// 238 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34] = 0x000000ec,// 236 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35] = 0x000000f2,// 242 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0] = 0x0000038c,// 908 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1] = 0x0000037a,// 890 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2] = 0x0000039a,// 922 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3] = 0x00000395,// 917 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[0] = 0x0000007f-0x30,// 127 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[1] = 0x0000007d-0x30,// 125 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[2] = 0x0000006d-0x30,// 109 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[3] = 0x0000006f-0x30,// 111 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[4] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[5] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[6] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[7] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0] = 0x00000048-0x30,// 72 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1] = 0x00000044-0x30,// 68 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2] = 0x00000038-0x30,// 56 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3] = 0x0000003b-0x30,// 59 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4] = 0x00000049-0x30,// 73 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5] = 0x0000004b-0x30,// 75 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6] = 0x0000003b-0x30,// 59 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7] = 0x00000049-0x30,// 73 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9] = 0x00000040-0x30,// 64 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10] = 0x00000052-0x30,// 82 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11] = 0x00000039-0x30,// 57 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12] = 0x00000040-0x30,// 64 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13] = 0x00000045-0x30,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14] = 0x00000042-0x30,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15] = 0x00000034-0x30,// 52 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16] = 0x0000003c-0x30,// 60 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17] = 0x00000086-0x30,// 134 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18] = 0x0000003f-0x30,// 63 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19] = 0x00000048-0x30,// 72 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20] = 0x00000037-0x30,// 55 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21] = 0x00000048-0x30,// 72 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22] = (0x0000004e)-0x30,// 78 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23] = 0x00000044-0x30,// 68 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24] = 0x00000042-0x30,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25] = 0x00000047-0x30,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26] = 0x0000007f-0x30,// 127 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27] = 0x00000040-0x30,// 64 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28] = 0x00000052-0x30,// 82 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29] = 0x0000003d-0x30,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30] = (0x0000004e)-0x30,// 78 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31] = 0x0000003c-0x30,// 60 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32] = (0x0000003e)-0x30,// 62 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33] = 0x0000003f-0x30,// 63 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34] = 0x0000004c-0x30,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35] = 0x00000091-0x30,// 145 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71] = 0x00000000,// 0 - - .cfg_ddr_training_delay_ps[0].reserve_training_parameter = {0}, - .cfg_board_SI_setting_ps[1].DRAMFreq = 667, - .cfg_board_SI_setting_ps[1].PllBypassEn = 0, - .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, - .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, - .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[1].reserve2 = 0, - .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, - .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, - .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, - .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, - .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, - }, //total 36 - .cfg_ddr_training_delay_ps[1].ac_trace_delay = { - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, - }, //total 36 - .cfg_ddr_training_delay_ps[1].write_dqs_delay = { - 0, 0, 0, 0, 0, 0, 0, 0 - }, - .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50 - }, - .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { - 192, 192, 192, 192, 192, 192, 192, 192 - }, //total 8 - .cfg_ddr_training_delay_ps[1].read_dqs_delay = { - 64, 64, 64, 64, 64, 64, 64, 64 - }, //total 8 - .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 - }, //total 72 - .cfg_ddr_training_delay_ps[1].soc_bit_vref = { - 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40 - }, //total 44 - .cfg_ddr_training_delay_ps[1].dram_bit_vref = { - 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32 - }, //total 36 - .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0}, -}, -#endif - -#if ENABLE_LPDDR4 //LPDDR4 rank0,timing_config -{ - .cfg_board_common_setting.timming_magic = 0, - .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, - .cfg_board_common_setting.timming_struct_version = 0, - .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), - .cfg_board_common_setting.timming_struct_real_size = 0, //0 - .cfg_board_common_setting.fast_boot = { 0 }, - .cfg_board_common_setting.ddr_func = 0, - .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, - .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_LPDDR4, - .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH01, - .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, - .cfg_board_common_setting.dram_cs0_base_add = 0, - .cfg_board_common_setting.dram_cs1_base_add = 0, - .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB, - .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, - .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, - .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_1T_MODE, - .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, - .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, //DDR_WRITE_READ_DBI_DISABLE , - .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, - .cfg_board_common_setting.org_tdqs2dq = 0, - .cfg_board_common_setting.reserve1_test_function = { 0 }, - .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT, -#ifdef CONFIG_DDR_WINDOWING_BOOT - .cfg_board_common_setting.fast_boot[0] = 0x1, - .cfg_board_common_setting.fast_boot[3] = 0x46, -#endif - //lpddr4 ac pinmux - .cfg_board_common_setting.ac_pinmux = { - 0, 0, 0, 1, 0, 1, 1, 3, - 0, 4, 4, 2, 0, 0, 1, 0, - 2, 0, 0, 0, 0, 3, 0, 0, - 0, 0, 5, 5, 0, 0, 0, 0, - 0, 0, - }, - .cfg_board_common_setting.ddr_dqs_swap = 0, - - .cfg_board_common_setting.ddr_dq_remap = { - 1, 0, 3, 2, 7, 5, 6, 4, - 9, 15, 13, 14, 10, 11, 12, 8, - 21, 19, 20, 18, 17, 16, 22, 23, - 25, 26, 24, 27, 31, 29, 30, 28, - 32, 33, 34, 35 - }, //d0-d31 dm0 dm1 dm2 dm3 - - .cfg_board_common_setting.ddr_vddee_setting = { 0 }, - .cfg_board_SI_setting_ps[0].DRAMFreq = 1320, - .cfg_board_SI_setting_ps[0].PllBypassEn = 0, - .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_60_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_LPDDR4_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_LPDDR4_ODT_60_OHM, - .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_LPDDR4_AC_ODT_80_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[0].reserve2 = 0, - .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, //3000/11, - .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, //170, - .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, //280, //330 - .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 }, - .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { - 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 0 + 128, //0,0,0,0,0,0,0,0, - 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128, 128 + 20 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - }, //total 36 - - .cfg_ddr_training_delay_ps[0].ac_trace_delay = { - 64 + 128, 64 + 128, 64 + 128-64, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 128 + 128, //0,0,0,0,0,0,0,0, - 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128-40, 128 + 20 + 128-10, 128 + 0 + 128, 128 + 0 + 128+10, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - }, //total 36 - .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 }, - - .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x000000af,// 175 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x000000cd,// 205 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x000000aa,// 170 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x000000cd,// 205 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x000000af,// 175 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x000000cd,// 205 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x000000aa,// 170 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x000000cd,// 205 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x000001cd,// 461 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x000001cc,// 460 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x000001ba,// 442 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000001d8,// 472 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000001e1,// 481 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000001ce,// 462 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000001c6,// 454 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000001d0,// 464 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000001cc,// 460 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000001d9,// 473 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000001da,// 474 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000001c4,// 452 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000001d5,// 469 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000001ea,// 490 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000001e9,// 489 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000001e2,// 482 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000001ea,// 490 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000001d5,// 469 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000001c6,// 454 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000001ce,// 462 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000001b5,// 437 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000001c7,// 455 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000001d3,// 467 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000001d1,// 465 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000001c4,// 452 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000001eb,// 491 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000001d1,// 465 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000001f7,// 503 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000001d8,// 472 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000001cf,// 463 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000001d3,// 467 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000001c9,// 457 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000001de,// 478 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x000001cd,// 461 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x000001cc,// 460 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x000001ba,// 442 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x000001d8,// 472 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x000001e1,// 481 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x000001ce,// 462 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x000001c6,// 454 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x000001d0,// 464 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x000001cc,// 460 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x000001d9,// 473 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x000001da,// 474 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x000001c4,// 452 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x000001d5,// 469 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x000001ea,// 490 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x000001e9,// 489 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x000001e2,// 482 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x000001ea,// 490 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x000001d5,// 469 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x000001c6,// 454 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x000001ce,// 462 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x000001b5,// 437 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x000001c7,// 455 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x000001d3,// 467 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x000001d1,// 465 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x000001c4,// 452 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x000001eb,// 491 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x000001d1,// 465 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x000001f7,// 503 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x000001d8,// 472 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x000001cf,// 463 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x000001d3,// 467 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x000001c9,// 457 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x000001de,// 478 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x000003ab,// 939 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000383,// 899 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000395,// 917 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x00000378,// 888 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x000003ab,// 939 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000383,// 899 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000395,// 917 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000378,// 888 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x0000007e,// 126 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x00000088,// 136 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000070,// 112 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007a,// 122 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x0000007e,// 126 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000088,// 136 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000070,// 112 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x0000007a,// 122 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000044,// 68 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000051,// 81 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x00000036,// 54 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000054,// 84 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x0000003d,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000045,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000051,// 81 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000037,// 55 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x0000003d,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000052,// 82 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x0000005b,// 91 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x0000004c,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000005a,// 90 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x0000004b,// 75 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000042,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x0000004f,// 79 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000030,// 48 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000042,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000004c,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000041,// 65 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000058,// 88 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000045,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000041,// 65 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000056,// 86 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003f,// 63 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000055,// 85 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x0000003e,// 62 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000034,// 52 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x00000031,// 49 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000036,// 54 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000040,// 64 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000044,// 68 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000051,// 81 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000036,// 54 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000054,// 84 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x0000003d,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000045,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000051,// 81 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000037,// 55 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x0000003d,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000052,// 82 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x0000005b,// 91 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x0000004c,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x0000005a,// 90 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x0000004b,// 75 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000042,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x0000004f,// 79 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000030,// 48 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000042,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x0000004c,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000041,// 65 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000058,// 88 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000045,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000041,// 65 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000056,// 86 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x0000003f,// 63 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000055,// 85 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x0000003e,// 62 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000034,// 52 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000031,// 49 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000036,// 54 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000040,// 64 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[0]=0,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[1]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[2]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[3]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[4]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[5]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[6]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[7]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[8]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[9]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[10]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[11]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[12]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[13]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[14]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[15]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[16]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[17]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[18]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[19]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[20]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[21]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[22]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[23]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[24]=0x00000016,// 22 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[25]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[26]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[27]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[28]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[29]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[30]=0x00000016,// 22 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[31]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[32]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[33]=0x00000016,// 22 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[34]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[35]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[36]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[37]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[38]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[39]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[40]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[41]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[42]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[43]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[0]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[1]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[2]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[3]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[4]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[5]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[6]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[7]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[8]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[9]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[10]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[11]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[12]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[13]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[14]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[15]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[16]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[17]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[18]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[19]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[20]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[21]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[22]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[23]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[24]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[25]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[26]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[27]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[28]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[29]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[30]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[31]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[32]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[33]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[34]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[35]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { - (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, - (1 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, - (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, - (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, - }, - .cfg_board_SI_setting_ps[1].DRAMFreq = 667, - .cfg_board_SI_setting_ps[1].PllBypassEn = 0, - .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, - .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, - .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[1].reserve2 = 0, - .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, - .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, - .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, - .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 }, - .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, - }, //total 36 - .cfg_ddr_training_delay_ps[1].ac_trace_delay = { - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, - }, //total 36 - - .cfg_ddr_training_delay_ps[1].write_dqs_delay = { - 0, 0, 0, 0, 0, 0, 0, 0 - }, - .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - }, - .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { - 192, 192, 192, 192, 192, 192, 192, 192 - }, //total 8 - .cfg_ddr_training_delay_ps[1].read_dqs_delay = { - 64, 64, 64, 64, 64, 64, 64, 64 - }, //total 8 - .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 - }, //total 72 - .cfg_ddr_training_delay_ps[1].soc_bit_vref = { - 0, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40 - }, //total 44 - .cfg_ddr_training_delay_ps[1].dram_bit_vref = { - 0, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32 - }, //total 36 - .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 }, -}, -#endif -}; -//ddr timing end - -pll_set_t __pll_setting = { - .cpu_clk = CPU_CLK / 24 * 24, -#ifdef CONFIG_PXP_EMULATOR - .pxp = 1, -#else - .pxp = 0, -#endif - .spi_ctrl = 0, - .lCustomerID = AML_CUSTOMER_ID, - .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */ - .log_ctrl = (1 << 7) | /* (1<<7), print bl2 log into buffer */ -#ifdef CONFIG_SILENT_CONSOLE - (1<<6), /* do not print log buffer */ -#else - (0<<6), /* print log buffer before run bl31 */ -#endif - .ddr_timming_save_mode = 1, -}; - -ddr_reg_t __ddr_reg[] = { - /* demo, user defined override register */ - {0xaabbccdd, 0, 0, 0, 0, 0}, - {0x11223344, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0}, -}; - - - -#define VCCK_VAL AML_VCCK_INIT_VOLTAGE -#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE -/* VCCK PWM table */ -#if (VCCK_VAL == 1039) - #define VCCK_VAL_REG 0x00000022 -#elif (VCCK_VAL == 1029) - #define VCCK_VAL_REG 0x00010021 -#elif (VCCK_VAL == 1019) - #define VCCK_VAL_REG 0x00020020 -#elif (VCCK_VAL == 1009) - #define VCCK_VAL_REG 0x0003001f -#elif (VCCK_VAL == 999) - #define VCCK_VAL_REG 0x0004001e -#elif (VCCK_VAL == 989) - #define VCCK_VAL_REG 0x0005001d -#elif (VCCK_VAL == 979) - #define VCCK_VAL_REG 0x0006001c -#elif (VCCK_VAL == 969) - #define VCCK_VAL_REG 0x0007001b -#elif (VCCK_VAL == 959) - #define VCCK_VAL_REG 0x0008001a -#elif (VCCK_VAL == 949) - #define VCCK_VAL_REG 0x00090019 -#elif (VCCK_VAL == 939) - #define VCCK_VAL_REG 0x000a0018 -#elif (VCCK_VAL == 929) - #define VCCK_VAL_REG 0x000b0017 -#elif (VCCK_VAL == 919) - #define VCCK_VAL_REG 0x000c0016 -#elif (VCCK_VAL == 909) - #define VCCK_VAL_REG 0x000d0015 -#elif (VCCK_VAL == 899) - #define VCCK_VAL_REG 0x000e0014 -#elif (VCCK_VAL == 889) - #define VCCK_VAL_REG 0x000f0013 -#elif (VCCK_VAL == 879) - #define VCCK_VAL_REG 0x00100012 -#elif (VCCK_VAL == 869) - #define VCCK_VAL_REG 0x00110011 -#elif (VCCK_VAL == 859) - #define VCCK_VAL_REG 0x00120010 -#elif (VCCK_VAL == 849) - #define VCCK_VAL_REG 0x0013000f -#elif (VCCK_VAL == 839) - #define VCCK_VAL_REG 0x0014000e -#elif (VCCK_VAL == 829) - #define VCCK_VAL_REG 0x0015000d -#elif (VCCK_VAL == 819) - #define VCCK_VAL_REG 0x0016000c -#elif (VCCK_VAL == 809) - #define VCCK_VAL_REG 0x0017000b -#elif (VCCK_VAL == 799) - #define VCCK_VAL_REG 0x0018000a -#elif (VCCK_VAL == 789) - #define VCCK_VAL_REG 0x00190009 -#elif (VCCK_VAL == 779) - #define VCCK_VAL_REG 0x001a0008 -#elif (VCCK_VAL == 769) - #define VCCK_VAL_REG 0x001b0007 -#elif (VCCK_VAL == 759) - #define VCCK_VAL_REG 0x001c0006 -#elif (VCCK_VAL == 749) - #define VCCK_VAL_REG 0x001d0005 -#elif (VCCK_VAL == 739) - #define VCCK_VAL_REG 0x001e0004 -#elif (VCCK_VAL == 729) - #define VCCK_VAL_REG 0x001f0003 -#elif (VCCK_VAL == 719) - #define VCCK_VAL_REG 0x00200002 -#elif (VCCK_VAL == 709) - #define VCCK_VAL_REG 0x00210001 -#elif (VCCK_VAL == 699) - #define VCCK_VAL_REG 0x00220000 -#else - #error "VCCK val out of range\n" -#endif - -/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/ -#ifdef CONFIG_I2C_REGULATOR -#if (VDDEE_VAL == 711) - #define VDDEE_VAL_REG 0xb -#elif (VDDEE_VAL == 721) - #define VDDEE_VAL_REG 0xc -#elif (VDDEE_VAL == 731) - #define VDDEE_VAL_REG 0xd -#elif (VDDEE_VAL == 741) - #define VDDEE_VAL_REG 0xe -#elif (VDDEE_VAL == 751) - #define VDDEE_VAL_REG 0xf -#elif (VDDEE_VAL == 761) - #define VDDEE_VAL_REG 0x10 -#elif (VDDEE_VAL == 771) - #define VDDEE_VAL_REG 0x11 -#elif (VDDEE_VAL == 781) - #define VDDEE_VAL_REG 0x12 -#elif (VDDEE_VAL == 791) - #define VDDEE_VAL_REG 0x13 -#elif (VDDEE_VAL == 801) - #define VDDEE_VAL_REG 0x14 -#elif (VDDEE_VAL == 811) - #define VDDEE_VAL_REG 0x15 -#elif (VDDEE_VAL == 821) - #define VDDEE_VAL_REG 0x16 -#elif (VDDEE_VAL == 831) - #define VDDEE_VAL_REG 0x17 -#elif (VDDEE_VAL == 841) - #define VDDEE_VAL_REG 0x18 -#elif (VDDEE_VAL == 851) - #define VDDEE_VAL_REG 0x19 -#elif (VDDEE_VAL == 861) - #define VDDEE_VAL_REG 0x1a -#elif (VDDEE_VAL == 871) - #define VDDEE_VAL_REG 0x1b -#elif (VDDEE_VAL == 881) - #define VDDEE_VAL_REG 0x1c -#elif (VDDEE_VAL == 891) - #define VDDEE_VAL_REG 0x1d -#else - #error "VDDEE val out of range\n" -#endif - -#else - -#if (VDDEE_VAL == 711) - #define VDDEE_VAL_REG 0x120000 -#elif (VDDEE_VAL == 721) - #define VDDEE_VAL_REG 0x110001 -#elif (VDDEE_VAL == 731) - #define VDDEE_VAL_REG 0x100002 -#elif (VDDEE_VAL == 741) - #define VDDEE_VAL_REG 0xf0003 -#elif (VDDEE_VAL == 751) - #define VDDEE_VAL_REG 0xe0004 -#elif (VDDEE_VAL == 761) - #define VDDEE_VAL_REG 0xd0005 -#elif (VDDEE_VAL == 771) - #define VDDEE_VAL_REG 0xc0006 -#elif (VDDEE_VAL == 781) - #define VDDEE_VAL_REG 0xb0007 -#elif (VDDEE_VAL == 791) - #define VDDEE_VAL_REG 0xa0008 -#elif (VDDEE_VAL == 801) - #define VDDEE_VAL_REG 0x90009 -#elif (VDDEE_VAL == 811) - #define VDDEE_VAL_REG 0x8000a -#elif (VDDEE_VAL == 821) - #define VDDEE_VAL_REG 0x7000b -#elif (VDDEE_VAL == 831) - #define VDDEE_VAL_REG 0x6000c -#elif (VDDEE_VAL == 841) - #define VDDEE_VAL_REG 0x5000d -#elif (VDDEE_VAL == 851) - #define VDDEE_VAL_REG 0x4000e -#elif (VDDEE_VAL == 861) - #define VDDEE_VAL_REG 0x3000f -#elif (VDDEE_VAL == 871) - #define VDDEE_VAL_REG 0x20010 -#elif (VDDEE_VAL == 881) - #define VDDEE_VAL_REG 0x10011 -#elif (VDDEE_VAL == 891) - #define VDDEE_VAL_REG 0x12 -#else - #error "VDDEE val out of range\n" -#endif -#endif - -/* for PWM use */ -/* - * GPIOE_0 PWM_A VDDEE_PWM - * - * GPIOE_1 PWM_B VCCK_PWM - */ -/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */ -#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400) -#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400) - -/* pwm clock and pwm controller */ -#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800) -#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400) -#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400) -#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400) - -bl2_reg_t __bl2_reg[] = { -#ifdef CONFIG_I2C_REGULATOR - /* demo, user defined override register */ - {0, 0, 0xffffffff, 0, 0, 0}, - {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, - {PWMAB_MISC_REG_AB, 0x1 << 1, 0x1 << 1, 0, BL2_INIT_STAGE_1, 0}, - /* Set GPIOA_5 low */ - {PADCTRL_GPIOA_O, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_GPIOA_OEN, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, - /* Set GPIOD_10 low */ - {PADCTRL_GPIOD_O, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, - /* Set GPIOX_11 low */ - {PADCTRL_GPIOX_O, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_GPIOX_OEN, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, - /* set pwm A and pwm B clock rate to 24M, enable them */ - {CLKTREE_PWM_CLK_AB_CTRL, 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, - /* set GPIOE_0 GPIOE_1 drive strength to 3*/ - {PADCTRL_GPIOE_DS, 0x3 << 2, 0x3 << 2, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, -#ifdef CONFIG_PDVFS_ENABLE - /* table_id, ee_voltage, ...... */ - {1, 0x11, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, - {2, 0x14, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, - {3, 0x16, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, -#else - {0x0, VDDEE_VAL_REG, 0x0, 0, BL2_INIT_STAGE_I2C_REGULATOR, 0}, -#endif -#else - /* demo, user defined override register */ - {0, 0, 0xffffffff, 0, 0, 0}, -#ifdef CONFIG_PDVFS_ENABLE - {PWMAB_PWM_A, 0x000c0006, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, - {PWMAB_PWM_A, 0x00090009, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, - {PWMAB_PWM_A, 0x0007000b, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, -#else - {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, -#endif - {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, - {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0}, - /* Set GPIOA_5(SOC_LEDRING_EN) low */ - {PADCTRL_GPIOA_O, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_GPIOA_OEN, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, - /* Set GPIOD_10(BAT_HEALTH_CHECK_EN) low */ - {PADCTRL_GPIOD_O, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, - /* Set GPIOX_11(BAT_VSENSE_EN) low */ - {PADCTRL_GPIOX_O, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_GPIOX_OEN, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, - /* set pwm A and pwm B clock rate to 24M, enable them */ - {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, - /* set GPIOE_0 GPIOE_1 drive strength to 3*/ - {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, -#endif -};
diff --git a/board/amlogic/c2_2rs4_p2/Kconfig b/board/amlogic/c2_2rs4_p2/Kconfig deleted file mode 100644 index 48d8107..0000000 --- a/board/amlogic/c2_2rs4_p2/Kconfig +++ /dev/null
@@ -1,37 +0,0 @@ -if TARGET_C2_2RS4_P2 - -config SYS_SOC - default "c2" - -config SYS_BOARD - default "c2_2rs4_p2" - -config SYS_VENDOR - default "amlogic" - -config SYS_CONFIG_NAME - default "c2_2rs4_p2" - -config DTB_BIND_KERNEL - bool "load dtb from boot part but not flash rsv" - default n - -config CMD_PLLTEST - bool "support plltest command" - default y - help - support plltest command - -config I2C_REGULATOR - bool "use i2c regulator to configure vddee" - default n - -config DDR_WINDOWING_BOOT - bool "enable/disable ddr windowing boot" - default n - -config LED_AW210XX - bool "enable/disable AW210XX LED" - default y - -endif
diff --git a/board/amlogic/c2_2rs4_p2/Makefile b/board/amlogic/c2_2rs4_p2/Makefile deleted file mode 100644 index 0403c0c..0000000 --- a/board/amlogic/c2_2rs4_p2/Makefile +++ /dev/null
@@ -1 +0,0 @@ -obj-y += $(BOARD).o
diff --git a/board/amlogic/c2_2rs4_p2/aml-user-key.sig b/board/amlogic/c2_2rs4_p2/aml-user-key.sig deleted file mode 100644 index 0f89a75..0000000 --- a/board/amlogic/c2_2rs4_p2/aml-user-key.sig +++ /dev/null Binary files differ
diff --git a/board/amlogic/c2_2rs4_p2/c2_2rs4_p2.c b/board/amlogic/c2_2rs4_p2/c2_2rs4_p2.c deleted file mode 100644 index e345687..0000000 --- a/board/amlogic/c2_2rs4_p2/c2_2rs4_p2.c +++ /dev/null
@@ -1,287 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2024 Amlogic, Inc. All rights reserved. - */ - -#include <common.h> -#include <asm/io.h> -#include <malloc.h> -#include <errno.h> -#include <environment.h> -#include <fdt_support.h> -#include <linux/libfdt.h> -#include <amlogic/cpu_id.h> -#include <asm/arch/secure_apb.h> -#include <asm/arch/pinctrl_init.h> -#include <linux/sizes.h> -#include <asm-generic/gpio.h> -#include <dm.h> -#include <asm/armv8/mmu.h> -#include <amlogic/aml_v3_burning.h> -#include <amlogic/aml_v2_burning.h> -#include <amlogic/leds-aw210xx.h> -#include <linux/mtd/partitions.h> - -DECLARE_GLOBAL_DATA_PTR; - -int serial_set_pin_port(unsigned long port_base) -{ - return 0; -} - -int dram_init(void) -{ - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -unsigned int get_dram_size(void) -{ - // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 -#if defined(CONFIG_SYS_MEM_TOP_HIDE) - return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; -#else - return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); -#endif /* CONFIG_SYS_MEM_TOP_HIDE */ -} - - -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = get_dram_size(); - return 0; -} - -/* secondary_boot_func - * this function should be write with asm, here, is is only for compiling pass - * */ -void secondary_boot_func(void) -{ -} - -int board_eth_init(bd_t *bis) -{ - return 0; -} - -int active_clk(void) -{ - struct udevice *clk = NULL; - int err; - - err = uclass_get_device_by_name(UCLASS_CLK, - "xtal-clk", &clk); - if (err) { - pr_err("Can't find xtal-clk clock (%d)\n", err); - return err; - } - err = uclass_get_device_by_name(UCLASS_CLK, - "clock-controller@0", &clk); - if (err) { - pr_err("Can't find clock-controller@0 clock (%d)\n", err); - return err; - } - - return 0; -} - -void board_init_mem(void) { - /* config bootm low size, make sure whole dram/psram space can be used */ - phys_size_t ram_size; - char *env_tmp; - env_tmp = env_get("bootm_size"); - if (!env_tmp) { - ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); - env_set_hex("bootm_low", 0); - env_set_hex("bootm_size", ram_size); - } -} - -int board_init(void) -{ - unsigned int value; - - printf("board init\n"); - - /* set GPIOB_3 to low before emmc init */ - value = readl(PADCTRL_PIN_MUX_REG3); - /* set to gpio pin */ - writel(value & ~(0xf << 12), PADCTRL_PIN_MUX_REG3); - value = readl(PADCTRL_GPIOB_OEN); - /* enable gpio output */ - writel(value & ~(0x1 << 3), PADCTRL_GPIOB_OEN); - value = readl(PADCTRL_GPIOB_O); - /* set output value to low */ - writel(value & ~(0x1 << 3), PADCTRL_GPIOB_O); - udelay(20000); - - //Please keep try usb boot first in board_init, as other init before usb may cause burning failure -#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) - if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2))) - { aml_v3_factory_usb_burning(0, gd->bd); } -#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) - - pinctrl_devices_active(PIN_CONTROLLER_NUM); - active_clk(); - - // set to white by default - sys_led_init(WHITE); - return 0; -} - -int board_late_init(void) -{ - board_init_mem(); - -#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard - aml_try_factory_sdcard_burning(0, gd->bd); -#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE - //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003' -#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) - if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2)) - { aml_v3_factory_usb_burning(0, gd->bd); } -#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) - - return 0; -} - - -phys_size_t get_effective_memsize(void) -{ -#ifdef UBOOT_RUN_IN_SRAM - return 0x180000; /* SRAM 1.5MB */ -#else - // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 -#if defined(CONFIG_SYS_MEM_TOP_HIDE) - return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; -#else - return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); -#endif /* CONFIG_SYS_MEM_TOP_HIDE */ -#endif /* UBOOT_RUN_IN_SRAM */ -} - -static struct mm_region bd_mem_map[] = { - { - .virt = 0x00000000UL, - .phys = 0x00000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = bd_mem_map; - -int mach_cpu_init(void) { - printf("\nmach_cpu_init\n"); - return 0; -} - -int ft_board_setup(void *blob, bd_t *bd) -{ - /* eg: bl31/32 rsv */ - return 0; -} - - -int do_get_hw_id(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) -{ - unsigned int hw_id = 0, ret = 0; - char hw_id_str[8] = {0}; // eg: 0x0A - - /* - * HWID_4 : GPIOD_9 - * HWID_3 : GPIOD_8 - * HWID_2 : GPIOD_7 - * HWID_1 : GPIOD_6 - * HWID_0 : GPIOD_5 - * - */ - /* disable gpio pull */ - ret = readl(PADCTRL_GPIOD_PULL_EN); - writel(ret & (~(0x1F << 5)), PADCTRL_GPIOD_PULL_EN); - - /* pin mux to gpio pin */ - /* GPIOD_5, GPIOD_6, GPIOD_7 */ - ret = readl(PADCTRL_PIN_MUX_REG0); - writel(ret & (~(0xFFF << 20)), PADCTRL_PIN_MUX_REG0); - /* GPIOD_8, GPIOD_9 */ - ret = readl(PADCTRL_PIN_MUX_REG1); - writel(ret & (~(0xFF << 0)), PADCTRL_PIN_MUX_REG1); - - /* enable input */ - ret = readl(PADCTRL_GPIOD_OEN); - writel(ret | (0x1F << 5), PADCTRL_GPIOD_OEN); - - /* read hw id */ - ret = readl(PADCTRL_GPIOD_I); - hw_id = (ret >> 5) & 0x1F; - - snprintf(hw_id_str, sizeof(hw_id_str), "0x%02x", hw_id); - env_set("hw_id", hw_id_str); - return 0; -} - -U_BOOT_CMD( - get_hw_id, 1, 0, do_get_hw_id, "get HW_ID and env_set 'hw_id'\n", "get_hw_id" -); - -/* partition table */ -/* partition table for spinand flash */ -#ifdef CONFIG_SPI_NAND -static const struct mtd_partition spinand_partitions[] = { - { - .name = "logo", - .offset = 0, - .size = 2 * SZ_1M, - }, - { - .name = "recovery", - .offset = 0, - .size = 16 * SZ_1M, - }, - { - .name = "boot", - .offset = 0, - .size = 16 * SZ_1M, - }, - { - .name = "system", - .offset = 0, - .size = 64 * SZ_1M, - }, - /* last partition get the rest capacity */ - { - .name = "data", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - } -}; -struct mtd_partition *get_partition_table(int *partitions) -{ - *partitions = ARRAY_SIZE(spinand_partitions); - return spinand_partitions; -} -#endif /* CONFIG_SPI_NAND */ - -int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;} - -int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;} - -void __attribute__((weak)) set_working_fdt_addr(ulong addr) {} - -int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;} - -void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c2_2rs4_p2/firmware/timing.c b/board/amlogic/c2_2rs4_p2/firmware/timing.c deleted file mode 100755 index ec2f8ee..0000000 --- a/board/amlogic/c2_2rs4_p2/firmware/timing.c +++ /dev/null
@@ -1,1095 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2024 Amlogic, Inc. All rights reserved. - */ - -#include <asm/arch/secure_apb.h> -#include <asm/arch/timing.h> -#include <asm/arch/ddr_define.h> - -/* board clk defines */ -#define CPU_CLK 1512 -#define TIMMING_MAX_CONFIG 1 -#define ENABLE_DDR3 0 -#define ENABLE_LPDDR4 1 - -ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = { -#if ENABLE_DDR3 -{ - .cfg_board_common_setting.timming_magic = 0, - .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, - .cfg_board_common_setting.timming_struct_version = 0, - .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), - .cfg_board_common_setting.timming_struct_real_size = 0, //0 - .cfg_board_common_setting.fast_boot = {0}, - .cfg_board_common_setting.ddr_func = 0, - .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, - .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR3, - .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0, - .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, - .cfg_board_common_setting.dram_cs0_base_add = 0, - .cfg_board_common_setting.dram_cs1_base_add = 0, - .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB, - .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, - .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, - .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE, - .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, - .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, - .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, - .cfg_board_common_setting.org_tdqs2dq = 0, - .cfg_board_common_setting.reserve1_test_function = {0}, - .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT, - .cfg_board_common_setting.ac_pinmux = - { - 0, 0, 0, 1, 2, 3, 0, 1, - 2, 3, 4, 5, 6, 7, 8, 9, - 10, 11, 12, 13, 14, 15, 0, 0, - 0, 0, 20, 21, 22, 0, 0, 25, - 26, 27, 0 - }, - .cfg_board_common_setting.ddr_dqs_swap = 0, - .cfg_board_common_setting.ddr_dq_remap = { - 0, 1, 2, 3, 4, 5, 6, 7, - 8, 9, 10, 11, 12, 13, 14, 15, - 16, 17, 18, 19, 20, 21, 22, 23, - 24, 25, 26, 27, 28, 29, 30, 31, - 32, 33, 34, 35, - }, //d0-d31 dm0 dm1 dm2 dm3 - .cfg_board_common_setting.ddr_vddee_setting = {0}, - .cfg_board_SI_setting_ps[0].DRAMFreq = 912, - .cfg_board_SI_setting_ps[0].PllBypassEn = 0, - .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM, - .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[0].reserve2 = 0, - .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, - .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, - .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, - .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, - .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { - 128, 128, 128 - 20, 128, 128, 128, 128, 128, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, - }, //total 36 - - .cfg_ddr_training_delay_ps[0].ac_trace_delay = { - 128, 128, 128 - 20, 128, 128, 128, 128, 128, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, - }, //total 36 - .cfg_ddr_training_delay_ps[0].write_dqs_delay = { - 128 - 1, 128 - 1, 128 + 48, 128 + 58, 128 + 32, 128 + 32, 128 + 32, 128 + 32 - }, - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay = { - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, - 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, - 128 + 128, 128 + 128, 128 + 128, 128 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - }, - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay = { - 896, 896, 896, 896, 896, 896, 896, 896 - }, //total 8 - .cfg_ddr_training_delay_ps[0].read_dqs_delay = { - 64, 64, 50, 40, 64, 64, 64, 64 - }, //total 8 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay = { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 - }, //total 72 - .cfg_ddr_training_delay_ps[0].soc_bit_vref = { - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32 + 5, 32, 32 + 5, - 32, 32 + 5, 32, 32 + 5 - }, - .cfg_ddr_training_delay_ps[0].dram_bit_vref = { - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32 - }, //total 36 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[0] = 0x0000007d,// 125 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[1] = 0x00000091,// 145 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[2] = 0x00000091,// 145 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[3] = 0x0000009b,// 155 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[4] = 0x000000a0,// 160 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[5] = 0x000000a0,// 160 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[6] = 0x000000a0,// 160 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[7] = 0x000000a0,// 160 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0] = 0x000000c2,// 194 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1] = 0x000000b0,// 176 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2] = 0x000000af,// 175 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3] = 0x000000b0,// 176 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4] = 0x000000c0,// 192 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5] = 0x000000c3,// 195 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6] = 0x000000b4,// 180 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7] = 0x000000be,// 190 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8] = 0x000000ba,// 186 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9] = 0x000000c1,// 193 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10] = 0x000000d5,// 213 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11] = 0x000000c1,// 193 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12] = 0x000000d0,// 208 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13] = 0x000000cc,// 204 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14] = 0x000000c3,// 195 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15] = 0x000000be,// 190 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16] = 0x000000c0,// 192 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17] = 0x000000c8,// 200 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18] = 0x000000e0,// 224 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19] = 0x000000e5,// 229 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20] = 0x000000e2,// 226 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21] = 0x000000ec,// 236 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22] = 0x000000ec,// 236 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23] = 0x000000e7,// 231 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24] = 0x000000e4,// 228 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25] = 0x000000e9,// 233 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26] = 0x000000e6,// 230 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27] = 0x000000eb,// 235 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28] = 0x000000f5,// 245 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29] = 0x000000e7,// 231 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30] = 0x000000fd,// 253 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31] = 0x000000e8,// 232 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32] = 0x000000e4,// 228 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33] = 0x000000ee,// 238 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34] = 0x000000ec,// 236 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35] = 0x000000f2,// 242 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0] = 0x0000038c,// 908 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1] = 0x0000037a,// 890 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2] = 0x0000039a,// 922 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3] = 0x00000395,// 917 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[0] = 0x0000007f-0x30,// 127 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[1] = 0x0000007d-0x30,// 125 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[2] = 0x0000006d-0x30,// 109 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[3] = 0x0000006f-0x30,// 111 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[4] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[5] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[6] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[7] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0] = 0x00000048-0x30,// 72 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1] = 0x00000044-0x30,// 68 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2] = 0x00000038-0x30,// 56 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3] = 0x0000003b-0x30,// 59 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4] = 0x00000049-0x30,// 73 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5] = 0x0000004b-0x30,// 75 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6] = 0x0000003b-0x30,// 59 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7] = 0x00000049-0x30,// 73 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9] = 0x00000040-0x30,// 64 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10] = 0x00000052-0x30,// 82 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11] = 0x00000039-0x30,// 57 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12] = 0x00000040-0x30,// 64 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13] = 0x00000045-0x30,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14] = 0x00000042-0x30,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15] = 0x00000034-0x30,// 52 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16] = 0x0000003c-0x30,// 60 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17] = 0x00000086-0x30,// 134 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18] = 0x0000003f-0x30,// 63 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19] = 0x00000048-0x30,// 72 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20] = 0x00000037-0x30,// 55 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21] = 0x00000048-0x30,// 72 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22] = (0x0000004e)-0x30,// 78 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23] = 0x00000044-0x30,// 68 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24] = 0x00000042-0x30,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25] = 0x00000047-0x30,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26] = 0x0000007f-0x30,// 127 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27] = 0x00000040-0x30,// 64 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28] = 0x00000052-0x30,// 82 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29] = 0x0000003d-0x30,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30] = (0x0000004e)-0x30,// 78 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31] = 0x0000003c-0x30,// 60 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32] = (0x0000003e)-0x30,// 62 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33] = 0x0000003f-0x30,// 63 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34] = 0x0000004c-0x30,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35] = 0x00000091-0x30,// 145 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71] = 0x00000000,// 0 - - .cfg_ddr_training_delay_ps[0].reserve_training_parameter = {0}, - .cfg_board_SI_setting_ps[1].DRAMFreq = 667, - .cfg_board_SI_setting_ps[1].PllBypassEn = 0, - .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, - .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, - .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[1].reserve2 = 0, - .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, - .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, - .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, - .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, - .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, - }, //total 36 - .cfg_ddr_training_delay_ps[1].ac_trace_delay = { - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, - }, //total 36 - .cfg_ddr_training_delay_ps[1].write_dqs_delay = { - 0, 0, 0, 0, 0, 0, 0, 0 - }, - .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50 - }, - .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { - 192, 192, 192, 192, 192, 192, 192, 192 - }, //total 8 - .cfg_ddr_training_delay_ps[1].read_dqs_delay = { - 64, 64, 64, 64, 64, 64, 64, 64 - }, //total 8 - .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 - }, //total 72 - .cfg_ddr_training_delay_ps[1].soc_bit_vref = { - 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40 - }, //total 44 - .cfg_ddr_training_delay_ps[1].dram_bit_vref = { - 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32 - }, //total 36 - .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0}, -}, -#endif - -#if ENABLE_LPDDR4 //LPDDR4 rank0,timing_config -{ - .cfg_board_common_setting.timming_magic = 0, - .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, - .cfg_board_common_setting.timming_struct_version = 0, - .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), - .cfg_board_common_setting.timming_struct_real_size = 0, //0 - .cfg_board_common_setting.fast_boot = { 0 }, - .cfg_board_common_setting.ddr_func = 0, - .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, - .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_LPDDR4, - .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH01, - .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, - .cfg_board_common_setting.dram_cs0_base_add = 0, - .cfg_board_common_setting.dram_cs1_base_add = 0, - .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB, - .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, - .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, - .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_1T_MODE, - .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, - .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, //DDR_WRITE_READ_DBI_DISABLE , - .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, - .cfg_board_common_setting.org_tdqs2dq = 0, - .cfg_board_common_setting.reserve1_test_function = { 0 }, - .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT, -#ifdef CONFIG_DDR_WINDOWING_BOOT - .cfg_board_common_setting.fast_boot[0] = 0x1, - .cfg_board_common_setting.fast_boot[3] = 0x46, -#endif - //lpddr4 ac pinmux - .cfg_board_common_setting.ac_pinmux = { - 0, 0, 0, 1, 0, 1, 1, 3, - 0, 4, 4, 2, 0, 0, 1, 0, - 2, 0, 0, 0, 0, 3, 0, 0, - 0, 0, 5, 5, 0, 0, 0, 0, - 0, 0, - }, - .cfg_board_common_setting.ddr_dqs_swap = 0, - - .cfg_board_common_setting.ddr_dq_remap = { - 1, 0, 3, 2, 7, 5, 6, 4, - 9, 15, 13, 14, 10, 11, 12, 8, - 21, 19, 20, 18, 17, 16, 22, 23, - 25, 26, 24, 27, 31, 29, 30, 28, - 32, 33, 34, 35 - }, //d0-d31 dm0 dm1 dm2 dm3 - - .cfg_board_common_setting.ddr_vddee_setting = { 0 }, - .cfg_board_SI_setting_ps[0].DRAMFreq = 1320, - .cfg_board_SI_setting_ps[0].PllBypassEn = 0, - .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_60_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_LPDDR4_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_LPDDR4_ODT_60_OHM, - .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_LPDDR4_AC_ODT_80_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[0].reserve2 = 0, - .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, //3000/11, - .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, //170, - .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, //280, //330 - .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 }, - .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { - 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 0 + 128, //0,0,0,0,0,0,0,0, - 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128, 128 + 20 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - }, //total 36 - - .cfg_ddr_training_delay_ps[0].ac_trace_delay = { - 64 + 128, 64 + 128, 64 + 128-64, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 128 + 128, //0,0,0,0,0,0,0,0, - 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128-40, 128 + 20 + 128-10, 128 + 0 + 128, 128 + 0 + 128+10, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - }, //total 36 - .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 }, - - .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x000000af,// 175 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x000000cd,// 205 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x000000aa,// 170 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x000000cd,// 205 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x000000af,// 175 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x000000cd,// 205 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x000000aa,// 170 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x000000cd,// 205 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x000001cd,// 461 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x000001cc,// 460 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x000001ba,// 442 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000001d8,// 472 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000001e1,// 481 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000001ce,// 462 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000001c6,// 454 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000001d0,// 464 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000001cc,// 460 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000001d9,// 473 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000001da,// 474 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000001c4,// 452 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000001d5,// 469 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000001ea,// 490 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000001e9,// 489 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000001e2,// 482 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000001ea,// 490 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000001d5,// 469 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000001c6,// 454 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000001ce,// 462 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000001b5,// 437 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000001c7,// 455 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000001d3,// 467 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000001d1,// 465 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000001c4,// 452 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000001eb,// 491 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000001d1,// 465 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000001f7,// 503 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000001d8,// 472 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000001cf,// 463 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000001d3,// 467 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000001c9,// 457 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000001de,// 478 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x000001cd,// 461 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x000001cc,// 460 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x000001ba,// 442 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x000001d8,// 472 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x000001e1,// 481 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x000001ce,// 462 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x000001c6,// 454 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x000001d0,// 464 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x000001cc,// 460 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x000001d9,// 473 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x000001da,// 474 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x000001c4,// 452 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x000001d5,// 469 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x000001ea,// 490 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x000001e9,// 489 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x000001e2,// 482 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x000001ea,// 490 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x000001d5,// 469 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x000001c6,// 454 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x000001ce,// 462 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x000001b5,// 437 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x000001c7,// 455 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x000001d3,// 467 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x000001d1,// 465 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x000001c4,// 452 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x000001eb,// 491 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x000001d1,// 465 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x000001f7,// 503 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x000001d8,// 472 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x000001cf,// 463 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x000001d3,// 467 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x000001c9,// 457 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x000001de,// 478 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x000003ab,// 939 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000383,// 899 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000395,// 917 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x00000378,// 888 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x000003ab,// 939 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000383,// 899 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000395,// 917 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000378,// 888 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x0000007e,// 126 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x00000088,// 136 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000070,// 112 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007a,// 122 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x0000007e,// 126 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000088,// 136 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000070,// 112 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x0000007a,// 122 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000044,// 68 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000051,// 81 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x00000036,// 54 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000054,// 84 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x0000003d,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000045,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000051,// 81 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000037,// 55 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x0000003d,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000052,// 82 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x0000005b,// 91 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x0000004c,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000005a,// 90 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x0000004b,// 75 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000042,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x0000004f,// 79 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000030,// 48 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000042,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000004c,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000041,// 65 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000058,// 88 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000045,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000041,// 65 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000056,// 86 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003f,// 63 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000055,// 85 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x0000003e,// 62 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000034,// 52 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x00000031,// 49 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000036,// 54 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000040,// 64 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000044,// 68 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000051,// 81 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000036,// 54 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000054,// 84 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x0000003d,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000045,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000051,// 81 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000037,// 55 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x0000003d,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000052,// 82 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x0000005b,// 91 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x0000004c,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x0000005a,// 90 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x0000004b,// 75 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000042,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x0000004f,// 79 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000030,// 48 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000042,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x0000004c,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000041,// 65 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000058,// 88 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000045,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000041,// 65 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000056,// 86 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x0000003f,// 63 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000055,// 85 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x0000003e,// 62 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000034,// 52 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000031,// 49 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000036,// 54 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000040,// 64 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[0]=0,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[1]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[2]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[3]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[4]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[5]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[6]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[7]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[8]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[9]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[10]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[11]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[12]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[13]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[14]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[15]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[16]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[17]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[18]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[19]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[20]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[21]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[22]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[23]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[24]=0x00000016,// 22 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[25]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[26]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[27]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[28]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[29]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[30]=0x00000016,// 22 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[31]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[32]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[33]=0x00000016,// 22 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[34]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[35]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[36]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[37]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[38]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[39]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[40]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[41]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[42]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[43]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[0]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[1]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[2]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[3]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[4]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[5]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[6]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[7]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[8]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[9]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[10]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[11]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[12]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[13]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[14]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[15]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[16]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[17]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[18]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[19]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[20]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[21]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[22]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[23]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[24]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[25]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[26]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[27]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[28]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[29]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[30]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[31]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[32]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[33]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[34]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[35]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { - (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, - (1 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, - (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, - (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, - }, - .cfg_board_SI_setting_ps[1].DRAMFreq = 667, - .cfg_board_SI_setting_ps[1].PllBypassEn = 0, - .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, - .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, - .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[1].reserve2 = 0, - .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, - .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, - .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, - .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 }, - .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, - }, //total 36 - .cfg_ddr_training_delay_ps[1].ac_trace_delay = { - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, - }, //total 36 - - .cfg_ddr_training_delay_ps[1].write_dqs_delay = { - 0, 0, 0, 0, 0, 0, 0, 0 - }, - .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - }, - .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { - 192, 192, 192, 192, 192, 192, 192, 192 - }, //total 8 - .cfg_ddr_training_delay_ps[1].read_dqs_delay = { - 64, 64, 64, 64, 64, 64, 64, 64 - }, //total 8 - .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 - }, //total 72 - .cfg_ddr_training_delay_ps[1].soc_bit_vref = { - 0, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40 - }, //total 44 - .cfg_ddr_training_delay_ps[1].dram_bit_vref = { - 0, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32 - }, //total 36 - .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 }, -}, -#endif -}; -//ddr timing end - -pll_set_t __pll_setting = { - .cpu_clk = CPU_CLK / 24 * 24, -#ifdef CONFIG_PXP_EMULATOR - .pxp = 1, -#else - .pxp = 0, -#endif - .spi_ctrl = 0, - .lCustomerID = AML_CUSTOMER_ID, - .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */ - .log_ctrl = (1 << 7) | /* (1<<7), print bl2 log into buffer */ -#ifdef CONFIG_SILENT_CONSOLE - (1<<6), /* do not print log buffer */ -#else - (0<<6), /* print log buffer before run bl31 */ -#endif - .ddr_timming_save_mode = 1, -}; - -ddr_reg_t __ddr_reg[] = { - /* demo, user defined override register */ - {0xaabbccdd, 0, 0, 0, 0, 0}, - {0x11223344, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0}, -}; - - - -#define VCCK_VAL AML_VCCK_INIT_VOLTAGE -#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE -/* VCCK PWM table */ -#if (VCCK_VAL == 1039) - #define VCCK_VAL_REG 0x00000022 -#elif (VCCK_VAL == 1029) - #define VCCK_VAL_REG 0x00010021 -#elif (VCCK_VAL == 1019) - #define VCCK_VAL_REG 0x00020020 -#elif (VCCK_VAL == 1009) - #define VCCK_VAL_REG 0x0003001f -#elif (VCCK_VAL == 999) - #define VCCK_VAL_REG 0x0004001e -#elif (VCCK_VAL == 989) - #define VCCK_VAL_REG 0x0005001d -#elif (VCCK_VAL == 979) - #define VCCK_VAL_REG 0x0006001c -#elif (VCCK_VAL == 969) - #define VCCK_VAL_REG 0x0007001b -#elif (VCCK_VAL == 959) - #define VCCK_VAL_REG 0x0008001a -#elif (VCCK_VAL == 949) - #define VCCK_VAL_REG 0x00090019 -#elif (VCCK_VAL == 939) - #define VCCK_VAL_REG 0x000a0018 -#elif (VCCK_VAL == 929) - #define VCCK_VAL_REG 0x000b0017 -#elif (VCCK_VAL == 919) - #define VCCK_VAL_REG 0x000c0016 -#elif (VCCK_VAL == 909) - #define VCCK_VAL_REG 0x000d0015 -#elif (VCCK_VAL == 899) - #define VCCK_VAL_REG 0x000e0014 -#elif (VCCK_VAL == 889) - #define VCCK_VAL_REG 0x000f0013 -#elif (VCCK_VAL == 879) - #define VCCK_VAL_REG 0x00100012 -#elif (VCCK_VAL == 869) - #define VCCK_VAL_REG 0x00110011 -#elif (VCCK_VAL == 859) - #define VCCK_VAL_REG 0x00120010 -#elif (VCCK_VAL == 849) - #define VCCK_VAL_REG 0x0013000f -#elif (VCCK_VAL == 839) - #define VCCK_VAL_REG 0x0014000e -#elif (VCCK_VAL == 829) - #define VCCK_VAL_REG 0x0015000d -#elif (VCCK_VAL == 819) - #define VCCK_VAL_REG 0x0016000c -#elif (VCCK_VAL == 809) - #define VCCK_VAL_REG 0x0017000b -#elif (VCCK_VAL == 799) - #define VCCK_VAL_REG 0x0018000a -#elif (VCCK_VAL == 789) - #define VCCK_VAL_REG 0x00190009 -#elif (VCCK_VAL == 779) - #define VCCK_VAL_REG 0x001a0008 -#elif (VCCK_VAL == 769) - #define VCCK_VAL_REG 0x001b0007 -#elif (VCCK_VAL == 759) - #define VCCK_VAL_REG 0x001c0006 -#elif (VCCK_VAL == 749) - #define VCCK_VAL_REG 0x001d0005 -#elif (VCCK_VAL == 739) - #define VCCK_VAL_REG 0x001e0004 -#elif (VCCK_VAL == 729) - #define VCCK_VAL_REG 0x001f0003 -#elif (VCCK_VAL == 719) - #define VCCK_VAL_REG 0x00200002 -#elif (VCCK_VAL == 709) - #define VCCK_VAL_REG 0x00210001 -#elif (VCCK_VAL == 699) - #define VCCK_VAL_REG 0x00220000 -#else - #error "VCCK val out of range\n" -#endif - -/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/ -#ifdef CONFIG_I2C_REGULATOR -#if (VDDEE_VAL == 711) - #define VDDEE_VAL_REG 0xb -#elif (VDDEE_VAL == 721) - #define VDDEE_VAL_REG 0xc -#elif (VDDEE_VAL == 731) - #define VDDEE_VAL_REG 0xd -#elif (VDDEE_VAL == 741) - #define VDDEE_VAL_REG 0xe -#elif (VDDEE_VAL == 751) - #define VDDEE_VAL_REG 0xf -#elif (VDDEE_VAL == 761) - #define VDDEE_VAL_REG 0x10 -#elif (VDDEE_VAL == 771) - #define VDDEE_VAL_REG 0x11 -#elif (VDDEE_VAL == 781) - #define VDDEE_VAL_REG 0x12 -#elif (VDDEE_VAL == 791) - #define VDDEE_VAL_REG 0x13 -#elif (VDDEE_VAL == 801) - #define VDDEE_VAL_REG 0x14 -#elif (VDDEE_VAL == 811) - #define VDDEE_VAL_REG 0x15 -#elif (VDDEE_VAL == 821) - #define VDDEE_VAL_REG 0x16 -#elif (VDDEE_VAL == 831) - #define VDDEE_VAL_REG 0x17 -#elif (VDDEE_VAL == 841) - #define VDDEE_VAL_REG 0x18 -#elif (VDDEE_VAL == 851) - #define VDDEE_VAL_REG 0x19 -#elif (VDDEE_VAL == 861) - #define VDDEE_VAL_REG 0x1a -#elif (VDDEE_VAL == 871) - #define VDDEE_VAL_REG 0x1b -#elif (VDDEE_VAL == 881) - #define VDDEE_VAL_REG 0x1c -#elif (VDDEE_VAL == 891) - #define VDDEE_VAL_REG 0x1d -#else - #error "VDDEE val out of range\n" -#endif - -#else - -#if (VDDEE_VAL == 711) - #define VDDEE_VAL_REG 0x120000 -#elif (VDDEE_VAL == 721) - #define VDDEE_VAL_REG 0x110001 -#elif (VDDEE_VAL == 731) - #define VDDEE_VAL_REG 0x100002 -#elif (VDDEE_VAL == 741) - #define VDDEE_VAL_REG 0xf0003 -#elif (VDDEE_VAL == 751) - #define VDDEE_VAL_REG 0xe0004 -#elif (VDDEE_VAL == 761) - #define VDDEE_VAL_REG 0xd0005 -#elif (VDDEE_VAL == 771) - #define VDDEE_VAL_REG 0xc0006 -#elif (VDDEE_VAL == 781) - #define VDDEE_VAL_REG 0xb0007 -#elif (VDDEE_VAL == 791) - #define VDDEE_VAL_REG 0xa0008 -#elif (VDDEE_VAL == 801) - #define VDDEE_VAL_REG 0x90009 -#elif (VDDEE_VAL == 811) - #define VDDEE_VAL_REG 0x8000a -#elif (VDDEE_VAL == 821) - #define VDDEE_VAL_REG 0x7000b -#elif (VDDEE_VAL == 831) - #define VDDEE_VAL_REG 0x6000c -#elif (VDDEE_VAL == 841) - #define VDDEE_VAL_REG 0x5000d -#elif (VDDEE_VAL == 851) - #define VDDEE_VAL_REG 0x4000e -#elif (VDDEE_VAL == 861) - #define VDDEE_VAL_REG 0x3000f -#elif (VDDEE_VAL == 871) - #define VDDEE_VAL_REG 0x20010 -#elif (VDDEE_VAL == 881) - #define VDDEE_VAL_REG 0x10011 -#elif (VDDEE_VAL == 891) - #define VDDEE_VAL_REG 0x12 -#else - #error "VDDEE val out of range\n" -#endif -#endif - -/* for PWM use */ -/* - * GPIOE_0 PWM_A VDDEE_PWM - * - * GPIOE_1 PWM_B VCCK_PWM - */ -/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */ -#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400) -#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400) - -/* pwm clock and pwm controller */ -#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800) -#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400) -#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400) -#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400) - -bl2_reg_t __bl2_reg[] = { -#ifdef CONFIG_I2C_REGULATOR - /* demo, user defined override register */ - {0, 0, 0xffffffff, 0, 0, 0}, - {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, - {PWMAB_MISC_REG_AB, 0x1 << 1, 0x1 << 1, 0, BL2_INIT_STAGE_1, 0}, - /* Set GPIOA_5 low */ - {PADCTRL_GPIOA_O, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_GPIOA_OEN, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, - /* Set GPIOD_10 low */ - {PADCTRL_GPIOD_O, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, - /* Set GPIOX_11 low */ - {PADCTRL_GPIOX_O, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_GPIOX_OEN, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, - /* set pwm A and pwm B clock rate to 24M, enable them */ - {CLKTREE_PWM_CLK_AB_CTRL, 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, - /* set GPIOE_0 GPIOE_1 drive strength to 3*/ - {PADCTRL_GPIOE_DS, 0x3 << 2, 0x3 << 2, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, -#ifdef CONFIG_PDVFS_ENABLE - /* table_id, ee_voltage, ...... */ - {1, 0x11, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, - {2, 0x14, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, - {3, 0x16, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, -#else - {0x0, VDDEE_VAL_REG, 0x0, 0, BL2_INIT_STAGE_I2C_REGULATOR, 0}, -#endif -#else - /* demo, user defined override register */ - {0, 0, 0xffffffff, 0, 0, 0}, -#ifdef CONFIG_PDVFS_ENABLE - {PWMAB_PWM_A, 0x000c0006, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, - {PWMAB_PWM_A, 0x00090009, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, - {PWMAB_PWM_A, 0x0007000b, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, -#else - {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, -#endif - {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, - {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0}, - /* Set GPIOA_5(SOC_LEDRING_EN) low */ - {PADCTRL_GPIOA_O, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_GPIOA_OEN, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, - /* Set GPIOD_10(BAT_HEALTH_CHECK_EN) low */ - {PADCTRL_GPIOD_O, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, - /* Set GPIOX_11(BAT_VSENSE_EN) low */ - {PADCTRL_GPIOX_O, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_GPIOX_OEN, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, - /* set pwm A and pwm B clock rate to 24M, enable them */ - {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, - /* set GPIOE_0 GPIOE_1 drive strength to 3*/ - {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, -#endif -};
diff --git a/board/amlogic/c2_bla4_bx/Kconfig b/board/amlogic/c2_bla4_bx/Kconfig deleted file mode 100644 index f75643f..0000000 --- a/board/amlogic/c2_bla4_bx/Kconfig +++ /dev/null
@@ -1,37 +0,0 @@ -if TARGET_C2_BLA4_BX - -config SYS_SOC - default "c2" - -config SYS_BOARD - default "c2_bla4_bx" - -config SYS_VENDOR - default "amlogic" - -config SYS_CONFIG_NAME - default "c2_bla4_bx" - -config DTB_BIND_KERNEL - bool "load dtb from boot part but not flash rsv" - default n - -config CMD_PLLTEST - bool "support plltest command" - default y - help - support plltest command - -config I2C_REGULATOR - bool "use i2c regulator to configure vddee" - default n - -config DDR_WINDOWING_BOOT - bool "enable/disable ddr windowing boot" - default n - -config LED_AW2026 - bool "enable/disable AW2026 LED" - default y - -endif
diff --git a/board/amlogic/c2_bla4_bx/Makefile b/board/amlogic/c2_bla4_bx/Makefile deleted file mode 100644 index 0403c0c..0000000 --- a/board/amlogic/c2_bla4_bx/Makefile +++ /dev/null
@@ -1 +0,0 @@ -obj-y += $(BOARD).o
diff --git a/board/amlogic/c2_bla4_bx/aml-user-key.sig b/board/amlogic/c2_bla4_bx/aml-user-key.sig deleted file mode 100644 index 0f89a75..0000000 --- a/board/amlogic/c2_bla4_bx/aml-user-key.sig +++ /dev/null Binary files differ
diff --git a/board/amlogic/c2_bla4_bx/c2_bla4_bx.c b/board/amlogic/c2_bla4_bx/c2_bla4_bx.c deleted file mode 100644 index bb85c68..0000000 --- a/board/amlogic/c2_bla4_bx/c2_bla4_bx.c +++ /dev/null
@@ -1,319 +0,0 @@ - -/* - * Copyright (C) 2015 Amlogic, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -*/ - -#include <common.h> -#include <asm/io.h> -#include <malloc.h> -#include <errno.h> -#include <environment.h> -#include <fdt_support.h> -#include <linux/libfdt.h> -#include <amlogic/cpu_id.h> -#include <asm/arch/secure_apb.h> -#include <asm/arch/pinctrl_init.h> -#include <linux/sizes.h> -#include <asm-generic/gpio.h> -#include <dm.h> -#include <asm/armv8/mmu.h> -#include <amlogic/aml_v3_burning.h> -#include <amlogic/aml_v2_burning.h> -#include <amlogic/leds-aw2026.h> -#include <linux/mtd/partitions.h> -#include <linux/ssr/ps13216.h> - -DECLARE_GLOBAL_DATA_PTR; - -int serial_set_pin_port(unsigned long port_base) -{ - return 0; -} - -int dram_init(void) -{ - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -unsigned int get_dram_size(void) -{ - // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 -#if defined(CONFIG_SYS_MEM_TOP_HIDE) - return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; -#else - return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); -#endif /* CONFIG_SYS_MEM_TOP_HIDE */ -} - - -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = get_dram_size(); - return 0; -} - -/* secondary_boot_func - * this function should be write with asm, here, is is only for compiling pass - * */ -void secondary_boot_func(void) -{ -} - -int board_eth_init(bd_t *bis) -{ - return 0; -} - -int active_clk(void) -{ - struct udevice *clk = NULL; - int err; - - err = uclass_get_device_by_name(UCLASS_CLK, - "xtal-clk", &clk); - if (err) { - pr_err("Can't find xtal-clk clock (%d)\n", err); - return err; - } - err = uclass_get_device_by_name(UCLASS_CLK, - "clock-controller@0", &clk); - if (err) { - pr_err("Can't find clock-controller@0 clock (%d)\n", err); - return err; - } - - return 0; -} - -void board_init_mem(void) { - /* config bootm low size, make sure whole dram/psram space can be used */ - phys_size_t ram_size; - char *env_tmp; - env_tmp = env_get("bootm_size"); - if (!env_tmp) { - ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); - env_set_hex("bootm_low", 0); - env_set_hex("bootm_size", ram_size); - } -} - -int board_init(void) -{ - unsigned int value; - - printf("board init\n"); - - /* set GPIOB_3 to low before emmc init */ - value = readl(PADCTRL_PIN_MUX_REG3); - /* set to gpio pin */ - writel(value & ~(0xf << 12), PADCTRL_PIN_MUX_REG3); - value = readl(PADCTRL_GPIOB_OEN); - /* enable gpio output */ - writel(value & ~(0x1 << 3), PADCTRL_GPIOB_OEN); - value = readl(PADCTRL_GPIOB_O); - /* set output value to low */ - writel(value & ~(0x1 << 3), PADCTRL_GPIOB_O); - udelay(20000); - - //Please keep try usb boot first in board_init, as other init before usb may cause burning failure -#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) - if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2))) - { aml_v3_factory_usb_burning(0, gd->bd); } -#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) - - pinctrl_devices_active(PIN_CONTROLLER_NUM); - active_clk(); - - // set to white by default - sys_led_init(WHITE); - return 0; -} - -int board_late_init(void) -{ - board_init_mem(); - -#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard - aml_try_factory_sdcard_burning(0, gd->bd); -#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE - //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003' -#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) - if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2)) - { aml_v3_factory_usb_burning(0, gd->bd); } -#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) - - return 0; -} - - -phys_size_t get_effective_memsize(void) -{ -#ifdef UBOOT_RUN_IN_SRAM - return 0x180000; /* SRAM 1.5MB */ -#else - // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 -#if defined(CONFIG_SYS_MEM_TOP_HIDE) - return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; -#else - return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); -#endif /* CONFIG_SYS_MEM_TOP_HIDE */ -#endif /* UBOOT_RUN_IN_SRAM */ -} - -static struct mm_region bd_mem_map[] = { - { - .virt = 0x00000000UL, - .phys = 0x00000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = bd_mem_map; - -int mach_cpu_init(void) { - printf("\nmach_cpu_init\n"); - return 0; -} - -int ft_board_setup(void *blob, bd_t *bd) -{ - /* eg: bl31/32 rsv */ - return 0; -} - -int do_get_hw_id(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) -{ - unsigned int hw_bid = 0, hw_cid = 0, ret = 0; - char hw_id_str[8] = {0}; // eg: 0x0A - - /* - * HW_BID_2 : GPIOD_8 - * HW_BID_1 : GPIOD_5 - * HW_BID_0 : GPIOD_4 - * HW_CID_2 : GPIOX_10 - * HW_CID_1 : GPIOX_9 - * HW_CID_0 : GPIOX_8 - * - */ - /* disable gpio pull */ - ret = readl(PADCTRL_GPIOD_PULL_EN); - writel(ret & (~(0x13 << 4)), PADCTRL_GPIOD_PULL_EN); - ret = readl(PADCTRL_GPIOX_PULL_EN); - writel(ret & (~(0x7 << 8)), PADCTRL_GPIOX_PULL_EN); - - /* pin mux to gpio pin */ - /* GPIOD_4, GPIOD_5 */ - ret = readl(PADCTRL_PIN_MUX_REG0); - writel(ret & (~(0xFF << 16)), PADCTRL_PIN_MUX_REG0); - /* GPIOD_8 */ - ret = readl(PADCTRL_PIN_MUX_REG1); - writel(ret & (~(0xF << 0)), PADCTRL_PIN_MUX_REG1); - /* GPIOX_8, GPIOX_9, GPIOX_10 */ - ret = readl(PADCTRL_PIN_MUX_REG7); - writel(ret & (~(0xFFF << 0)), PADCTRL_PIN_MUX_REG7); - - /* enable input */ - ret = readl(PADCTRL_GPIOD_OEN); - writel(ret | (0x13 << 4), PADCTRL_GPIOD_OEN); - ret = readl(PADCTRL_GPIOX_OEN); - writel(ret | (0x7 << 8), PADCTRL_GPIOX_OEN); - - /* read hw id */ - ret = readl(PADCTRL_GPIOD_I); - hw_bid = (ret >> 4) & 0x3; - hw_bid |= (ret >> 6) & 0x4; - ret = readl(PADCTRL_GPIOX_I); - hw_cid = (ret >> 8) & 0x7; - - if (BLA4_HW_CID != hw_cid) { - pr_err("The image doesn't match the device(CID=0x%x)\n", hw_cid); - sys_led_init(YELLOW); - while(1); - } - - ret = (hw_cid << 0x3) | hw_bid; - snprintf(hw_id_str, sizeof(hw_id_str), "0x%02x", ret); - env_set("hw_id", hw_id_str); - return 0; -} - -U_BOOT_CMD( - get_hw_id, 1, 0, do_get_hw_id, "get HW_ID and env_set 'hw_id'\n", "get_hw_id" -); - -/* partition table */ -/* partition table for spinand flash */ -#ifdef CONFIG_SPI_NAND -static const struct mtd_partition spinand_partitions[] = { - { - .name = "logo", - .offset = 0, - .size = 2 * SZ_1M, - }, - { - .name = "recovery", - .offset = 0, - .size = 16 * SZ_1M, - }, - { - .name = "boot", - .offset = 0, - .size = 16 * SZ_1M, - }, - { - .name = "system", - .offset = 0, - .size = 64 * SZ_1M, - }, - /* last partition get the rest capacity */ - { - .name = "data", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - } -}; -struct mtd_partition *get_partition_table(int *partitions) -{ - *partitions = ARRAY_SIZE(spinand_partitions); - return spinand_partitions; -} -#endif /* CONFIG_SPI_NAND */ - -int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;} - -int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;} - -void __attribute__((weak)) set_working_fdt_addr(ulong addr) {} - -int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;} - -void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c2_bla4_bx/firmware/timing.c b/board/amlogic/c2_bla4_bx/firmware/timing.c deleted file mode 100755 index b703ec3..0000000 --- a/board/amlogic/c2_bla4_bx/firmware/timing.c +++ /dev/null
@@ -1,1457 +0,0 @@ -/* - * board/amlogic/c2_bla4_bx/firmware/timing.c - * - * Copyright (C) 2015 Amlogic, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -*/ - -#include <asm/arch/secure_apb.h> -#include <asm/arch/timing.h> -#include <asm/arch/ddr_define.h> - -/* board clk defines */ -#define CPU_CLK 1512 -#define TIMMING_MAX_CONFIG 1 -#define ENABLE_DDR3 0 -#define ENABLE_DDR4 1 -#define ENABLE_LPDDR4 0 - -ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = { -#if ENABLE_DDR4 -{ - .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, - .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4, - .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, - .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096 - .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, - .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, - .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, - .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, - .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT, - .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)}, - .cfg_board_common_setting. fast_boot[0] = 0x1, - .cfg_board_common_setting. fast_boot[3] = 0x46, - - //DDR frequercy 1 - .cfg_board_SI_setting_ps[0].DRAMFreq = 1272,//1320,1200,1104,1008,912,792 - .cfg_board_SI_setting_ps[0].PllBypassEn = 0, - .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_48_OHM, - .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, - .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[0].reserve2 = 0, - .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, - .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, - .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, - .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, - .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { - 128,128,128-20,128,128,128,128,128, - 384,384,384,384,384,384,384,384, - 384,384,384,384,384,384,384,384, - 384,384,384,384,384,384,384,384, - 384,384,384,384, - },//total 36 - - .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { - 128,128,128-20,128,128,128,128,128, - 384,384,384,384,384,384,384,384, - 384,384,384,384,384,384,384,384, - 384,384,384,384,384,384,384,384, - 384,384,384,384, - },//total 36 - - .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x0000005f,// 95 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000073,// 115 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x0000005f,// 95 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000087,// 135 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000080,// 128 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000080,// 128 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000080,// 128 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000080,// 128 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000009f,// 159 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000095,// 149 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000092,// 146 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x0000009f,// 159 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000bb,// 187 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000cd,// 205 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000b1,// 177 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000c5,// 197 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000ad,// 173 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000000a1,// 161 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000d3,// 211 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000000a2,// 162 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000d1,// 209 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000000d3,// 211 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000d0,// 208 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000000a7,// 167 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000a9,// 169 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000000b9,// 185 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000000ae,// 174 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000b1,// 177 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000b2,// 178 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000bd,// 189 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000000d1,// 209 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000d0,// 208 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000c6,// 198 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000d1,// 209 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000bf,// 191 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000000c1,// 193 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000d3,// 211 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000000c1,// 193 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000dc,// 220 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000000ae,// 174 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000a1,// 161 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000ab,// 171 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000ac,// 172 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000bd,// 189 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000037a,// 890 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000359,// 857 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000352,// 850 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x0000034f,// 847 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000075,// 117 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x0000006c,// 108 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000058,// 88 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007c,// 124 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000034,// 52 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000033,// 51 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000002b,// 43 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000032,// 50 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000050,// 80 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000062,// 98 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000043,// 67 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000058,// 88 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000028,// 40 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000028,// 40 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000036,// 54 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000044,// 68 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x00000042,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000026,// 38 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000002c,// 44 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x0000002a,// 42 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x00000032,// 50 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000029,// 41 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x0000002c,// 44 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000048,// 72 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000003e,// 62 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x0000003b,// 59 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x0000003b,// 59 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000050,// 80 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003d,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x00000030,// 48 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x0000002e,// 46 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000002f,// 47 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000033,// 51 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0 - - .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { - 0,40,40,40,40,40,40,40,40,40,40, - 40,40,40,40,40,40,40,40,40,40,40, - 40,40,40,40,40,40,40,40,40,40,40, - 40,40,40,40,50,40,50,40,50,40,50},//total 44 - .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { - 0,32,32,32,32,32,32,32,32,32,32, - 32,32,32,32,32,32,32,32,32,32,32, - 32,32,32,32,32,32,32,32,32,32,32, - 32,32,32},//total 36 - .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { - (0 << 7) | 6, (0 << 7) | 6, (1 << 7) | 5, (0 << 7) | 0, - (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, - (1 << 7) | 10, (1 << 7) | 10, (1 << 7) | 10, (1 << 7) | 10, - (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, - }, - - //pinmux setting - .cfg_board_common_setting. ac_pinmux = { - 0, 0, 0, 1, 2, 3, - 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, - }, - .cfg_board_common_setting. ddr_dqs_swap = 0, - - .cfg_board_common_setting. ddr_dq_remap = { - 0,1,2,3,4,5,6,7, - 8,9,10,11,12,13,14,15, - 16,17,18,19,20,21,22,23, - 24,25,26,27,28,29,30,31, - 32,33,34,35 - },//d0-d31 dm0 dm1 dm2 dm3 - - .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start - .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), - .cfg_board_common_setting. timming_struct_version = 0, - .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), - .cfg_board_common_setting. timming_struct_real_size = 0, //0 - .cfg_board_common_setting. ddr_func = 0, - .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, - .cfg_board_common_setting. dram_cs0_base_add = 0, - .cfg_board_common_setting. dram_cs1_base_add = 0, - - .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE, - .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, - .cfg_board_common_setting. org_tdqs2dq = 0, - .cfg_board_common_setting. reserve1_test_function = {0}, - .cfg_board_common_setting. ddr_vddee_setting = {0}, - - //DDR frequercy 2 - .cfg_board_SI_setting_ps[1].DRAMFreq = 600, - .cfg_board_SI_setting_ps[1].PllBypassEn = 0, - .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, - .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, - .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[1].reserve2 = 0, - .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, - .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, - .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, - .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, - .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { - 128,128,128,128,128,128,128,128, - 128,128,128,128,128,128,128,128, - 128,128,128,128,128,128,128,128, - 128,128,128,128,128,128,128,128, - 128,128,128,128, - },//total 36 - - .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { - 128,128,128,128,128,128,128,128, - 128,128,128,128,128,128,128,128, - 128,128,128,128,128,128,128,128, - 128,128,128,128,128,128,128,128, - 128,128,128,128, - },//total 36 - .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, - //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, - .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50,}, - - //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 - .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 - //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 - .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 - .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0},//total 72 - .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { - 40,40,40,40,40,40,40,40,40,40,40, - 40,40,40,40,40,40,40,40,40,40,40, - 40,40,40,40,40,40,40,40,40,40,40, - 40,40,40,40,40,40,40,40,40,40,40},//total 44 - .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { - 32,32,32,32,32,32,32,32,32,32,32, - 32,32,32,32,32,32,32,32,32,32,32, - 32,32,32,32,32,32,32,32,32,32,32, - 32,32,32},//total 36 - - .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end -}, -#endif //end ENABLE_DDR4 -#if ENABLE_DDR3 -{ - .cfg_board_common_setting.timming_magic = 0, - .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, - .cfg_board_common_setting.timming_struct_version = 0, - .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), - .cfg_board_common_setting.timming_struct_real_size = 0, //0 - .cfg_board_common_setting.fast_boot = {0}, - .cfg_board_common_setting.ddr_func = 0, - .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, - .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR3, - .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0, - .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, - .cfg_board_common_setting.dram_cs0_base_add = 0, - .cfg_board_common_setting.dram_cs1_base_add = 0, - .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB, - .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, - .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, - .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE, - .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, - .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, - .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, - .cfg_board_common_setting.org_tdqs2dq = 0, - .cfg_board_common_setting.reserve1_test_function = {0}, - .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT, - .cfg_board_common_setting.ac_pinmux = - { - 0, 0, 0, 1, 2, 3, 0, 1, - 2, 3, 4, 5, 6, 7, 8, 9, - 10, 11, 12, 13, 14, 15, 0, 0, - 0, 0, 20, 21, 22, 0, 0, 25, - 26, 27, 0 - }, - .cfg_board_common_setting.ddr_dqs_swap = 0, - .cfg_board_common_setting.ddr_dq_remap = { - 0, 1, 2, 3, 4, 5, 6, 7, - 8, 9, 10, 11, 12, 13, 14, 15, - 16, 17, 18, 19, 20, 21, 22, 23, - 24, 25, 26, 27, 28, 29, 30, 31, - 32, 33, 34, 35, - }, //d0-d31 dm0 dm1 dm2 dm3 - .cfg_board_common_setting.ddr_vddee_setting = {0}, - .cfg_board_SI_setting_ps[0].DRAMFreq = 912, - .cfg_board_SI_setting_ps[0].PllBypassEn = 0, - .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM, - .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[0].reserve2 = 0, - .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, - .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, - .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, - .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, - .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { - 128, 128, 128 - 20, 128, 128, 128, 128, 128, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, - }, //total 36 - - .cfg_ddr_training_delay_ps[0].ac_trace_delay = { - 128, 128, 128 - 20, 128, 128, 128, 128, 128, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, - }, //total 36 - .cfg_ddr_training_delay_ps[0].write_dqs_delay = { - 128 - 1, 128 - 1, 128 + 48, 128 + 58, 128 + 32, 128 + 32, 128 + 32, 128 + 32 - }, - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay = { - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, - 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, - 128 + 128, 128 + 128, 128 + 128, 128 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - }, - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay = { - 896, 896, 896, 896, 896, 896, 896, 896 - }, //total 8 - .cfg_ddr_training_delay_ps[0].read_dqs_delay = { - 64, 64, 50, 40, 64, 64, 64, 64 - }, //total 8 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay = { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 - }, //total 72 - .cfg_ddr_training_delay_ps[0].soc_bit_vref = { - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32 + 5, 32, 32 + 5, - 32, 32 + 5, 32, 32 + 5 - }, - .cfg_ddr_training_delay_ps[0].dram_bit_vref = { - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32 - }, //total 36 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[0] = 0x0000007d,// 125 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[1] = 0x00000091,// 145 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[2] = 0x00000091,// 145 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[3] = 0x0000009b,// 155 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[4] = 0x000000a0,// 160 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[5] = 0x000000a0,// 160 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[6] = 0x000000a0,// 160 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[7] = 0x000000a0,// 160 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0] = 0x000000c2,// 194 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1] = 0x000000b0,// 176 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2] = 0x000000af,// 175 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3] = 0x000000b0,// 176 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4] = 0x000000c0,// 192 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5] = 0x000000c3,// 195 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6] = 0x000000b4,// 180 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7] = 0x000000be,// 190 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8] = 0x000000ba,// 186 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9] = 0x000000c1,// 193 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10] = 0x000000d5,// 213 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11] = 0x000000c1,// 193 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12] = 0x000000d0,// 208 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13] = 0x000000cc,// 204 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14] = 0x000000c3,// 195 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15] = 0x000000be,// 190 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16] = 0x000000c0,// 192 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17] = 0x000000c8,// 200 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18] = 0x000000e0,// 224 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19] = 0x000000e5,// 229 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20] = 0x000000e2,// 226 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21] = 0x000000ec,// 236 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22] = 0x000000ec,// 236 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23] = 0x000000e7,// 231 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24] = 0x000000e4,// 228 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25] = 0x000000e9,// 233 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26] = 0x000000e6,// 230 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27] = 0x000000eb,// 235 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28] = 0x000000f5,// 245 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29] = 0x000000e7,// 231 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30] = 0x000000fd,// 253 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31] = 0x000000e8,// 232 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32] = 0x000000e4,// 228 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33] = 0x000000ee,// 238 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34] = 0x000000ec,// 236 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35] = 0x000000f2,// 242 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0] = 0x0000038c,// 908 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1] = 0x0000037a,// 890 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2] = 0x0000039a,// 922 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3] = 0x00000395,// 917 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[0] = 0x0000007f-0x30,// 127 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[1] = 0x0000007d-0x30,// 125 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[2] = 0x0000006d-0x30,// 109 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[3] = 0x0000006f-0x30,// 111 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[4] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[5] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[6] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[7] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0] = 0x00000048-0x30,// 72 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1] = 0x00000044-0x30,// 68 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2] = 0x00000038-0x30,// 56 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3] = 0x0000003b-0x30,// 59 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4] = 0x00000049-0x30,// 73 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5] = 0x0000004b-0x30,// 75 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6] = 0x0000003b-0x30,// 59 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7] = 0x00000049-0x30,// 73 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9] = 0x00000040-0x30,// 64 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10] = 0x00000052-0x30,// 82 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11] = 0x00000039-0x30,// 57 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12] = 0x00000040-0x30,// 64 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13] = 0x00000045-0x30,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14] = 0x00000042-0x30,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15] = 0x00000034-0x30,// 52 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16] = 0x0000003c-0x30,// 60 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17] = 0x00000086-0x30,// 134 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18] = 0x0000003f-0x30,// 63 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19] = 0x00000048-0x30,// 72 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20] = 0x00000037-0x30,// 55 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21] = 0x00000048-0x30,// 72 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22] = (0x0000004e)-0x30,// 78 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23] = 0x00000044-0x30,// 68 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24] = 0x00000042-0x30,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25] = 0x00000047-0x30,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26] = 0x0000007f-0x30,// 127 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27] = 0x00000040-0x30,// 64 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28] = 0x00000052-0x30,// 82 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29] = 0x0000003d-0x30,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30] = (0x0000004e)-0x30,// 78 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31] = 0x0000003c-0x30,// 60 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32] = (0x0000003e)-0x30,// 62 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33] = 0x0000003f-0x30,// 63 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34] = 0x0000004c-0x30,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35] = 0x00000091-0x30,// 145 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71] = 0x00000000,// 0 - - .cfg_ddr_training_delay_ps[0].reserve_training_parameter = {0}, - .cfg_board_SI_setting_ps[1].DRAMFreq = 667, - .cfg_board_SI_setting_ps[1].PllBypassEn = 0, - .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, - .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, - .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[1].reserve2 = 0, - .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, - .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, - .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, - .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, - .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, - }, //total 36 - .cfg_ddr_training_delay_ps[1].ac_trace_delay = { - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, - }, //total 36 - .cfg_ddr_training_delay_ps[1].write_dqs_delay = { - 0, 0, 0, 0, 0, 0, 0, 0 - }, - .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50 - }, - .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { - 192, 192, 192, 192, 192, 192, 192, 192 - }, //total 8 - .cfg_ddr_training_delay_ps[1].read_dqs_delay = { - 64, 64, 64, 64, 64, 64, 64, 64 - }, //total 8 - .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 - }, //total 72 - .cfg_ddr_training_delay_ps[1].soc_bit_vref = { - 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40 - }, //total 44 - .cfg_ddr_training_delay_ps[1].dram_bit_vref = { - 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32 - }, //total 36 - .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0}, -}, -#endif - -#if ENABLE_LPDDR4 //LPDDR4 rank0,timing_config -{ - .cfg_board_common_setting.timming_magic = 0, - .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, - .cfg_board_common_setting.timming_struct_version = 0, - .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), - .cfg_board_common_setting.timming_struct_real_size = 0, //0 - .cfg_board_common_setting.fast_boot = { 0 }, - .cfg_board_common_setting.ddr_func = 0, - .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, - .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_LPDDR4, - .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH01, - .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, - .cfg_board_common_setting.dram_cs0_base_add = 0, - .cfg_board_common_setting.dram_cs1_base_add = 0, - .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB, - .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, - .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, - .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_1T_MODE, - .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, - .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, //DDR_WRITE_READ_DBI_DISABLE , - .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, - .cfg_board_common_setting.org_tdqs2dq = 0, - .cfg_board_common_setting.reserve1_test_function = { 0 }, - .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT, -#ifdef CONFIG_DDR_WINDOWING_BOOT - .cfg_board_common_setting.fast_boot[0] = 0x1, - .cfg_board_common_setting.fast_boot[3] = 0x46, -#endif - //lpddr4 ac pinmux - .cfg_board_common_setting.ac_pinmux = { - 0, 0, 0, 1, 0, 1, 1, 3, - 0, 4, 4, 2, 0, 0, 1, 0, - 2, 0, 0, 0, 0, 3, 0, 0, - 0, 0, 5, 5, 0, 0, 0, 0, - 0, 0, - }, - .cfg_board_common_setting.ddr_dqs_swap = 0, - - .cfg_board_common_setting.ddr_dq_remap = { - 1, 0, 3, 2, 7, 5, 6, 4, - 9, 15, 13, 14, 10, 11, 12, 8, - 21, 19, 20, 18, 17, 16, 22, 23, - 25, 26, 24, 27, 31, 29, 30, 28, - 32, 33, 34, 35 - }, //d0-d31 dm0 dm1 dm2 dm3 - - .cfg_board_common_setting.ddr_vddee_setting = { 0 }, - .cfg_board_SI_setting_ps[0].DRAMFreq = 1320, - .cfg_board_SI_setting_ps[0].PllBypassEn = 0, - .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_60_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_LPDDR4_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_LPDDR4_ODT_60_OHM, - .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_LPDDR4_AC_ODT_80_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[0].reserve2 = 0, - .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, //3000/11, - .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, //170, - .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, //280, //330 - .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 }, - .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { - 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 0 + 128, //0,0,0,0,0,0,0,0, - 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128, 128 + 20 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - }, //total 36 - - .cfg_ddr_training_delay_ps[0].ac_trace_delay = { - 64 + 128, 64 + 128, 64 + 128-64, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 128 + 128, //0,0,0,0,0,0,0,0, - 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128-40, 128 + 20 + 128-10, 128 + 0 + 128, 128 + 0 + 128+10, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - }, //total 36 - .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 }, - - .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x000000af,// 175 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x000000cd,// 205 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x000000aa,// 170 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x000000cd,// 205 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x000000af,// 175 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x000000cd,// 205 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x000000aa,// 170 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x000000cd,// 205 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x000001cd,// 461 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x000001cc,// 460 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x000001ba,// 442 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000001d8,// 472 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000001e1,// 481 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000001ce,// 462 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000001c6,// 454 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000001d0,// 464 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000001cc,// 460 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000001d9,// 473 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000001da,// 474 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000001c4,// 452 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000001d5,// 469 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000001ea,// 490 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000001e9,// 489 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000001e2,// 482 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000001ea,// 490 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000001d5,// 469 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000001c6,// 454 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000001ce,// 462 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000001b5,// 437 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000001c7,// 455 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000001d3,// 467 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000001d1,// 465 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000001c4,// 452 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000001eb,// 491 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000001d1,// 465 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000001f7,// 503 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000001d8,// 472 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000001cf,// 463 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000001d3,// 467 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000001c9,// 457 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000001de,// 478 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x000001cd,// 461 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x000001cc,// 460 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x000001ba,// 442 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x000001d8,// 472 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x000001e1,// 481 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x000001ce,// 462 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x000001c6,// 454 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x000001d0,// 464 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x000001cc,// 460 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x000001d9,// 473 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x000001da,// 474 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x000001c4,// 452 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x000001d5,// 469 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x000001ea,// 490 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x000001e9,// 489 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x000001e2,// 482 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x000001ea,// 490 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x000001d5,// 469 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x000001c6,// 454 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x000001ce,// 462 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x000001b5,// 437 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x000001c7,// 455 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x000001d3,// 467 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x000001d1,// 465 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x000001c4,// 452 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x000001eb,// 491 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x000001d1,// 465 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x000001f7,// 503 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x000001d8,// 472 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x000001cf,// 463 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x000001d3,// 467 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x000001c9,// 457 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x000001de,// 478 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x000003ab,// 939 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000383,// 899 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000395,// 917 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x00000378,// 888 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x000003ab,// 939 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000383,// 899 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000395,// 917 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000378,// 888 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x0000007e,// 126 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x00000088,// 136 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000070,// 112 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007a,// 122 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x0000007e,// 126 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000088,// 136 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000070,// 112 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x0000007a,// 122 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000044,// 68 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000051,// 81 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x00000036,// 54 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000054,// 84 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x0000003d,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000045,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000051,// 81 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000037,// 55 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x0000003d,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000052,// 82 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x0000005b,// 91 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x0000004c,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000005a,// 90 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x0000004b,// 75 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000042,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x0000004f,// 79 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000030,// 48 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000042,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000004c,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000041,// 65 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000058,// 88 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000045,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000041,// 65 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000056,// 86 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003f,// 63 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000055,// 85 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x0000003e,// 62 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000034,// 52 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x00000031,// 49 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000036,// 54 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000040,// 64 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000044,// 68 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000051,// 81 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000036,// 54 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000054,// 84 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x0000003d,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000045,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000051,// 81 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000037,// 55 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x0000003d,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000052,// 82 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x0000005b,// 91 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x0000004c,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x0000005a,// 90 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x0000004b,// 75 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000042,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x0000004f,// 79 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000030,// 48 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000042,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x0000004c,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000041,// 65 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000058,// 88 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000045,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000041,// 65 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000056,// 86 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x0000003f,// 63 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000055,// 85 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x0000003e,// 62 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000034,// 52 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000031,// 49 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000036,// 54 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000040,// 64 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[0]=0,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[1]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[2]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[3]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[4]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[5]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[6]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[7]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[8]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[9]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[10]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[11]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[12]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[13]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[14]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[15]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[16]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[17]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[18]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[19]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[20]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[21]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[22]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[23]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[24]=0x00000016,// 22 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[25]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[26]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[27]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[28]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[29]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[30]=0x00000016,// 22 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[31]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[32]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[33]=0x00000016,// 22 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[34]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[35]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[36]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[37]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[38]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[39]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[40]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[41]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[42]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[43]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[0]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[1]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[2]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[3]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[4]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[5]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[6]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[7]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[8]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[9]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[10]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[11]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[12]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[13]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[14]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[15]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[16]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[17]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[18]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[19]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[20]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[21]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[22]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[23]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[24]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[25]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[26]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[27]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[28]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[29]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[30]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[31]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[32]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[33]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[34]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[35]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { - (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, - (1 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, - (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, - (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, - }, - .cfg_board_SI_setting_ps[1].DRAMFreq = 667, - .cfg_board_SI_setting_ps[1].PllBypassEn = 0, - .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, - .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, - .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[1].reserve2 = 0, - .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, - .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, - .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, - .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 }, - .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, - }, //total 36 - .cfg_ddr_training_delay_ps[1].ac_trace_delay = { - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, - }, //total 36 - - .cfg_ddr_training_delay_ps[1].write_dqs_delay = { - 0, 0, 0, 0, 0, 0, 0, 0 - }, - .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - }, - .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { - 192, 192, 192, 192, 192, 192, 192, 192 - }, //total 8 - .cfg_ddr_training_delay_ps[1].read_dqs_delay = { - 64, 64, 64, 64, 64, 64, 64, 64 - }, //total 8 - .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 - }, //total 72 - .cfg_ddr_training_delay_ps[1].soc_bit_vref = { - 0, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40 - }, //total 44 - .cfg_ddr_training_delay_ps[1].dram_bit_vref = { - 0, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32 - }, //total 36 - .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 }, -}, -#endif -}; -//ddr timing end - -pll_set_t __pll_setting = { - .cpu_clk = CPU_CLK / 24 * 24, -#ifdef CONFIG_PXP_EMULATOR - .pxp = 1, -#else - .pxp = 0, -#endif - .spi_ctrl = 0, - .lCustomerID = AML_CUSTOMER_ID, - .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */ - .log_ctrl = (1 << 7) | /* (1<<7), print bl2 log into buffer */ -#ifdef CONFIG_SILENT_CONSOLE - (1<<6), /* do not print log buffer */ -#else - (0<<6), /* print log buffer before run bl31 */ -#endif - .ddr_timming_save_mode = 1, -}; - -ddr_reg_t __ddr_reg[] = { - /* demo, user defined override register */ - {0xaabbccdd, 0, 0, 0, 0, 0}, - {0x11223344, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0}, -}; - - - -#define VCCK_VAL AML_VCCK_INIT_VOLTAGE -#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE -/* VCCK PWM table */ -#if (VCCK_VAL == 1039) - #define VCCK_VAL_REG 0x00000022 -#elif (VCCK_VAL == 1029) - #define VCCK_VAL_REG 0x00010021 -#elif (VCCK_VAL == 1019) - #define VCCK_VAL_REG 0x00020020 -#elif (VCCK_VAL == 1009) - #define VCCK_VAL_REG 0x0003001f -#elif (VCCK_VAL == 999) - #define VCCK_VAL_REG 0x0004001e -#elif (VCCK_VAL == 989) - #define VCCK_VAL_REG 0x0005001d -#elif (VCCK_VAL == 979) - #define VCCK_VAL_REG 0x0006001c -#elif (VCCK_VAL == 969) - #define VCCK_VAL_REG 0x0007001b -#elif (VCCK_VAL == 959) - #define VCCK_VAL_REG 0x0008001a -#elif (VCCK_VAL == 949) - #define VCCK_VAL_REG 0x00090019 -#elif (VCCK_VAL == 939) - #define VCCK_VAL_REG 0x000a0018 -#elif (VCCK_VAL == 929) - #define VCCK_VAL_REG 0x000b0017 -#elif (VCCK_VAL == 919) - #define VCCK_VAL_REG 0x000c0016 -#elif (VCCK_VAL == 909) - #define VCCK_VAL_REG 0x000d0015 -#elif (VCCK_VAL == 899) - #define VCCK_VAL_REG 0x000e0014 -#elif (VCCK_VAL == 889) - #define VCCK_VAL_REG 0x000f0013 -#elif (VCCK_VAL == 879) - #define VCCK_VAL_REG 0x00100012 -#elif (VCCK_VAL == 869) - #define VCCK_VAL_REG 0x00110011 -#elif (VCCK_VAL == 859) - #define VCCK_VAL_REG 0x00120010 -#elif (VCCK_VAL == 849) - #define VCCK_VAL_REG 0x0013000f -#elif (VCCK_VAL == 839) - #define VCCK_VAL_REG 0x0014000e -#elif (VCCK_VAL == 829) - #define VCCK_VAL_REG 0x0015000d -#elif (VCCK_VAL == 819) - #define VCCK_VAL_REG 0x0016000c -#elif (VCCK_VAL == 809) - #define VCCK_VAL_REG 0x0017000b -#elif (VCCK_VAL == 799) - #define VCCK_VAL_REG 0x0018000a -#elif (VCCK_VAL == 789) - #define VCCK_VAL_REG 0x00190009 -#elif (VCCK_VAL == 779) - #define VCCK_VAL_REG 0x001a0008 -#elif (VCCK_VAL == 769) - #define VCCK_VAL_REG 0x001b0007 -#elif (VCCK_VAL == 759) - #define VCCK_VAL_REG 0x001c0006 -#elif (VCCK_VAL == 749) - #define VCCK_VAL_REG 0x001d0005 -#elif (VCCK_VAL == 739) - #define VCCK_VAL_REG 0x001e0004 -#elif (VCCK_VAL == 729) - #define VCCK_VAL_REG 0x001f0003 -#elif (VCCK_VAL == 719) - #define VCCK_VAL_REG 0x00200002 -#elif (VCCK_VAL == 709) - #define VCCK_VAL_REG 0x00210001 -#elif (VCCK_VAL == 699) - #define VCCK_VAL_REG 0x00220000 -#else - #error "VCCK val out of range\n" -#endif - -/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/ -#ifdef CONFIG_I2C_REGULATOR -#if (VDDEE_VAL == 711) - #define VDDEE_VAL_REG 0xb -#elif (VDDEE_VAL == 721) - #define VDDEE_VAL_REG 0xc -#elif (VDDEE_VAL == 731) - #define VDDEE_VAL_REG 0xd -#elif (VDDEE_VAL == 741) - #define VDDEE_VAL_REG 0xe -#elif (VDDEE_VAL == 751) - #define VDDEE_VAL_REG 0xf -#elif (VDDEE_VAL == 761) - #define VDDEE_VAL_REG 0x10 -#elif (VDDEE_VAL == 771) - #define VDDEE_VAL_REG 0x11 -#elif (VDDEE_VAL == 781) - #define VDDEE_VAL_REG 0x12 -#elif (VDDEE_VAL == 791) - #define VDDEE_VAL_REG 0x13 -#elif (VDDEE_VAL == 801) - #define VDDEE_VAL_REG 0x14 -#elif (VDDEE_VAL == 811) - #define VDDEE_VAL_REG 0x15 -#elif (VDDEE_VAL == 821) - #define VDDEE_VAL_REG 0x16 -#elif (VDDEE_VAL == 831) - #define VDDEE_VAL_REG 0x17 -#elif (VDDEE_VAL == 841) - #define VDDEE_VAL_REG 0x18 -#elif (VDDEE_VAL == 851) - #define VDDEE_VAL_REG 0x19 -#elif (VDDEE_VAL == 861) - #define VDDEE_VAL_REG 0x1a -#elif (VDDEE_VAL == 871) - #define VDDEE_VAL_REG 0x1b -#elif (VDDEE_VAL == 881) - #define VDDEE_VAL_REG 0x1c -#elif (VDDEE_VAL == 891) - #define VDDEE_VAL_REG 0x1d -#else - #error "VDDEE val out of range\n" -#endif - -#else - -#if (VDDEE_VAL == 711) - #define VDDEE_VAL_REG 0x120000 -#elif (VDDEE_VAL == 721) - #define VDDEE_VAL_REG 0x110001 -#elif (VDDEE_VAL == 731) - #define VDDEE_VAL_REG 0x100002 -#elif (VDDEE_VAL == 741) - #define VDDEE_VAL_REG 0xf0003 -#elif (VDDEE_VAL == 751) - #define VDDEE_VAL_REG 0xe0004 -#elif (VDDEE_VAL == 761) - #define VDDEE_VAL_REG 0xd0005 -#elif (VDDEE_VAL == 771) - #define VDDEE_VAL_REG 0xc0006 -#elif (VDDEE_VAL == 781) - #define VDDEE_VAL_REG 0xb0007 -#elif (VDDEE_VAL == 791) - #define VDDEE_VAL_REG 0xa0008 -#elif (VDDEE_VAL == 801) - #define VDDEE_VAL_REG 0x90009 -#elif (VDDEE_VAL == 811) - #define VDDEE_VAL_REG 0x8000a -#elif (VDDEE_VAL == 821) - #define VDDEE_VAL_REG 0x7000b -#elif (VDDEE_VAL == 831) - #define VDDEE_VAL_REG 0x6000c -#elif (VDDEE_VAL == 841) - #define VDDEE_VAL_REG 0x5000d -#elif (VDDEE_VAL == 851) - #define VDDEE_VAL_REG 0x4000e -#elif (VDDEE_VAL == 861) - #define VDDEE_VAL_REG 0x3000f -#elif (VDDEE_VAL == 871) - #define VDDEE_VAL_REG 0x20010 -#elif (VDDEE_VAL == 881) - #define VDDEE_VAL_REG 0x10011 -#elif (VDDEE_VAL == 891) - #define VDDEE_VAL_REG 0x12 -#else - #error "VDDEE val out of range\n" -#endif -#endif - -/* for PWM use */ -/* - * GPIOE_0 PWM_A VDDEE_PWM - * - * GPIOE_1 PWM_B VCCK_PWM - */ -/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */ -#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400) -#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400) - -/* pwm clock and pwm controller */ -#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800) -#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400) -#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400) -#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400) - -bl2_reg_t __bl2_reg[] = { -#ifdef CONFIG_I2C_REGULATOR - /* demo, user defined override register */ - {0, 0, 0xffffffff, 0, 0, 0}, - {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, - {PWMAB_MISC_REG_AB, 0x1 << 1, 0x1 << 1, 0, BL2_INIT_STAGE_1, 0}, - /* Set GPIOA_5 low */ - {PADCTRL_GPIOA_O, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_GPIOA_OEN, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, - /* Set GPIOD_10 low */ - {PADCTRL_GPIOD_O, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, - /* Set GPIOX_11 low */ - {PADCTRL_GPIOX_O, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_GPIOX_OEN, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, - /* set pwm A and pwm B clock rate to 24M, enable them */ - {CLKTREE_PWM_CLK_AB_CTRL, 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, - /* set GPIOE_0 GPIOE_1 drive strength to 3*/ - {PADCTRL_GPIOE_DS, 0x3 << 2, 0x3 << 2, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, -#ifdef CONFIG_PDVFS_ENABLE - /* table_id, ee_voltage, ...... */ - {1, 0x11, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, - {2, 0x14, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, - {3, 0x16, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, -#else - {0x0, VDDEE_VAL_REG, 0x0, 0, BL2_INIT_STAGE_I2C_REGULATOR, 0}, -#endif -#else - /* demo, user defined override register */ - {0, 0, 0xffffffff, 0, 0, 0}, -#ifdef CONFIG_PDVFS_ENABLE - {PWMAB_PWM_A, 0x000c0006, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, - {PWMAB_PWM_A, 0x00090009, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, - {PWMAB_PWM_A, 0x0007000b, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, -#else - {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, -#endif - {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, - {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0}, - /* enable vddcpu dc-dc, set GPIOD_10 high */ - {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, - /* set pwm A and pwm B clock rate to 24M, enable them */ - {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, - /* set GPIOE_0 GPIOE_1 drive strength to 3*/ - {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, -#endif -};
diff --git a/board/amlogic/c2_bla4_p0/Kconfig b/board/amlogic/c2_bla4_p0/Kconfig deleted file mode 100644 index a8f75cc..0000000 --- a/board/amlogic/c2_bla4_p0/Kconfig +++ /dev/null
@@ -1,37 +0,0 @@ -if TARGET_C2_BLA4_P0 - -config SYS_SOC - default "c2" - -config SYS_BOARD - default "c2_bla4_p0" - -config SYS_VENDOR - default "amlogic" - -config SYS_CONFIG_NAME - default "c2_bla4_p0" - -config DTB_BIND_KERNEL - bool "load dtb from boot part but not flash rsv" - default n - -config CMD_PLLTEST - bool "support plltest command" - default y - help - support plltest command - -config I2C_REGULATOR - bool "use i2c regulator to configure vddee" - default n - -config DDR_WINDOWING_BOOT - bool "enable/disable ddr windowing boot" - default n - -config LED_AW2026 - bool "enable/disable AW2026 LED" - default y - -endif
diff --git a/board/amlogic/c2_bla4_p0/Makefile b/board/amlogic/c2_bla4_p0/Makefile deleted file mode 100644 index 0403c0c..0000000 --- a/board/amlogic/c2_bla4_p0/Makefile +++ /dev/null
@@ -1 +0,0 @@ -obj-y += $(BOARD).o
diff --git a/board/amlogic/c2_bla4_p0/aml-user-key.sig b/board/amlogic/c2_bla4_p0/aml-user-key.sig deleted file mode 100644 index 0f89a75..0000000 --- a/board/amlogic/c2_bla4_p0/aml-user-key.sig +++ /dev/null Binary files differ
diff --git a/board/amlogic/c2_bla4_p0/c2_bla4_p0.c b/board/amlogic/c2_bla4_p0/c2_bla4_p0.c deleted file mode 100644 index bb85c68..0000000 --- a/board/amlogic/c2_bla4_p0/c2_bla4_p0.c +++ /dev/null
@@ -1,319 +0,0 @@ - -/* - * Copyright (C) 2015 Amlogic, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -*/ - -#include <common.h> -#include <asm/io.h> -#include <malloc.h> -#include <errno.h> -#include <environment.h> -#include <fdt_support.h> -#include <linux/libfdt.h> -#include <amlogic/cpu_id.h> -#include <asm/arch/secure_apb.h> -#include <asm/arch/pinctrl_init.h> -#include <linux/sizes.h> -#include <asm-generic/gpio.h> -#include <dm.h> -#include <asm/armv8/mmu.h> -#include <amlogic/aml_v3_burning.h> -#include <amlogic/aml_v2_burning.h> -#include <amlogic/leds-aw2026.h> -#include <linux/mtd/partitions.h> -#include <linux/ssr/ps13216.h> - -DECLARE_GLOBAL_DATA_PTR; - -int serial_set_pin_port(unsigned long port_base) -{ - return 0; -} - -int dram_init(void) -{ - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -unsigned int get_dram_size(void) -{ - // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 -#if defined(CONFIG_SYS_MEM_TOP_HIDE) - return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; -#else - return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); -#endif /* CONFIG_SYS_MEM_TOP_HIDE */ -} - - -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = get_dram_size(); - return 0; -} - -/* secondary_boot_func - * this function should be write with asm, here, is is only for compiling pass - * */ -void secondary_boot_func(void) -{ -} - -int board_eth_init(bd_t *bis) -{ - return 0; -} - -int active_clk(void) -{ - struct udevice *clk = NULL; - int err; - - err = uclass_get_device_by_name(UCLASS_CLK, - "xtal-clk", &clk); - if (err) { - pr_err("Can't find xtal-clk clock (%d)\n", err); - return err; - } - err = uclass_get_device_by_name(UCLASS_CLK, - "clock-controller@0", &clk); - if (err) { - pr_err("Can't find clock-controller@0 clock (%d)\n", err); - return err; - } - - return 0; -} - -void board_init_mem(void) { - /* config bootm low size, make sure whole dram/psram space can be used */ - phys_size_t ram_size; - char *env_tmp; - env_tmp = env_get("bootm_size"); - if (!env_tmp) { - ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); - env_set_hex("bootm_low", 0); - env_set_hex("bootm_size", ram_size); - } -} - -int board_init(void) -{ - unsigned int value; - - printf("board init\n"); - - /* set GPIOB_3 to low before emmc init */ - value = readl(PADCTRL_PIN_MUX_REG3); - /* set to gpio pin */ - writel(value & ~(0xf << 12), PADCTRL_PIN_MUX_REG3); - value = readl(PADCTRL_GPIOB_OEN); - /* enable gpio output */ - writel(value & ~(0x1 << 3), PADCTRL_GPIOB_OEN); - value = readl(PADCTRL_GPIOB_O); - /* set output value to low */ - writel(value & ~(0x1 << 3), PADCTRL_GPIOB_O); - udelay(20000); - - //Please keep try usb boot first in board_init, as other init before usb may cause burning failure -#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) - if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2))) - { aml_v3_factory_usb_burning(0, gd->bd); } -#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) - - pinctrl_devices_active(PIN_CONTROLLER_NUM); - active_clk(); - - // set to white by default - sys_led_init(WHITE); - return 0; -} - -int board_late_init(void) -{ - board_init_mem(); - -#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard - aml_try_factory_sdcard_burning(0, gd->bd); -#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE - //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003' -#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) - if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2)) - { aml_v3_factory_usb_burning(0, gd->bd); } -#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) - - return 0; -} - - -phys_size_t get_effective_memsize(void) -{ -#ifdef UBOOT_RUN_IN_SRAM - return 0x180000; /* SRAM 1.5MB */ -#else - // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 -#if defined(CONFIG_SYS_MEM_TOP_HIDE) - return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; -#else - return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); -#endif /* CONFIG_SYS_MEM_TOP_HIDE */ -#endif /* UBOOT_RUN_IN_SRAM */ -} - -static struct mm_region bd_mem_map[] = { - { - .virt = 0x00000000UL, - .phys = 0x00000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = bd_mem_map; - -int mach_cpu_init(void) { - printf("\nmach_cpu_init\n"); - return 0; -} - -int ft_board_setup(void *blob, bd_t *bd) -{ - /* eg: bl31/32 rsv */ - return 0; -} - -int do_get_hw_id(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) -{ - unsigned int hw_bid = 0, hw_cid = 0, ret = 0; - char hw_id_str[8] = {0}; // eg: 0x0A - - /* - * HW_BID_2 : GPIOD_8 - * HW_BID_1 : GPIOD_5 - * HW_BID_0 : GPIOD_4 - * HW_CID_2 : GPIOX_10 - * HW_CID_1 : GPIOX_9 - * HW_CID_0 : GPIOX_8 - * - */ - /* disable gpio pull */ - ret = readl(PADCTRL_GPIOD_PULL_EN); - writel(ret & (~(0x13 << 4)), PADCTRL_GPIOD_PULL_EN); - ret = readl(PADCTRL_GPIOX_PULL_EN); - writel(ret & (~(0x7 << 8)), PADCTRL_GPIOX_PULL_EN); - - /* pin mux to gpio pin */ - /* GPIOD_4, GPIOD_5 */ - ret = readl(PADCTRL_PIN_MUX_REG0); - writel(ret & (~(0xFF << 16)), PADCTRL_PIN_MUX_REG0); - /* GPIOD_8 */ - ret = readl(PADCTRL_PIN_MUX_REG1); - writel(ret & (~(0xF << 0)), PADCTRL_PIN_MUX_REG1); - /* GPIOX_8, GPIOX_9, GPIOX_10 */ - ret = readl(PADCTRL_PIN_MUX_REG7); - writel(ret & (~(0xFFF << 0)), PADCTRL_PIN_MUX_REG7); - - /* enable input */ - ret = readl(PADCTRL_GPIOD_OEN); - writel(ret | (0x13 << 4), PADCTRL_GPIOD_OEN); - ret = readl(PADCTRL_GPIOX_OEN); - writel(ret | (0x7 << 8), PADCTRL_GPIOX_OEN); - - /* read hw id */ - ret = readl(PADCTRL_GPIOD_I); - hw_bid = (ret >> 4) & 0x3; - hw_bid |= (ret >> 6) & 0x4; - ret = readl(PADCTRL_GPIOX_I); - hw_cid = (ret >> 8) & 0x7; - - if (BLA4_HW_CID != hw_cid) { - pr_err("The image doesn't match the device(CID=0x%x)\n", hw_cid); - sys_led_init(YELLOW); - while(1); - } - - ret = (hw_cid << 0x3) | hw_bid; - snprintf(hw_id_str, sizeof(hw_id_str), "0x%02x", ret); - env_set("hw_id", hw_id_str); - return 0; -} - -U_BOOT_CMD( - get_hw_id, 1, 0, do_get_hw_id, "get HW_ID and env_set 'hw_id'\n", "get_hw_id" -); - -/* partition table */ -/* partition table for spinand flash */ -#ifdef CONFIG_SPI_NAND -static const struct mtd_partition spinand_partitions[] = { - { - .name = "logo", - .offset = 0, - .size = 2 * SZ_1M, - }, - { - .name = "recovery", - .offset = 0, - .size = 16 * SZ_1M, - }, - { - .name = "boot", - .offset = 0, - .size = 16 * SZ_1M, - }, - { - .name = "system", - .offset = 0, - .size = 64 * SZ_1M, - }, - /* last partition get the rest capacity */ - { - .name = "data", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - } -}; -struct mtd_partition *get_partition_table(int *partitions) -{ - *partitions = ARRAY_SIZE(spinand_partitions); - return spinand_partitions; -} -#endif /* CONFIG_SPI_NAND */ - -int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;} - -int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;} - -void __attribute__((weak)) set_working_fdt_addr(ulong addr) {} - -int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;} - -void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c2_bla4_p0/firmware/timing.c b/board/amlogic/c2_bla4_p0/firmware/timing.c deleted file mode 100755 index a4e5e95..0000000 --- a/board/amlogic/c2_bla4_p0/firmware/timing.c +++ /dev/null
@@ -1,1457 +0,0 @@ -/* - * board/amlogic/c2_bla4_p0/firmware/timing.c - * - * Copyright (C) 2015 Amlogic, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -*/ - -#include <asm/arch/secure_apb.h> -#include <asm/arch/timing.h> -#include <asm/arch/ddr_define.h> - -/* board clk defines */ -#define CPU_CLK 1512 -#define TIMMING_MAX_CONFIG 1 -#define ENABLE_DDR3 0 -#define ENABLE_DDR4 1 -#define ENABLE_LPDDR4 0 - -ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = { -#if ENABLE_DDR4 -{ - .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, - .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4, - .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, - .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096 - .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, - .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, - .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, - .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, - .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT, - .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)}, - .cfg_board_common_setting. fast_boot[0] = 0x1, - .cfg_board_common_setting. fast_boot[3] = 0x46, - - //DDR frequercy 1 - .cfg_board_SI_setting_ps[0].DRAMFreq = 1272,//1320,1200,1104,1008,912,792 - .cfg_board_SI_setting_ps[0].PllBypassEn = 0, - .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_48_OHM, - .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, - .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[0].reserve2 = 0, - .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, - .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, - .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, - .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, - .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { - 128,128,128-20,128,128,128,128,128, - 384,384,384,384,384,384,384,384, - 384,384,384,384,384,384,384,384, - 384,384,384,384,384,384,384,384, - 384,384,384,384, - },//total 36 - - .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { - 128,128,128-20,128,128,128,128,128, - 384,384,384,384,384,384,384,384, - 384,384,384,384,384,384,384,384, - 384,384,384,384,384,384,384,384, - 384,384,384,384, - },//total 36 - - .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x0000005f,// 95 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000073,// 115 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x0000005f,// 95 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000087,// 135 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000080,// 128 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000080,// 128 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000080,// 128 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000080,// 128 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000009f,// 159 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000095,// 149 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000092,// 146 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x0000009f,// 159 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000bb,// 187 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000cd,// 205 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000b1,// 177 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000c5,// 197 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000ad,// 173 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000000a1,// 161 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000d3,// 211 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000000a2,// 162 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000d1,// 209 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000000d3,// 211 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000d0,// 208 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000000a7,// 167 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000a9,// 169 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000000b9,// 185 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000000ae,// 174 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000b1,// 177 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000b2,// 178 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000bd,// 189 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000000d1,// 209 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000d0,// 208 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000c6,// 198 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000d1,// 209 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000bf,// 191 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000000c1,// 193 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000d3,// 211 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000000c1,// 193 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000dc,// 220 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000000ae,// 174 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000a1,// 161 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000ab,// 171 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000ac,// 172 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000bd,// 189 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000037a,// 890 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000359,// 857 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000352,// 850 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x0000034f,// 847 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000075,// 117 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x0000006c,// 108 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000058,// 88 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007c,// 124 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000034,// 52 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000033,// 51 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000002b,// 43 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000032,// 50 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000050,// 80 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000062,// 98 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000043,// 67 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000058,// 88 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000028,// 40 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000028,// 40 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000036,// 54 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000044,// 68 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x00000042,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000026,// 38 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000002c,// 44 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x0000002a,// 42 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x00000032,// 50 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000029,// 41 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x0000002c,// 44 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000048,// 72 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000003e,// 62 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x0000003b,// 59 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x0000003b,// 59 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000050,// 80 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003d,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x00000030,// 48 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x0000002e,// 46 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000002f,// 47 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000033,// 51 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0 - - .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { - 0,40,40,40,40,40,40,40,40,40,40, - 40,40,40,40,40,40,40,40,40,40,40, - 40,40,40,40,40,40,40,40,40,40,40, - 40,40,40,40,50,40,50,40,50,40,50},//total 44 - .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { - 0,32,32,32,32,32,32,32,32,32,32, - 32,32,32,32,32,32,32,32,32,32,32, - 32,32,32,32,32,32,32,32,32,32,32, - 32,32,32},//total 36 - .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { - (0 << 7) | 6, (0 << 7) | 6, (1 << 7) | 5, (0 << 7) | 0, - (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, - (1 << 7) | 10, (1 << 7) | 10, (1 << 7) | 10, (1 << 7) | 10, - (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, - }, - - //pinmux setting - .cfg_board_common_setting. ac_pinmux = { - 0, 0, 0, 1, 2, 3, - 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, - }, - .cfg_board_common_setting. ddr_dqs_swap = 0, - - .cfg_board_common_setting. ddr_dq_remap = { - 0,1,2,3,4,5,6,7, - 8,9,10,11,12,13,14,15, - 16,17,18,19,20,21,22,23, - 24,25,26,27,28,29,30,31, - 32,33,34,35 - },//d0-d31 dm0 dm1 dm2 dm3 - - .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start - .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), - .cfg_board_common_setting. timming_struct_version = 0, - .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), - .cfg_board_common_setting. timming_struct_real_size = 0, //0 - .cfg_board_common_setting. ddr_func = 0, - .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, - .cfg_board_common_setting. dram_cs0_base_add = 0, - .cfg_board_common_setting. dram_cs1_base_add = 0, - - .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE, - .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, - .cfg_board_common_setting. org_tdqs2dq = 0, - .cfg_board_common_setting. reserve1_test_function = {0}, - .cfg_board_common_setting. ddr_vddee_setting = {0}, - - //DDR frequercy 2 - .cfg_board_SI_setting_ps[1].DRAMFreq = 600, - .cfg_board_SI_setting_ps[1].PllBypassEn = 0, - .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, - .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, - .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[1].reserve2 = 0, - .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, - .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, - .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, - .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, - .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { - 128,128,128,128,128,128,128,128, - 128,128,128,128,128,128,128,128, - 128,128,128,128,128,128,128,128, - 128,128,128,128,128,128,128,128, - 128,128,128,128, - },//total 36 - - .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { - 128,128,128,128,128,128,128,128, - 128,128,128,128,128,128,128,128, - 128,128,128,128,128,128,128,128, - 128,128,128,128,128,128,128,128, - 128,128,128,128, - },//total 36 - .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, - //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, - .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50,}, - - //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 - .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 - //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 - .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 - .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0},//total 72 - .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { - 40,40,40,40,40,40,40,40,40,40,40, - 40,40,40,40,40,40,40,40,40,40,40, - 40,40,40,40,40,40,40,40,40,40,40, - 40,40,40,40,40,40,40,40,40,40,40},//total 44 - .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { - 32,32,32,32,32,32,32,32,32,32,32, - 32,32,32,32,32,32,32,32,32,32,32, - 32,32,32,32,32,32,32,32,32,32,32, - 32,32,32},//total 36 - - .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end -}, -#endif //end ENABLE_DDR4 -#if ENABLE_DDR3 -{ - .cfg_board_common_setting.timming_magic = 0, - .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, - .cfg_board_common_setting.timming_struct_version = 0, - .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), - .cfg_board_common_setting.timming_struct_real_size = 0, //0 - .cfg_board_common_setting.fast_boot = {0}, - .cfg_board_common_setting.ddr_func = 0, - .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, - .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR3, - .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0, - .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, - .cfg_board_common_setting.dram_cs0_base_add = 0, - .cfg_board_common_setting.dram_cs1_base_add = 0, - .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB, - .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, - .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, - .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE, - .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, - .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, - .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, - .cfg_board_common_setting.org_tdqs2dq = 0, - .cfg_board_common_setting.reserve1_test_function = {0}, - .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT, - .cfg_board_common_setting.ac_pinmux = - { - 0, 0, 0, 1, 2, 3, 0, 1, - 2, 3, 4, 5, 6, 7, 8, 9, - 10, 11, 12, 13, 14, 15, 0, 0, - 0, 0, 20, 21, 22, 0, 0, 25, - 26, 27, 0 - }, - .cfg_board_common_setting.ddr_dqs_swap = 0, - .cfg_board_common_setting.ddr_dq_remap = { - 0, 1, 2, 3, 4, 5, 6, 7, - 8, 9, 10, 11, 12, 13, 14, 15, - 16, 17, 18, 19, 20, 21, 22, 23, - 24, 25, 26, 27, 28, 29, 30, 31, - 32, 33, 34, 35, - }, //d0-d31 dm0 dm1 dm2 dm3 - .cfg_board_common_setting.ddr_vddee_setting = {0}, - .cfg_board_SI_setting_ps[0].DRAMFreq = 912, - .cfg_board_SI_setting_ps[0].PllBypassEn = 0, - .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM, - .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[0].reserve2 = 0, - .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, - .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, - .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, - .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, - .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { - 128, 128, 128 - 20, 128, 128, 128, 128, 128, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, - }, //total 36 - - .cfg_ddr_training_delay_ps[0].ac_trace_delay = { - 128, 128, 128 - 20, 128, 128, 128, 128, 128, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, - }, //total 36 - .cfg_ddr_training_delay_ps[0].write_dqs_delay = { - 128 - 1, 128 - 1, 128 + 48, 128 + 58, 128 + 32, 128 + 32, 128 + 32, 128 + 32 - }, - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay = { - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, - 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, - 128 + 128, 128 + 128, 128 + 128, 128 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - }, - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay = { - 896, 896, 896, 896, 896, 896, 896, 896 - }, //total 8 - .cfg_ddr_training_delay_ps[0].read_dqs_delay = { - 64, 64, 50, 40, 64, 64, 64, 64 - }, //total 8 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay = { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 - }, //total 72 - .cfg_ddr_training_delay_ps[0].soc_bit_vref = { - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32 + 5, 32, 32 + 5, - 32, 32 + 5, 32, 32 + 5 - }, - .cfg_ddr_training_delay_ps[0].dram_bit_vref = { - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32 - }, //total 36 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[0] = 0x0000007d,// 125 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[1] = 0x00000091,// 145 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[2] = 0x00000091,// 145 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[3] = 0x0000009b,// 155 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[4] = 0x000000a0,// 160 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[5] = 0x000000a0,// 160 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[6] = 0x000000a0,// 160 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[7] = 0x000000a0,// 160 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0] = 0x000000c2,// 194 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1] = 0x000000b0,// 176 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2] = 0x000000af,// 175 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3] = 0x000000b0,// 176 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4] = 0x000000c0,// 192 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5] = 0x000000c3,// 195 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6] = 0x000000b4,// 180 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7] = 0x000000be,// 190 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8] = 0x000000ba,// 186 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9] = 0x000000c1,// 193 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10] = 0x000000d5,// 213 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11] = 0x000000c1,// 193 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12] = 0x000000d0,// 208 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13] = 0x000000cc,// 204 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14] = 0x000000c3,// 195 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15] = 0x000000be,// 190 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16] = 0x000000c0,// 192 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17] = 0x000000c8,// 200 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18] = 0x000000e0,// 224 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19] = 0x000000e5,// 229 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20] = 0x000000e2,// 226 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21] = 0x000000ec,// 236 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22] = 0x000000ec,// 236 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23] = 0x000000e7,// 231 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24] = 0x000000e4,// 228 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25] = 0x000000e9,// 233 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26] = 0x000000e6,// 230 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27] = 0x000000eb,// 235 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28] = 0x000000f5,// 245 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29] = 0x000000e7,// 231 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30] = 0x000000fd,// 253 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31] = 0x000000e8,// 232 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32] = 0x000000e4,// 228 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33] = 0x000000ee,// 238 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34] = 0x000000ec,// 236 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35] = 0x000000f2,// 242 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0] = 0x0000038c,// 908 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1] = 0x0000037a,// 890 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2] = 0x0000039a,// 922 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3] = 0x00000395,// 917 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[0] = 0x0000007f-0x30,// 127 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[1] = 0x0000007d-0x30,// 125 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[2] = 0x0000006d-0x30,// 109 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[3] = 0x0000006f-0x30,// 111 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[4] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[5] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[6] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[7] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0] = 0x00000048-0x30,// 72 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1] = 0x00000044-0x30,// 68 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2] = 0x00000038-0x30,// 56 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3] = 0x0000003b-0x30,// 59 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4] = 0x00000049-0x30,// 73 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5] = 0x0000004b-0x30,// 75 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6] = 0x0000003b-0x30,// 59 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7] = 0x00000049-0x30,// 73 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9] = 0x00000040-0x30,// 64 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10] = 0x00000052-0x30,// 82 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11] = 0x00000039-0x30,// 57 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12] = 0x00000040-0x30,// 64 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13] = 0x00000045-0x30,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14] = 0x00000042-0x30,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15] = 0x00000034-0x30,// 52 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16] = 0x0000003c-0x30,// 60 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17] = 0x00000086-0x30,// 134 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18] = 0x0000003f-0x30,// 63 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19] = 0x00000048-0x30,// 72 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20] = 0x00000037-0x30,// 55 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21] = 0x00000048-0x30,// 72 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22] = (0x0000004e)-0x30,// 78 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23] = 0x00000044-0x30,// 68 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24] = 0x00000042-0x30,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25] = 0x00000047-0x30,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26] = 0x0000007f-0x30,// 127 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27] = 0x00000040-0x30,// 64 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28] = 0x00000052-0x30,// 82 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29] = 0x0000003d-0x30,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30] = (0x0000004e)-0x30,// 78 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31] = 0x0000003c-0x30,// 60 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32] = (0x0000003e)-0x30,// 62 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33] = 0x0000003f-0x30,// 63 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34] = 0x0000004c-0x30,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35] = 0x00000091-0x30,// 145 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71] = 0x00000000,// 0 - - .cfg_ddr_training_delay_ps[0].reserve_training_parameter = {0}, - .cfg_board_SI_setting_ps[1].DRAMFreq = 667, - .cfg_board_SI_setting_ps[1].PllBypassEn = 0, - .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, - .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, - .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[1].reserve2 = 0, - .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, - .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, - .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, - .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, - .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, - }, //total 36 - .cfg_ddr_training_delay_ps[1].ac_trace_delay = { - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, - }, //total 36 - .cfg_ddr_training_delay_ps[1].write_dqs_delay = { - 0, 0, 0, 0, 0, 0, 0, 0 - }, - .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50 - }, - .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { - 192, 192, 192, 192, 192, 192, 192, 192 - }, //total 8 - .cfg_ddr_training_delay_ps[1].read_dqs_delay = { - 64, 64, 64, 64, 64, 64, 64, 64 - }, //total 8 - .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 - }, //total 72 - .cfg_ddr_training_delay_ps[1].soc_bit_vref = { - 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40 - }, //total 44 - .cfg_ddr_training_delay_ps[1].dram_bit_vref = { - 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32 - }, //total 36 - .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0}, -}, -#endif - -#if ENABLE_LPDDR4 //LPDDR4 rank0,timing_config -{ - .cfg_board_common_setting.timming_magic = 0, - .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, - .cfg_board_common_setting.timming_struct_version = 0, - .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), - .cfg_board_common_setting.timming_struct_real_size = 0, //0 - .cfg_board_common_setting.fast_boot = { 0 }, - .cfg_board_common_setting.ddr_func = 0, - .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, - .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_LPDDR4, - .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH01, - .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, - .cfg_board_common_setting.dram_cs0_base_add = 0, - .cfg_board_common_setting.dram_cs1_base_add = 0, - .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB, - .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, - .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, - .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_1T_MODE, - .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, - .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, //DDR_WRITE_READ_DBI_DISABLE , - .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, - .cfg_board_common_setting.org_tdqs2dq = 0, - .cfg_board_common_setting.reserve1_test_function = { 0 }, - .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT, -#ifdef CONFIG_DDR_WINDOWING_BOOT - .cfg_board_common_setting.fast_boot[0] = 0x1, - .cfg_board_common_setting.fast_boot[3] = 0x46, -#endif - //lpddr4 ac pinmux - .cfg_board_common_setting.ac_pinmux = { - 0, 0, 0, 1, 0, 1, 1, 3, - 0, 4, 4, 2, 0, 0, 1, 0, - 2, 0, 0, 0, 0, 3, 0, 0, - 0, 0, 5, 5, 0, 0, 0, 0, - 0, 0, - }, - .cfg_board_common_setting.ddr_dqs_swap = 0, - - .cfg_board_common_setting.ddr_dq_remap = { - 1, 0, 3, 2, 7, 5, 6, 4, - 9, 15, 13, 14, 10, 11, 12, 8, - 21, 19, 20, 18, 17, 16, 22, 23, - 25, 26, 24, 27, 31, 29, 30, 28, - 32, 33, 34, 35 - }, //d0-d31 dm0 dm1 dm2 dm3 - - .cfg_board_common_setting.ddr_vddee_setting = { 0 }, - .cfg_board_SI_setting_ps[0].DRAMFreq = 1320, - .cfg_board_SI_setting_ps[0].PllBypassEn = 0, - .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_60_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_LPDDR4_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_LPDDR4_ODT_60_OHM, - .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_LPDDR4_AC_ODT_80_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[0].reserve2 = 0, - .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, //3000/11, - .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, //170, - .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, //280, //330 - .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 }, - .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { - 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 0 + 128, //0,0,0,0,0,0,0,0, - 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128, 128 + 20 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - }, //total 36 - - .cfg_ddr_training_delay_ps[0].ac_trace_delay = { - 64 + 128, 64 + 128, 64 + 128-64, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 128 + 128, //0,0,0,0,0,0,0,0, - 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128-40, 128 + 20 + 128-10, 128 + 0 + 128, 128 + 0 + 128+10, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - }, //total 36 - .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 }, - - .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x000000af,// 175 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x000000cd,// 205 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x000000aa,// 170 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x000000cd,// 205 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x000000af,// 175 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x000000cd,// 205 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x000000aa,// 170 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x000000cd,// 205 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x000001cd,// 461 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x000001cc,// 460 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x000001ba,// 442 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000001d8,// 472 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000001e1,// 481 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000001ce,// 462 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000001c6,// 454 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000001d0,// 464 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000001cc,// 460 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000001d9,// 473 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000001da,// 474 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000001c4,// 452 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000001d5,// 469 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000001ea,// 490 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000001e9,// 489 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000001e2,// 482 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000001ea,// 490 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000001d5,// 469 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000001c6,// 454 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000001ce,// 462 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000001b5,// 437 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000001c7,// 455 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000001d3,// 467 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000001d1,// 465 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000001c4,// 452 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000001eb,// 491 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000001d1,// 465 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000001f7,// 503 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000001d8,// 472 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000001cf,// 463 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000001d3,// 467 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000001c9,// 457 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000001de,// 478 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x000001cd,// 461 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x000001cc,// 460 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x000001ba,// 442 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x000001d8,// 472 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x000001e1,// 481 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x000001ce,// 462 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x000001c6,// 454 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x000001d0,// 464 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x000001cc,// 460 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x000001d9,// 473 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x000001da,// 474 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x000001c4,// 452 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x000001d5,// 469 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x000001ea,// 490 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x000001e9,// 489 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x000001e2,// 482 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x000001ea,// 490 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x000001d5,// 469 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x000001c6,// 454 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x000001ce,// 462 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x000001b5,// 437 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x000001c7,// 455 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x000001d3,// 467 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x000001d1,// 465 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x000001c4,// 452 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x000001eb,// 491 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x000001d1,// 465 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x000001f7,// 503 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x000001d8,// 472 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x000001cf,// 463 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x000001d3,// 467 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x000001c9,// 457 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x000001de,// 478 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x000003ab,// 939 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000383,// 899 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000395,// 917 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x00000378,// 888 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x000003ab,// 939 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000383,// 899 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000395,// 917 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000378,// 888 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x0000007e,// 126 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x00000088,// 136 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000070,// 112 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007a,// 122 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x0000007e,// 126 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000088,// 136 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000070,// 112 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x0000007a,// 122 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000044,// 68 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000051,// 81 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x00000036,// 54 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000054,// 84 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x0000003d,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000045,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000051,// 81 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000037,// 55 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x0000003d,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000052,// 82 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x0000005b,// 91 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x0000004c,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000005a,// 90 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x0000004b,// 75 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000042,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x0000004f,// 79 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000030,// 48 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000042,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000004c,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000041,// 65 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000058,// 88 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000045,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000041,// 65 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000056,// 86 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003f,// 63 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000055,// 85 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x0000003e,// 62 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000034,// 52 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x00000031,// 49 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000036,// 54 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000040,// 64 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000044,// 68 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000051,// 81 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000036,// 54 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000054,// 84 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x0000003d,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000045,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000051,// 81 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000037,// 55 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x0000003d,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000052,// 82 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x0000005b,// 91 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x0000004c,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x0000005a,// 90 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x0000004b,// 75 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000042,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x0000004f,// 79 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000030,// 48 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000042,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x0000004c,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000041,// 65 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000058,// 88 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000045,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000041,// 65 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000056,// 86 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x0000003f,// 63 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000055,// 85 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x0000003e,// 62 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000034,// 52 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000031,// 49 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000036,// 54 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000040,// 64 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[0]=0,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[1]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[2]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[3]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[4]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[5]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[6]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[7]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[8]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[9]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[10]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[11]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[12]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[13]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[14]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[15]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[16]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[17]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[18]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[19]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[20]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[21]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[22]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[23]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[24]=0x00000016,// 22 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[25]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[26]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[27]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[28]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[29]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[30]=0x00000016,// 22 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[31]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[32]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[33]=0x00000016,// 22 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[34]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[35]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[36]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[37]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[38]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[39]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[40]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[41]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[42]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[43]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[0]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[1]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[2]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[3]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[4]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[5]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[6]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[7]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[8]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[9]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[10]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[11]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[12]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[13]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[14]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[15]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[16]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[17]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[18]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[19]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[20]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[21]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[22]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[23]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[24]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[25]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[26]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[27]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[28]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[29]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[30]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[31]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[32]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[33]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[34]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[35]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { - (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, - (1 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, - (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, - (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, - }, - .cfg_board_SI_setting_ps[1].DRAMFreq = 667, - .cfg_board_SI_setting_ps[1].PllBypassEn = 0, - .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, - .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, - .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[1].reserve2 = 0, - .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, - .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, - .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, - .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 }, - .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, - }, //total 36 - .cfg_ddr_training_delay_ps[1].ac_trace_delay = { - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, - }, //total 36 - - .cfg_ddr_training_delay_ps[1].write_dqs_delay = { - 0, 0, 0, 0, 0, 0, 0, 0 - }, - .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - }, - .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { - 192, 192, 192, 192, 192, 192, 192, 192 - }, //total 8 - .cfg_ddr_training_delay_ps[1].read_dqs_delay = { - 64, 64, 64, 64, 64, 64, 64, 64 - }, //total 8 - .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 - }, //total 72 - .cfg_ddr_training_delay_ps[1].soc_bit_vref = { - 0, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40 - }, //total 44 - .cfg_ddr_training_delay_ps[1].dram_bit_vref = { - 0, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32 - }, //total 36 - .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 }, -}, -#endif -}; -//ddr timing end - -pll_set_t __pll_setting = { - .cpu_clk = CPU_CLK / 24 * 24, -#ifdef CONFIG_PXP_EMULATOR - .pxp = 1, -#else - .pxp = 0, -#endif - .spi_ctrl = 0, - .lCustomerID = AML_CUSTOMER_ID, - .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */ - .log_ctrl = (1 << 7) | /* (1<<7), print bl2 log into buffer */ -#ifdef CONFIG_SILENT_CONSOLE - (1<<6), /* do not print log buffer */ -#else - (0<<6), /* print log buffer before run bl31 */ -#endif - .ddr_timming_save_mode = 1, -}; - -ddr_reg_t __ddr_reg[] = { - /* demo, user defined override register */ - {0xaabbccdd, 0, 0, 0, 0, 0}, - {0x11223344, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0}, -}; - - - -#define VCCK_VAL AML_VCCK_INIT_VOLTAGE -#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE -/* VCCK PWM table */ -#if (VCCK_VAL == 1039) - #define VCCK_VAL_REG 0x00000022 -#elif (VCCK_VAL == 1029) - #define VCCK_VAL_REG 0x00010021 -#elif (VCCK_VAL == 1019) - #define VCCK_VAL_REG 0x00020020 -#elif (VCCK_VAL == 1009) - #define VCCK_VAL_REG 0x0003001f -#elif (VCCK_VAL == 999) - #define VCCK_VAL_REG 0x0004001e -#elif (VCCK_VAL == 989) - #define VCCK_VAL_REG 0x0005001d -#elif (VCCK_VAL == 979) - #define VCCK_VAL_REG 0x0006001c -#elif (VCCK_VAL == 969) - #define VCCK_VAL_REG 0x0007001b -#elif (VCCK_VAL == 959) - #define VCCK_VAL_REG 0x0008001a -#elif (VCCK_VAL == 949) - #define VCCK_VAL_REG 0x00090019 -#elif (VCCK_VAL == 939) - #define VCCK_VAL_REG 0x000a0018 -#elif (VCCK_VAL == 929) - #define VCCK_VAL_REG 0x000b0017 -#elif (VCCK_VAL == 919) - #define VCCK_VAL_REG 0x000c0016 -#elif (VCCK_VAL == 909) - #define VCCK_VAL_REG 0x000d0015 -#elif (VCCK_VAL == 899) - #define VCCK_VAL_REG 0x000e0014 -#elif (VCCK_VAL == 889) - #define VCCK_VAL_REG 0x000f0013 -#elif (VCCK_VAL == 879) - #define VCCK_VAL_REG 0x00100012 -#elif (VCCK_VAL == 869) - #define VCCK_VAL_REG 0x00110011 -#elif (VCCK_VAL == 859) - #define VCCK_VAL_REG 0x00120010 -#elif (VCCK_VAL == 849) - #define VCCK_VAL_REG 0x0013000f -#elif (VCCK_VAL == 839) - #define VCCK_VAL_REG 0x0014000e -#elif (VCCK_VAL == 829) - #define VCCK_VAL_REG 0x0015000d -#elif (VCCK_VAL == 819) - #define VCCK_VAL_REG 0x0016000c -#elif (VCCK_VAL == 809) - #define VCCK_VAL_REG 0x0017000b -#elif (VCCK_VAL == 799) - #define VCCK_VAL_REG 0x0018000a -#elif (VCCK_VAL == 789) - #define VCCK_VAL_REG 0x00190009 -#elif (VCCK_VAL == 779) - #define VCCK_VAL_REG 0x001a0008 -#elif (VCCK_VAL == 769) - #define VCCK_VAL_REG 0x001b0007 -#elif (VCCK_VAL == 759) - #define VCCK_VAL_REG 0x001c0006 -#elif (VCCK_VAL == 749) - #define VCCK_VAL_REG 0x001d0005 -#elif (VCCK_VAL == 739) - #define VCCK_VAL_REG 0x001e0004 -#elif (VCCK_VAL == 729) - #define VCCK_VAL_REG 0x001f0003 -#elif (VCCK_VAL == 719) - #define VCCK_VAL_REG 0x00200002 -#elif (VCCK_VAL == 709) - #define VCCK_VAL_REG 0x00210001 -#elif (VCCK_VAL == 699) - #define VCCK_VAL_REG 0x00220000 -#else - #error "VCCK val out of range\n" -#endif - -/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/ -#ifdef CONFIG_I2C_REGULATOR -#if (VDDEE_VAL == 711) - #define VDDEE_VAL_REG 0xb -#elif (VDDEE_VAL == 721) - #define VDDEE_VAL_REG 0xc -#elif (VDDEE_VAL == 731) - #define VDDEE_VAL_REG 0xd -#elif (VDDEE_VAL == 741) - #define VDDEE_VAL_REG 0xe -#elif (VDDEE_VAL == 751) - #define VDDEE_VAL_REG 0xf -#elif (VDDEE_VAL == 761) - #define VDDEE_VAL_REG 0x10 -#elif (VDDEE_VAL == 771) - #define VDDEE_VAL_REG 0x11 -#elif (VDDEE_VAL == 781) - #define VDDEE_VAL_REG 0x12 -#elif (VDDEE_VAL == 791) - #define VDDEE_VAL_REG 0x13 -#elif (VDDEE_VAL == 801) - #define VDDEE_VAL_REG 0x14 -#elif (VDDEE_VAL == 811) - #define VDDEE_VAL_REG 0x15 -#elif (VDDEE_VAL == 821) - #define VDDEE_VAL_REG 0x16 -#elif (VDDEE_VAL == 831) - #define VDDEE_VAL_REG 0x17 -#elif (VDDEE_VAL == 841) - #define VDDEE_VAL_REG 0x18 -#elif (VDDEE_VAL == 851) - #define VDDEE_VAL_REG 0x19 -#elif (VDDEE_VAL == 861) - #define VDDEE_VAL_REG 0x1a -#elif (VDDEE_VAL == 871) - #define VDDEE_VAL_REG 0x1b -#elif (VDDEE_VAL == 881) - #define VDDEE_VAL_REG 0x1c -#elif (VDDEE_VAL == 891) - #define VDDEE_VAL_REG 0x1d -#else - #error "VDDEE val out of range\n" -#endif - -#else - -#if (VDDEE_VAL == 711) - #define VDDEE_VAL_REG 0x120000 -#elif (VDDEE_VAL == 721) - #define VDDEE_VAL_REG 0x110001 -#elif (VDDEE_VAL == 731) - #define VDDEE_VAL_REG 0x100002 -#elif (VDDEE_VAL == 741) - #define VDDEE_VAL_REG 0xf0003 -#elif (VDDEE_VAL == 751) - #define VDDEE_VAL_REG 0xe0004 -#elif (VDDEE_VAL == 761) - #define VDDEE_VAL_REG 0xd0005 -#elif (VDDEE_VAL == 771) - #define VDDEE_VAL_REG 0xc0006 -#elif (VDDEE_VAL == 781) - #define VDDEE_VAL_REG 0xb0007 -#elif (VDDEE_VAL == 791) - #define VDDEE_VAL_REG 0xa0008 -#elif (VDDEE_VAL == 801) - #define VDDEE_VAL_REG 0x90009 -#elif (VDDEE_VAL == 811) - #define VDDEE_VAL_REG 0x8000a -#elif (VDDEE_VAL == 821) - #define VDDEE_VAL_REG 0x7000b -#elif (VDDEE_VAL == 831) - #define VDDEE_VAL_REG 0x6000c -#elif (VDDEE_VAL == 841) - #define VDDEE_VAL_REG 0x5000d -#elif (VDDEE_VAL == 851) - #define VDDEE_VAL_REG 0x4000e -#elif (VDDEE_VAL == 861) - #define VDDEE_VAL_REG 0x3000f -#elif (VDDEE_VAL == 871) - #define VDDEE_VAL_REG 0x20010 -#elif (VDDEE_VAL == 881) - #define VDDEE_VAL_REG 0x10011 -#elif (VDDEE_VAL == 891) - #define VDDEE_VAL_REG 0x12 -#else - #error "VDDEE val out of range\n" -#endif -#endif - -/* for PWM use */ -/* - * GPIOE_0 PWM_A VDDEE_PWM - * - * GPIOE_1 PWM_B VCCK_PWM - */ -/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */ -#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400) -#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400) - -/* pwm clock and pwm controller */ -#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800) -#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400) -#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400) -#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400) - -bl2_reg_t __bl2_reg[] = { -#ifdef CONFIG_I2C_REGULATOR - /* demo, user defined override register */ - {0, 0, 0xffffffff, 0, 0, 0}, - {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, - {PWMAB_MISC_REG_AB, 0x1 << 1, 0x1 << 1, 0, BL2_INIT_STAGE_1, 0}, - /* Set GPIOA_5 low */ - {PADCTRL_GPIOA_O, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_GPIOA_OEN, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, - /* Set GPIOD_10 low */ - {PADCTRL_GPIOD_O, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, - /* Set GPIOX_11 low */ - {PADCTRL_GPIOX_O, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_GPIOX_OEN, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, - /* set pwm A and pwm B clock rate to 24M, enable them */ - {CLKTREE_PWM_CLK_AB_CTRL, 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, - /* set GPIOE_0 GPIOE_1 drive strength to 3*/ - {PADCTRL_GPIOE_DS, 0x3 << 2, 0x3 << 2, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, -#ifdef CONFIG_PDVFS_ENABLE - /* table_id, ee_voltage, ...... */ - {1, 0x11, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, - {2, 0x14, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, - {3, 0x16, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, -#else - {0x0, VDDEE_VAL_REG, 0x0, 0, BL2_INIT_STAGE_I2C_REGULATOR, 0}, -#endif -#else - /* demo, user defined override register */ - {0, 0, 0xffffffff, 0, 0, 0}, -#ifdef CONFIG_PDVFS_ENABLE - {PWMAB_PWM_A, 0x000c0006, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, - {PWMAB_PWM_A, 0x00090009, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, - {PWMAB_PWM_A, 0x0007000b, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, -#else - {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, -#endif - {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, - {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0}, - /* enable vddcpu dc-dc, set GPIOD_10 high */ - {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, - /* set pwm A and pwm B clock rate to 24M, enable them */ - {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, - /* set GPIOE_0 GPIOE_1 drive strength to 3*/ - {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, -#endif -};
diff --git a/board/amlogic/c2_bla4_p1/Kconfig b/board/amlogic/c2_bla4_p1/Kconfig deleted file mode 100644 index 99d02ec..0000000 --- a/board/amlogic/c2_bla4_p1/Kconfig +++ /dev/null
@@ -1,37 +0,0 @@ -if TARGET_C2_BLA4_P1 - -config SYS_SOC - default "c2" - -config SYS_BOARD - default "c2_bla4_p1" - -config SYS_VENDOR - default "amlogic" - -config SYS_CONFIG_NAME - default "c2_bla4_p1" - -config DTB_BIND_KERNEL - bool "load dtb from boot part but not flash rsv" - default n - -config CMD_PLLTEST - bool "support plltest command" - default y - help - support plltest command - -config I2C_REGULATOR - bool "use i2c regulator to configure vddee" - default n - -config DDR_WINDOWING_BOOT - bool "enable/disable ddr windowing boot" - default n - -config LED_AW2026 - bool "enable/disable AW2026 LED" - default y - -endif
diff --git a/board/amlogic/c2_bla4_p1/Makefile b/board/amlogic/c2_bla4_p1/Makefile deleted file mode 100644 index 0403c0c..0000000 --- a/board/amlogic/c2_bla4_p1/Makefile +++ /dev/null
@@ -1 +0,0 @@ -obj-y += $(BOARD).o
diff --git a/board/amlogic/c2_bla4_p1/aml-user-key.sig b/board/amlogic/c2_bla4_p1/aml-user-key.sig deleted file mode 100644 index 0f89a75..0000000 --- a/board/amlogic/c2_bla4_p1/aml-user-key.sig +++ /dev/null Binary files differ
diff --git a/board/amlogic/c2_bla4_p1/c2_bla4_p1.c b/board/amlogic/c2_bla4_p1/c2_bla4_p1.c deleted file mode 100644 index bb85c68..0000000 --- a/board/amlogic/c2_bla4_p1/c2_bla4_p1.c +++ /dev/null
@@ -1,319 +0,0 @@ - -/* - * Copyright (C) 2015 Amlogic, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -*/ - -#include <common.h> -#include <asm/io.h> -#include <malloc.h> -#include <errno.h> -#include <environment.h> -#include <fdt_support.h> -#include <linux/libfdt.h> -#include <amlogic/cpu_id.h> -#include <asm/arch/secure_apb.h> -#include <asm/arch/pinctrl_init.h> -#include <linux/sizes.h> -#include <asm-generic/gpio.h> -#include <dm.h> -#include <asm/armv8/mmu.h> -#include <amlogic/aml_v3_burning.h> -#include <amlogic/aml_v2_burning.h> -#include <amlogic/leds-aw2026.h> -#include <linux/mtd/partitions.h> -#include <linux/ssr/ps13216.h> - -DECLARE_GLOBAL_DATA_PTR; - -int serial_set_pin_port(unsigned long port_base) -{ - return 0; -} - -int dram_init(void) -{ - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -unsigned int get_dram_size(void) -{ - // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 -#if defined(CONFIG_SYS_MEM_TOP_HIDE) - return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; -#else - return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); -#endif /* CONFIG_SYS_MEM_TOP_HIDE */ -} - - -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = get_dram_size(); - return 0; -} - -/* secondary_boot_func - * this function should be write with asm, here, is is only for compiling pass - * */ -void secondary_boot_func(void) -{ -} - -int board_eth_init(bd_t *bis) -{ - return 0; -} - -int active_clk(void) -{ - struct udevice *clk = NULL; - int err; - - err = uclass_get_device_by_name(UCLASS_CLK, - "xtal-clk", &clk); - if (err) { - pr_err("Can't find xtal-clk clock (%d)\n", err); - return err; - } - err = uclass_get_device_by_name(UCLASS_CLK, - "clock-controller@0", &clk); - if (err) { - pr_err("Can't find clock-controller@0 clock (%d)\n", err); - return err; - } - - return 0; -} - -void board_init_mem(void) { - /* config bootm low size, make sure whole dram/psram space can be used */ - phys_size_t ram_size; - char *env_tmp; - env_tmp = env_get("bootm_size"); - if (!env_tmp) { - ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); - env_set_hex("bootm_low", 0); - env_set_hex("bootm_size", ram_size); - } -} - -int board_init(void) -{ - unsigned int value; - - printf("board init\n"); - - /* set GPIOB_3 to low before emmc init */ - value = readl(PADCTRL_PIN_MUX_REG3); - /* set to gpio pin */ - writel(value & ~(0xf << 12), PADCTRL_PIN_MUX_REG3); - value = readl(PADCTRL_GPIOB_OEN); - /* enable gpio output */ - writel(value & ~(0x1 << 3), PADCTRL_GPIOB_OEN); - value = readl(PADCTRL_GPIOB_O); - /* set output value to low */ - writel(value & ~(0x1 << 3), PADCTRL_GPIOB_O); - udelay(20000); - - //Please keep try usb boot first in board_init, as other init before usb may cause burning failure -#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) - if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2))) - { aml_v3_factory_usb_burning(0, gd->bd); } -#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) - - pinctrl_devices_active(PIN_CONTROLLER_NUM); - active_clk(); - - // set to white by default - sys_led_init(WHITE); - return 0; -} - -int board_late_init(void) -{ - board_init_mem(); - -#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard - aml_try_factory_sdcard_burning(0, gd->bd); -#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE - //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003' -#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) - if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2)) - { aml_v3_factory_usb_burning(0, gd->bd); } -#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) - - return 0; -} - - -phys_size_t get_effective_memsize(void) -{ -#ifdef UBOOT_RUN_IN_SRAM - return 0x180000; /* SRAM 1.5MB */ -#else - // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 -#if defined(CONFIG_SYS_MEM_TOP_HIDE) - return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; -#else - return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); -#endif /* CONFIG_SYS_MEM_TOP_HIDE */ -#endif /* UBOOT_RUN_IN_SRAM */ -} - -static struct mm_region bd_mem_map[] = { - { - .virt = 0x00000000UL, - .phys = 0x00000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = bd_mem_map; - -int mach_cpu_init(void) { - printf("\nmach_cpu_init\n"); - return 0; -} - -int ft_board_setup(void *blob, bd_t *bd) -{ - /* eg: bl31/32 rsv */ - return 0; -} - -int do_get_hw_id(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) -{ - unsigned int hw_bid = 0, hw_cid = 0, ret = 0; - char hw_id_str[8] = {0}; // eg: 0x0A - - /* - * HW_BID_2 : GPIOD_8 - * HW_BID_1 : GPIOD_5 - * HW_BID_0 : GPIOD_4 - * HW_CID_2 : GPIOX_10 - * HW_CID_1 : GPIOX_9 - * HW_CID_0 : GPIOX_8 - * - */ - /* disable gpio pull */ - ret = readl(PADCTRL_GPIOD_PULL_EN); - writel(ret & (~(0x13 << 4)), PADCTRL_GPIOD_PULL_EN); - ret = readl(PADCTRL_GPIOX_PULL_EN); - writel(ret & (~(0x7 << 8)), PADCTRL_GPIOX_PULL_EN); - - /* pin mux to gpio pin */ - /* GPIOD_4, GPIOD_5 */ - ret = readl(PADCTRL_PIN_MUX_REG0); - writel(ret & (~(0xFF << 16)), PADCTRL_PIN_MUX_REG0); - /* GPIOD_8 */ - ret = readl(PADCTRL_PIN_MUX_REG1); - writel(ret & (~(0xF << 0)), PADCTRL_PIN_MUX_REG1); - /* GPIOX_8, GPIOX_9, GPIOX_10 */ - ret = readl(PADCTRL_PIN_MUX_REG7); - writel(ret & (~(0xFFF << 0)), PADCTRL_PIN_MUX_REG7); - - /* enable input */ - ret = readl(PADCTRL_GPIOD_OEN); - writel(ret | (0x13 << 4), PADCTRL_GPIOD_OEN); - ret = readl(PADCTRL_GPIOX_OEN); - writel(ret | (0x7 << 8), PADCTRL_GPIOX_OEN); - - /* read hw id */ - ret = readl(PADCTRL_GPIOD_I); - hw_bid = (ret >> 4) & 0x3; - hw_bid |= (ret >> 6) & 0x4; - ret = readl(PADCTRL_GPIOX_I); - hw_cid = (ret >> 8) & 0x7; - - if (BLA4_HW_CID != hw_cid) { - pr_err("The image doesn't match the device(CID=0x%x)\n", hw_cid); - sys_led_init(YELLOW); - while(1); - } - - ret = (hw_cid << 0x3) | hw_bid; - snprintf(hw_id_str, sizeof(hw_id_str), "0x%02x", ret); - env_set("hw_id", hw_id_str); - return 0; -} - -U_BOOT_CMD( - get_hw_id, 1, 0, do_get_hw_id, "get HW_ID and env_set 'hw_id'\n", "get_hw_id" -); - -/* partition table */ -/* partition table for spinand flash */ -#ifdef CONFIG_SPI_NAND -static const struct mtd_partition spinand_partitions[] = { - { - .name = "logo", - .offset = 0, - .size = 2 * SZ_1M, - }, - { - .name = "recovery", - .offset = 0, - .size = 16 * SZ_1M, - }, - { - .name = "boot", - .offset = 0, - .size = 16 * SZ_1M, - }, - { - .name = "system", - .offset = 0, - .size = 64 * SZ_1M, - }, - /* last partition get the rest capacity */ - { - .name = "data", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - } -}; -struct mtd_partition *get_partition_table(int *partitions) -{ - *partitions = ARRAY_SIZE(spinand_partitions); - return spinand_partitions; -} -#endif /* CONFIG_SPI_NAND */ - -int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;} - -int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;} - -void __attribute__((weak)) set_working_fdt_addr(ulong addr) {} - -int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;} - -void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c2_bla4_p1/firmware/timing.c b/board/amlogic/c2_bla4_p1/firmware/timing.c deleted file mode 100755 index e1067e1..0000000 --- a/board/amlogic/c2_bla4_p1/firmware/timing.c +++ /dev/null
@@ -1,1457 +0,0 @@ -/* - * board/amlogic/c2_bla4_p1/firmware/timing.c - * - * Copyright (C) 2015 Amlogic, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -*/ - -#include <asm/arch/secure_apb.h> -#include <asm/arch/timing.h> -#include <asm/arch/ddr_define.h> - -/* board clk defines */ -#define CPU_CLK 1512 -#define TIMMING_MAX_CONFIG 1 -#define ENABLE_DDR3 0 -#define ENABLE_DDR4 1 -#define ENABLE_LPDDR4 0 - -ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = { -#if ENABLE_DDR4 -{ - .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, - .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4, - .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, - .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096 - .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, - .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, - .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, - .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, - .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT, - .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)}, - .cfg_board_common_setting. fast_boot[0] = 0x1, - .cfg_board_common_setting. fast_boot[3] = 0x46, - - //DDR frequercy 1 - .cfg_board_SI_setting_ps[0].DRAMFreq = 1272,//1320,1200,1104,1008,912,792 - .cfg_board_SI_setting_ps[0].PllBypassEn = 0, - .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_48_OHM, - .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, - .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[0].reserve2 = 0, - .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, - .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, - .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, - .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, - .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { - 128,128,128-20,128,128,128,128,128, - 384,384,384,384,384,384,384,384, - 384,384,384,384,384,384,384,384, - 384,384,384,384,384,384,384,384, - 384,384,384,384, - },//total 36 - - .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { - 128,128,128-20,128,128,128,128,128, - 384,384,384,384,384,384,384,384, - 384,384,384,384,384,384,384,384, - 384,384,384,384,384,384,384,384, - 384,384,384,384, - },//total 36 - - .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x0000005f,// 95 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000073,// 115 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x0000005f,// 95 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000087,// 135 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000080,// 128 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000080,// 128 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000080,// 128 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000080,// 128 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000009f,// 159 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000095,// 149 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000092,// 146 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x0000009f,// 159 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000bb,// 187 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000cd,// 205 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000b1,// 177 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000c5,// 197 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000ad,// 173 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000000a1,// 161 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000d3,// 211 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000000a2,// 162 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000d1,// 209 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000000d3,// 211 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000d0,// 208 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000000a7,// 167 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000a9,// 169 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000000b9,// 185 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000000ae,// 174 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000b1,// 177 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000b2,// 178 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000bd,// 189 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000000d1,// 209 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000d0,// 208 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000c6,// 198 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000d1,// 209 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000bf,// 191 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000000c1,// 193 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000d3,// 211 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000000c1,// 193 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000dc,// 220 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000000ae,// 174 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000a1,// 161 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000ab,// 171 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000ac,// 172 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000bd,// 189 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000037a,// 890 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000359,// 857 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000352,// 850 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x0000034f,// 847 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000075,// 117 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x0000006c,// 108 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000058,// 88 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007c,// 124 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000034,// 52 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000033,// 51 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000002b,// 43 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000032,// 50 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000050,// 80 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000062,// 98 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000043,// 67 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000058,// 88 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000028,// 40 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000028,// 40 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000036,// 54 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000044,// 68 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x00000042,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000026,// 38 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000002c,// 44 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x0000002a,// 42 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x00000032,// 50 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000029,// 41 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x0000002c,// 44 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000048,// 72 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000003e,// 62 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x0000003b,// 59 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x0000003b,// 59 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000050,// 80 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003d,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x00000030,// 48 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x0000002e,// 46 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000002f,// 47 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000033,// 51 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0 - - .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { - 0,40,40,40,40,40,40,40,40,40,40, - 40,40,40,40,40,40,40,40,40,40,40, - 40,40,40,40,40,40,40,40,40,40,40, - 40,40,40,40,50,40,50,40,50,40,50},//total 44 - .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { - 0,32,32,32,32,32,32,32,32,32,32, - 32,32,32,32,32,32,32,32,32,32,32, - 32,32,32,32,32,32,32,32,32,32,32, - 32,32,32},//total 36 - .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { - (0 << 7) | 6, (0 << 7) | 6, (1 << 7) | 5, (0 << 7) | 0, - (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, - (1 << 7) | 10, (1 << 7) | 10, (1 << 7) | 10, (1 << 7) | 10, - (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, - }, - - //pinmux setting - .cfg_board_common_setting. ac_pinmux = { - 0, 0, 0, 1, 2, 3, - 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, - }, - .cfg_board_common_setting. ddr_dqs_swap = 0, - - .cfg_board_common_setting. ddr_dq_remap = { - 0,1,2,3,4,5,6,7, - 8,9,10,11,12,13,14,15, - 16,17,18,19,20,21,22,23, - 24,25,26,27,28,29,30,31, - 32,33,34,35 - },//d0-d31 dm0 dm1 dm2 dm3 - - .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start - .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), - .cfg_board_common_setting. timming_struct_version = 0, - .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), - .cfg_board_common_setting. timming_struct_real_size = 0, //0 - .cfg_board_common_setting. ddr_func = 0, - .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, - .cfg_board_common_setting. dram_cs0_base_add = 0, - .cfg_board_common_setting. dram_cs1_base_add = 0, - - .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE, - .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, - .cfg_board_common_setting. org_tdqs2dq = 0, - .cfg_board_common_setting. reserve1_test_function = {0}, - .cfg_board_common_setting. ddr_vddee_setting = {0}, - - //DDR frequercy 2 - .cfg_board_SI_setting_ps[1].DRAMFreq = 600, - .cfg_board_SI_setting_ps[1].PllBypassEn = 0, - .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, - .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, - .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[1].reserve2 = 0, - .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, - .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, - .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, - .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, - .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { - 128,128,128,128,128,128,128,128, - 128,128,128,128,128,128,128,128, - 128,128,128,128,128,128,128,128, - 128,128,128,128,128,128,128,128, - 128,128,128,128, - },//total 36 - - .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { - 128,128,128,128,128,128,128,128, - 128,128,128,128,128,128,128,128, - 128,128,128,128,128,128,128,128, - 128,128,128,128,128,128,128,128, - 128,128,128,128, - },//total 36 - .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, - //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, - .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50,}, - - //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 - .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 - //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 - .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 - .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0},//total 72 - .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { - 40,40,40,40,40,40,40,40,40,40,40, - 40,40,40,40,40,40,40,40,40,40,40, - 40,40,40,40,40,40,40,40,40,40,40, - 40,40,40,40,40,40,40,40,40,40,40},//total 44 - .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { - 32,32,32,32,32,32,32,32,32,32,32, - 32,32,32,32,32,32,32,32,32,32,32, - 32,32,32,32,32,32,32,32,32,32,32, - 32,32,32},//total 36 - - .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end -}, -#endif //end ENABLE_DDR4 -#if ENABLE_DDR3 -{ - .cfg_board_common_setting.timming_magic = 0, - .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, - .cfg_board_common_setting.timming_struct_version = 0, - .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), - .cfg_board_common_setting.timming_struct_real_size = 0, //0 - .cfg_board_common_setting.fast_boot = {0}, - .cfg_board_common_setting.ddr_func = 0, - .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, - .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR3, - .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0, - .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, - .cfg_board_common_setting.dram_cs0_base_add = 0, - .cfg_board_common_setting.dram_cs1_base_add = 0, - .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB, - .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, - .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, - .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE, - .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, - .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, - .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, - .cfg_board_common_setting.org_tdqs2dq = 0, - .cfg_board_common_setting.reserve1_test_function = {0}, - .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT, - .cfg_board_common_setting.ac_pinmux = - { - 0, 0, 0, 1, 2, 3, 0, 1, - 2, 3, 4, 5, 6, 7, 8, 9, - 10, 11, 12, 13, 14, 15, 0, 0, - 0, 0, 20, 21, 22, 0, 0, 25, - 26, 27, 0 - }, - .cfg_board_common_setting.ddr_dqs_swap = 0, - .cfg_board_common_setting.ddr_dq_remap = { - 0, 1, 2, 3, 4, 5, 6, 7, - 8, 9, 10, 11, 12, 13, 14, 15, - 16, 17, 18, 19, 20, 21, 22, 23, - 24, 25, 26, 27, 28, 29, 30, 31, - 32, 33, 34, 35, - }, //d0-d31 dm0 dm1 dm2 dm3 - .cfg_board_common_setting.ddr_vddee_setting = {0}, - .cfg_board_SI_setting_ps[0].DRAMFreq = 912, - .cfg_board_SI_setting_ps[0].PllBypassEn = 0, - .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM, - .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[0].reserve2 = 0, - .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, - .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, - .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, - .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, - .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { - 128, 128, 128 - 20, 128, 128, 128, 128, 128, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, - }, //total 36 - - .cfg_ddr_training_delay_ps[0].ac_trace_delay = { - 128, 128, 128 - 20, 128, 128, 128, 128, 128, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, - }, //total 36 - .cfg_ddr_training_delay_ps[0].write_dqs_delay = { - 128 - 1, 128 - 1, 128 + 48, 128 + 58, 128 + 32, 128 + 32, 128 + 32, 128 + 32 - }, - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay = { - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, - 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, - 128 + 128, 128 + 128, 128 + 128, 128 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - }, - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay = { - 896, 896, 896, 896, 896, 896, 896, 896 - }, //total 8 - .cfg_ddr_training_delay_ps[0].read_dqs_delay = { - 64, 64, 50, 40, 64, 64, 64, 64 - }, //total 8 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay = { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 - }, //total 72 - .cfg_ddr_training_delay_ps[0].soc_bit_vref = { - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32 + 5, 32, 32 + 5, - 32, 32 + 5, 32, 32 + 5 - }, - .cfg_ddr_training_delay_ps[0].dram_bit_vref = { - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32 - }, //total 36 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[0] = 0x0000007d,// 125 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[1] = 0x00000091,// 145 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[2] = 0x00000091,// 145 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[3] = 0x0000009b,// 155 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[4] = 0x000000a0,// 160 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[5] = 0x000000a0,// 160 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[6] = 0x000000a0,// 160 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[7] = 0x000000a0,// 160 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0] = 0x000000c2,// 194 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1] = 0x000000b0,// 176 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2] = 0x000000af,// 175 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3] = 0x000000b0,// 176 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4] = 0x000000c0,// 192 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5] = 0x000000c3,// 195 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6] = 0x000000b4,// 180 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7] = 0x000000be,// 190 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8] = 0x000000ba,// 186 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9] = 0x000000c1,// 193 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10] = 0x000000d5,// 213 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11] = 0x000000c1,// 193 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12] = 0x000000d0,// 208 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13] = 0x000000cc,// 204 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14] = 0x000000c3,// 195 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15] = 0x000000be,// 190 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16] = 0x000000c0,// 192 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17] = 0x000000c8,// 200 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18] = 0x000000e0,// 224 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19] = 0x000000e5,// 229 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20] = 0x000000e2,// 226 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21] = 0x000000ec,// 236 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22] = 0x000000ec,// 236 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23] = 0x000000e7,// 231 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24] = 0x000000e4,// 228 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25] = 0x000000e9,// 233 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26] = 0x000000e6,// 230 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27] = 0x000000eb,// 235 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28] = 0x000000f5,// 245 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29] = 0x000000e7,// 231 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30] = 0x000000fd,// 253 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31] = 0x000000e8,// 232 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32] = 0x000000e4,// 228 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33] = 0x000000ee,// 238 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34] = 0x000000ec,// 236 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35] = 0x000000f2,// 242 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0] = 0x0000038c,// 908 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1] = 0x0000037a,// 890 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2] = 0x0000039a,// 922 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3] = 0x00000395,// 917 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[0] = 0x0000007f-0x30,// 127 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[1] = 0x0000007d-0x30,// 125 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[2] = 0x0000006d-0x30,// 109 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[3] = 0x0000006f-0x30,// 111 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[4] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[5] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[6] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[7] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0] = 0x00000048-0x30,// 72 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1] = 0x00000044-0x30,// 68 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2] = 0x00000038-0x30,// 56 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3] = 0x0000003b-0x30,// 59 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4] = 0x00000049-0x30,// 73 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5] = 0x0000004b-0x30,// 75 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6] = 0x0000003b-0x30,// 59 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7] = 0x00000049-0x30,// 73 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9] = 0x00000040-0x30,// 64 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10] = 0x00000052-0x30,// 82 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11] = 0x00000039-0x30,// 57 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12] = 0x00000040-0x30,// 64 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13] = 0x00000045-0x30,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14] = 0x00000042-0x30,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15] = 0x00000034-0x30,// 52 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16] = 0x0000003c-0x30,// 60 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17] = 0x00000086-0x30,// 134 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18] = 0x0000003f-0x30,// 63 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19] = 0x00000048-0x30,// 72 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20] = 0x00000037-0x30,// 55 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21] = 0x00000048-0x30,// 72 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22] = (0x0000004e)-0x30,// 78 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23] = 0x00000044-0x30,// 68 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24] = 0x00000042-0x30,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25] = 0x00000047-0x30,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26] = 0x0000007f-0x30,// 127 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27] = 0x00000040-0x30,// 64 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28] = 0x00000052-0x30,// 82 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29] = 0x0000003d-0x30,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30] = (0x0000004e)-0x30,// 78 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31] = 0x0000003c-0x30,// 60 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32] = (0x0000003e)-0x30,// 62 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33] = 0x0000003f-0x30,// 63 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34] = 0x0000004c-0x30,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35] = 0x00000091-0x30,// 145 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71] = 0x00000000,// 0 - - .cfg_ddr_training_delay_ps[0].reserve_training_parameter = {0}, - .cfg_board_SI_setting_ps[1].DRAMFreq = 667, - .cfg_board_SI_setting_ps[1].PllBypassEn = 0, - .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, - .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, - .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[1].reserve2 = 0, - .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, - .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, - .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, - .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, - .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, - }, //total 36 - .cfg_ddr_training_delay_ps[1].ac_trace_delay = { - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, - }, //total 36 - .cfg_ddr_training_delay_ps[1].write_dqs_delay = { - 0, 0, 0, 0, 0, 0, 0, 0 - }, - .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50 - }, - .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { - 192, 192, 192, 192, 192, 192, 192, 192 - }, //total 8 - .cfg_ddr_training_delay_ps[1].read_dqs_delay = { - 64, 64, 64, 64, 64, 64, 64, 64 - }, //total 8 - .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 - }, //total 72 - .cfg_ddr_training_delay_ps[1].soc_bit_vref = { - 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40 - }, //total 44 - .cfg_ddr_training_delay_ps[1].dram_bit_vref = { - 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32 - }, //total 36 - .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0}, -}, -#endif - -#if ENABLE_LPDDR4 //LPDDR4 rank0,timing_config -{ - .cfg_board_common_setting.timming_magic = 0, - .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, - .cfg_board_common_setting.timming_struct_version = 0, - .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), - .cfg_board_common_setting.timming_struct_real_size = 0, //0 - .cfg_board_common_setting.fast_boot = { 0 }, - .cfg_board_common_setting.ddr_func = 0, - .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, - .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_LPDDR4, - .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH01, - .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, - .cfg_board_common_setting.dram_cs0_base_add = 0, - .cfg_board_common_setting.dram_cs1_base_add = 0, - .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB, - .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, - .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, - .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_1T_MODE, - .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, - .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, //DDR_WRITE_READ_DBI_DISABLE , - .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, - .cfg_board_common_setting.org_tdqs2dq = 0, - .cfg_board_common_setting.reserve1_test_function = { 0 }, - .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT, -#ifdef CONFIG_DDR_WINDOWING_BOOT - .cfg_board_common_setting.fast_boot[0] = 0x1, - .cfg_board_common_setting.fast_boot[3] = 0x46, -#endif - //lpddr4 ac pinmux - .cfg_board_common_setting.ac_pinmux = { - 0, 0, 0, 1, 0, 1, 1, 3, - 0, 4, 4, 2, 0, 0, 1, 0, - 2, 0, 0, 0, 0, 3, 0, 0, - 0, 0, 5, 5, 0, 0, 0, 0, - 0, 0, - }, - .cfg_board_common_setting.ddr_dqs_swap = 0, - - .cfg_board_common_setting.ddr_dq_remap = { - 1, 0, 3, 2, 7, 5, 6, 4, - 9, 15, 13, 14, 10, 11, 12, 8, - 21, 19, 20, 18, 17, 16, 22, 23, - 25, 26, 24, 27, 31, 29, 30, 28, - 32, 33, 34, 35 - }, //d0-d31 dm0 dm1 dm2 dm3 - - .cfg_board_common_setting.ddr_vddee_setting = { 0 }, - .cfg_board_SI_setting_ps[0].DRAMFreq = 1320, - .cfg_board_SI_setting_ps[0].PllBypassEn = 0, - .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_60_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_LPDDR4_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_LPDDR4_ODT_60_OHM, - .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_LPDDR4_AC_ODT_80_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[0].reserve2 = 0, - .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, //3000/11, - .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, //170, - .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, //280, //330 - .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 }, - .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { - 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 0 + 128, //0,0,0,0,0,0,0,0, - 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128, 128 + 20 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - }, //total 36 - - .cfg_ddr_training_delay_ps[0].ac_trace_delay = { - 64 + 128, 64 + 128, 64 + 128-64, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 128 + 128, //0,0,0,0,0,0,0,0, - 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128-40, 128 + 20 + 128-10, 128 + 0 + 128, 128 + 0 + 128+10, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - }, //total 36 - .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 }, - - .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x000000af,// 175 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x000000cd,// 205 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x000000aa,// 170 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x000000cd,// 205 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x000000af,// 175 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x000000cd,// 205 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x000000aa,// 170 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x000000cd,// 205 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x000001cd,// 461 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x000001cc,// 460 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x000001ba,// 442 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000001d8,// 472 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000001e1,// 481 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000001ce,// 462 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000001c6,// 454 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000001d0,// 464 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000001cc,// 460 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000001d9,// 473 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000001da,// 474 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000001c4,// 452 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000001d5,// 469 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000001ea,// 490 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000001e9,// 489 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000001e2,// 482 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000001ea,// 490 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000001d5,// 469 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000001c6,// 454 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000001ce,// 462 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000001b5,// 437 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000001c7,// 455 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000001d3,// 467 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000001d1,// 465 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000001c4,// 452 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000001eb,// 491 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000001d1,// 465 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000001f7,// 503 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000001d8,// 472 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000001cf,// 463 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000001d3,// 467 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000001c9,// 457 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000001de,// 478 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x000001cd,// 461 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x000001cc,// 460 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x000001ba,// 442 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x000001d8,// 472 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x000001e1,// 481 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x000001ce,// 462 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x000001c6,// 454 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x000001d0,// 464 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x000001cc,// 460 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x000001d9,// 473 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x000001da,// 474 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x000001c4,// 452 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x000001d5,// 469 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x000001ea,// 490 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x000001e9,// 489 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x000001e2,// 482 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x000001ea,// 490 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x000001d5,// 469 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x000001c6,// 454 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x000001ce,// 462 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x000001b5,// 437 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x000001c7,// 455 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x000001d3,// 467 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x000001d1,// 465 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x000001c4,// 452 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x000001eb,// 491 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x000001d1,// 465 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x000001f7,// 503 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x000001d8,// 472 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x000001cf,// 463 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x000001d3,// 467 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x000001c9,// 457 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x000001de,// 478 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x000003ab,// 939 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000383,// 899 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000395,// 917 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x00000378,// 888 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x000003ab,// 939 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000383,// 899 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000395,// 917 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000378,// 888 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x0000007e,// 126 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x00000088,// 136 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000070,// 112 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007a,// 122 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x0000007e,// 126 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000088,// 136 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000070,// 112 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x0000007a,// 122 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000044,// 68 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000051,// 81 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x00000036,// 54 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000054,// 84 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x0000003d,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000045,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000051,// 81 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000037,// 55 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x0000003d,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000052,// 82 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x0000005b,// 91 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x0000004c,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000005a,// 90 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x0000004b,// 75 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000042,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x0000004f,// 79 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000030,// 48 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000042,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000004c,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000041,// 65 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000058,// 88 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000045,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000041,// 65 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000056,// 86 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003f,// 63 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000055,// 85 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x0000003e,// 62 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000034,// 52 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x00000031,// 49 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000036,// 54 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000040,// 64 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000044,// 68 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000051,// 81 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000036,// 54 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000054,// 84 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x0000003d,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000045,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000051,// 81 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000037,// 55 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x0000003d,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000052,// 82 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x0000005b,// 91 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x0000004c,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x0000005a,// 90 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x0000004b,// 75 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000042,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x0000004f,// 79 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000030,// 48 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000042,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x0000004c,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000041,// 65 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000058,// 88 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000045,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000041,// 65 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000056,// 86 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x0000003f,// 63 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000055,// 85 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x0000003e,// 62 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000034,// 52 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000031,// 49 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000036,// 54 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000040,// 64 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[0]=0,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[1]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[2]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[3]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[4]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[5]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[6]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[7]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[8]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[9]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[10]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[11]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[12]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[13]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[14]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[15]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[16]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[17]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[18]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[19]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[20]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[21]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[22]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[23]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[24]=0x00000016,// 22 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[25]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[26]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[27]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[28]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[29]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[30]=0x00000016,// 22 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[31]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[32]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[33]=0x00000016,// 22 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[34]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[35]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[36]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[37]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[38]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[39]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[40]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[41]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[42]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[43]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[0]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[1]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[2]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[3]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[4]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[5]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[6]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[7]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[8]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[9]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[10]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[11]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[12]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[13]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[14]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[15]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[16]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[17]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[18]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[19]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[20]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[21]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[22]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[23]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[24]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[25]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[26]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[27]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[28]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[29]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[30]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[31]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[32]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[33]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[34]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[35]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { - (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, - (1 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, - (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, - (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, - }, - .cfg_board_SI_setting_ps[1].DRAMFreq = 667, - .cfg_board_SI_setting_ps[1].PllBypassEn = 0, - .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, - .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, - .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[1].reserve2 = 0, - .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, - .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, - .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, - .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 }, - .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, - }, //total 36 - .cfg_ddr_training_delay_ps[1].ac_trace_delay = { - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, - }, //total 36 - - .cfg_ddr_training_delay_ps[1].write_dqs_delay = { - 0, 0, 0, 0, 0, 0, 0, 0 - }, - .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - }, - .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { - 192, 192, 192, 192, 192, 192, 192, 192 - }, //total 8 - .cfg_ddr_training_delay_ps[1].read_dqs_delay = { - 64, 64, 64, 64, 64, 64, 64, 64 - }, //total 8 - .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 - }, //total 72 - .cfg_ddr_training_delay_ps[1].soc_bit_vref = { - 0, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40 - }, //total 44 - .cfg_ddr_training_delay_ps[1].dram_bit_vref = { - 0, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32 - }, //total 36 - .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 }, -}, -#endif -}; -//ddr timing end - -pll_set_t __pll_setting = { - .cpu_clk = CPU_CLK / 24 * 24, -#ifdef CONFIG_PXP_EMULATOR - .pxp = 1, -#else - .pxp = 0, -#endif - .spi_ctrl = 0, - .lCustomerID = AML_CUSTOMER_ID, - .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */ - .log_ctrl = (1 << 7) | /* (1<<7), print bl2 log into buffer */ -#ifdef CONFIG_SILENT_CONSOLE - (1<<6), /* do not print log buffer */ -#else - (0<<6), /* print log buffer before run bl31 */ -#endif - .ddr_timming_save_mode = 1, -}; - -ddr_reg_t __ddr_reg[] = { - /* demo, user defined override register */ - {0xaabbccdd, 0, 0, 0, 0, 0}, - {0x11223344, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0}, -}; - - - -#define VCCK_VAL AML_VCCK_INIT_VOLTAGE -#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE -/* VCCK PWM table */ -#if (VCCK_VAL == 1039) - #define VCCK_VAL_REG 0x00000022 -#elif (VCCK_VAL == 1029) - #define VCCK_VAL_REG 0x00010021 -#elif (VCCK_VAL == 1019) - #define VCCK_VAL_REG 0x00020020 -#elif (VCCK_VAL == 1009) - #define VCCK_VAL_REG 0x0003001f -#elif (VCCK_VAL == 999) - #define VCCK_VAL_REG 0x0004001e -#elif (VCCK_VAL == 989) - #define VCCK_VAL_REG 0x0005001d -#elif (VCCK_VAL == 979) - #define VCCK_VAL_REG 0x0006001c -#elif (VCCK_VAL == 969) - #define VCCK_VAL_REG 0x0007001b -#elif (VCCK_VAL == 959) - #define VCCK_VAL_REG 0x0008001a -#elif (VCCK_VAL == 949) - #define VCCK_VAL_REG 0x00090019 -#elif (VCCK_VAL == 939) - #define VCCK_VAL_REG 0x000a0018 -#elif (VCCK_VAL == 929) - #define VCCK_VAL_REG 0x000b0017 -#elif (VCCK_VAL == 919) - #define VCCK_VAL_REG 0x000c0016 -#elif (VCCK_VAL == 909) - #define VCCK_VAL_REG 0x000d0015 -#elif (VCCK_VAL == 899) - #define VCCK_VAL_REG 0x000e0014 -#elif (VCCK_VAL == 889) - #define VCCK_VAL_REG 0x000f0013 -#elif (VCCK_VAL == 879) - #define VCCK_VAL_REG 0x00100012 -#elif (VCCK_VAL == 869) - #define VCCK_VAL_REG 0x00110011 -#elif (VCCK_VAL == 859) - #define VCCK_VAL_REG 0x00120010 -#elif (VCCK_VAL == 849) - #define VCCK_VAL_REG 0x0013000f -#elif (VCCK_VAL == 839) - #define VCCK_VAL_REG 0x0014000e -#elif (VCCK_VAL == 829) - #define VCCK_VAL_REG 0x0015000d -#elif (VCCK_VAL == 819) - #define VCCK_VAL_REG 0x0016000c -#elif (VCCK_VAL == 809) - #define VCCK_VAL_REG 0x0017000b -#elif (VCCK_VAL == 799) - #define VCCK_VAL_REG 0x0018000a -#elif (VCCK_VAL == 789) - #define VCCK_VAL_REG 0x00190009 -#elif (VCCK_VAL == 779) - #define VCCK_VAL_REG 0x001a0008 -#elif (VCCK_VAL == 769) - #define VCCK_VAL_REG 0x001b0007 -#elif (VCCK_VAL == 759) - #define VCCK_VAL_REG 0x001c0006 -#elif (VCCK_VAL == 749) - #define VCCK_VAL_REG 0x001d0005 -#elif (VCCK_VAL == 739) - #define VCCK_VAL_REG 0x001e0004 -#elif (VCCK_VAL == 729) - #define VCCK_VAL_REG 0x001f0003 -#elif (VCCK_VAL == 719) - #define VCCK_VAL_REG 0x00200002 -#elif (VCCK_VAL == 709) - #define VCCK_VAL_REG 0x00210001 -#elif (VCCK_VAL == 699) - #define VCCK_VAL_REG 0x00220000 -#else - #error "VCCK val out of range\n" -#endif - -/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/ -#ifdef CONFIG_I2C_REGULATOR -#if (VDDEE_VAL == 711) - #define VDDEE_VAL_REG 0xb -#elif (VDDEE_VAL == 721) - #define VDDEE_VAL_REG 0xc -#elif (VDDEE_VAL == 731) - #define VDDEE_VAL_REG 0xd -#elif (VDDEE_VAL == 741) - #define VDDEE_VAL_REG 0xe -#elif (VDDEE_VAL == 751) - #define VDDEE_VAL_REG 0xf -#elif (VDDEE_VAL == 761) - #define VDDEE_VAL_REG 0x10 -#elif (VDDEE_VAL == 771) - #define VDDEE_VAL_REG 0x11 -#elif (VDDEE_VAL == 781) - #define VDDEE_VAL_REG 0x12 -#elif (VDDEE_VAL == 791) - #define VDDEE_VAL_REG 0x13 -#elif (VDDEE_VAL == 801) - #define VDDEE_VAL_REG 0x14 -#elif (VDDEE_VAL == 811) - #define VDDEE_VAL_REG 0x15 -#elif (VDDEE_VAL == 821) - #define VDDEE_VAL_REG 0x16 -#elif (VDDEE_VAL == 831) - #define VDDEE_VAL_REG 0x17 -#elif (VDDEE_VAL == 841) - #define VDDEE_VAL_REG 0x18 -#elif (VDDEE_VAL == 851) - #define VDDEE_VAL_REG 0x19 -#elif (VDDEE_VAL == 861) - #define VDDEE_VAL_REG 0x1a -#elif (VDDEE_VAL == 871) - #define VDDEE_VAL_REG 0x1b -#elif (VDDEE_VAL == 881) - #define VDDEE_VAL_REG 0x1c -#elif (VDDEE_VAL == 891) - #define VDDEE_VAL_REG 0x1d -#else - #error "VDDEE val out of range\n" -#endif - -#else - -#if (VDDEE_VAL == 711) - #define VDDEE_VAL_REG 0x120000 -#elif (VDDEE_VAL == 721) - #define VDDEE_VAL_REG 0x110001 -#elif (VDDEE_VAL == 731) - #define VDDEE_VAL_REG 0x100002 -#elif (VDDEE_VAL == 741) - #define VDDEE_VAL_REG 0xf0003 -#elif (VDDEE_VAL == 751) - #define VDDEE_VAL_REG 0xe0004 -#elif (VDDEE_VAL == 761) - #define VDDEE_VAL_REG 0xd0005 -#elif (VDDEE_VAL == 771) - #define VDDEE_VAL_REG 0xc0006 -#elif (VDDEE_VAL == 781) - #define VDDEE_VAL_REG 0xb0007 -#elif (VDDEE_VAL == 791) - #define VDDEE_VAL_REG 0xa0008 -#elif (VDDEE_VAL == 801) - #define VDDEE_VAL_REG 0x90009 -#elif (VDDEE_VAL == 811) - #define VDDEE_VAL_REG 0x8000a -#elif (VDDEE_VAL == 821) - #define VDDEE_VAL_REG 0x7000b -#elif (VDDEE_VAL == 831) - #define VDDEE_VAL_REG 0x6000c -#elif (VDDEE_VAL == 841) - #define VDDEE_VAL_REG 0x5000d -#elif (VDDEE_VAL == 851) - #define VDDEE_VAL_REG 0x4000e -#elif (VDDEE_VAL == 861) - #define VDDEE_VAL_REG 0x3000f -#elif (VDDEE_VAL == 871) - #define VDDEE_VAL_REG 0x20010 -#elif (VDDEE_VAL == 881) - #define VDDEE_VAL_REG 0x10011 -#elif (VDDEE_VAL == 891) - #define VDDEE_VAL_REG 0x12 -#else - #error "VDDEE val out of range\n" -#endif -#endif - -/* for PWM use */ -/* - * GPIOE_0 PWM_A VDDEE_PWM - * - * GPIOE_1 PWM_B VCCK_PWM - */ -/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */ -#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400) -#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400) - -/* pwm clock and pwm controller */ -#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800) -#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400) -#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400) -#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400) - -bl2_reg_t __bl2_reg[] = { -#ifdef CONFIG_I2C_REGULATOR - /* demo, user defined override register */ - {0, 0, 0xffffffff, 0, 0, 0}, - {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, - {PWMAB_MISC_REG_AB, 0x1 << 1, 0x1 << 1, 0, BL2_INIT_STAGE_1, 0}, - /* Set GPIOA_5 low */ - {PADCTRL_GPIOA_O, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_GPIOA_OEN, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, - /* Set GPIOD_10 low */ - {PADCTRL_GPIOD_O, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, - /* Set GPIOX_11 low */ - {PADCTRL_GPIOX_O, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_GPIOX_OEN, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, - /* set pwm A and pwm B clock rate to 24M, enable them */ - {CLKTREE_PWM_CLK_AB_CTRL, 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, - /* set GPIOE_0 GPIOE_1 drive strength to 3*/ - {PADCTRL_GPIOE_DS, 0x3 << 2, 0x3 << 2, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, -#ifdef CONFIG_PDVFS_ENABLE - /* table_id, ee_voltage, ...... */ - {1, 0x11, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, - {2, 0x14, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, - {3, 0x16, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, -#else - {0x0, VDDEE_VAL_REG, 0x0, 0, BL2_INIT_STAGE_I2C_REGULATOR, 0}, -#endif -#else - /* demo, user defined override register */ - {0, 0, 0xffffffff, 0, 0, 0}, -#ifdef CONFIG_PDVFS_ENABLE - {PWMAB_PWM_A, 0x000c0006, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, - {PWMAB_PWM_A, 0x00090009, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, - {PWMAB_PWM_A, 0x0007000b, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, -#else - {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, -#endif - {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, - {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0}, - /* enable vddcpu dc-dc, set GPIOD_10 high */ - {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, - /* set pwm A and pwm B clock rate to 24M, enable them */ - {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, - /* set GPIOE_0 GPIOE_1 drive strength to 3*/ - {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, -#endif -};
diff --git a/board/amlogic/c2_bla4_p2/Kconfig b/board/amlogic/c2_bla4_p2/Kconfig deleted file mode 100644 index bbdcb05..0000000 --- a/board/amlogic/c2_bla4_p2/Kconfig +++ /dev/null
@@ -1,37 +0,0 @@ -if TARGET_C2_BLA4_P2 - -config SYS_SOC - default "c2" - -config SYS_BOARD - default "c2_bla4_p2" - -config SYS_VENDOR - default "amlogic" - -config SYS_CONFIG_NAME - default "c2_bla4_p2" - -config DTB_BIND_KERNEL - bool "load dtb from boot part but not flash rsv" - default n - -config CMD_PLLTEST - bool "support plltest command" - default y - help - support plltest command - -config I2C_REGULATOR - bool "use i2c regulator to configure vddee" - default n - -config DDR_WINDOWING_BOOT - bool "enable/disable ddr windowing boot" - default n - -config LED_AW2026 - bool "enable/disable AW2026 LED" - default y - -endif
diff --git a/board/amlogic/c2_bla4_p2/Makefile b/board/amlogic/c2_bla4_p2/Makefile deleted file mode 100644 index 0403c0c..0000000 --- a/board/amlogic/c2_bla4_p2/Makefile +++ /dev/null
@@ -1 +0,0 @@ -obj-y += $(BOARD).o
diff --git a/board/amlogic/c2_bla4_p2/aml-user-key.sig b/board/amlogic/c2_bla4_p2/aml-user-key.sig deleted file mode 100644 index 0f89a75..0000000 --- a/board/amlogic/c2_bla4_p2/aml-user-key.sig +++ /dev/null Binary files differ
diff --git a/board/amlogic/c2_bla4_p2/c2_bla4_p2.c b/board/amlogic/c2_bla4_p2/c2_bla4_p2.c deleted file mode 100644 index bb85c68..0000000 --- a/board/amlogic/c2_bla4_p2/c2_bla4_p2.c +++ /dev/null
@@ -1,319 +0,0 @@ - -/* - * Copyright (C) 2015 Amlogic, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -*/ - -#include <common.h> -#include <asm/io.h> -#include <malloc.h> -#include <errno.h> -#include <environment.h> -#include <fdt_support.h> -#include <linux/libfdt.h> -#include <amlogic/cpu_id.h> -#include <asm/arch/secure_apb.h> -#include <asm/arch/pinctrl_init.h> -#include <linux/sizes.h> -#include <asm-generic/gpio.h> -#include <dm.h> -#include <asm/armv8/mmu.h> -#include <amlogic/aml_v3_burning.h> -#include <amlogic/aml_v2_burning.h> -#include <amlogic/leds-aw2026.h> -#include <linux/mtd/partitions.h> -#include <linux/ssr/ps13216.h> - -DECLARE_GLOBAL_DATA_PTR; - -int serial_set_pin_port(unsigned long port_base) -{ - return 0; -} - -int dram_init(void) -{ - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -unsigned int get_dram_size(void) -{ - // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 -#if defined(CONFIG_SYS_MEM_TOP_HIDE) - return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; -#else - return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); -#endif /* CONFIG_SYS_MEM_TOP_HIDE */ -} - - -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = get_dram_size(); - return 0; -} - -/* secondary_boot_func - * this function should be write with asm, here, is is only for compiling pass - * */ -void secondary_boot_func(void) -{ -} - -int board_eth_init(bd_t *bis) -{ - return 0; -} - -int active_clk(void) -{ - struct udevice *clk = NULL; - int err; - - err = uclass_get_device_by_name(UCLASS_CLK, - "xtal-clk", &clk); - if (err) { - pr_err("Can't find xtal-clk clock (%d)\n", err); - return err; - } - err = uclass_get_device_by_name(UCLASS_CLK, - "clock-controller@0", &clk); - if (err) { - pr_err("Can't find clock-controller@0 clock (%d)\n", err); - return err; - } - - return 0; -} - -void board_init_mem(void) { - /* config bootm low size, make sure whole dram/psram space can be used */ - phys_size_t ram_size; - char *env_tmp; - env_tmp = env_get("bootm_size"); - if (!env_tmp) { - ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); - env_set_hex("bootm_low", 0); - env_set_hex("bootm_size", ram_size); - } -} - -int board_init(void) -{ - unsigned int value; - - printf("board init\n"); - - /* set GPIOB_3 to low before emmc init */ - value = readl(PADCTRL_PIN_MUX_REG3); - /* set to gpio pin */ - writel(value & ~(0xf << 12), PADCTRL_PIN_MUX_REG3); - value = readl(PADCTRL_GPIOB_OEN); - /* enable gpio output */ - writel(value & ~(0x1 << 3), PADCTRL_GPIOB_OEN); - value = readl(PADCTRL_GPIOB_O); - /* set output value to low */ - writel(value & ~(0x1 << 3), PADCTRL_GPIOB_O); - udelay(20000); - - //Please keep try usb boot first in board_init, as other init before usb may cause burning failure -#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) - if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2))) - { aml_v3_factory_usb_burning(0, gd->bd); } -#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) - - pinctrl_devices_active(PIN_CONTROLLER_NUM); - active_clk(); - - // set to white by default - sys_led_init(WHITE); - return 0; -} - -int board_late_init(void) -{ - board_init_mem(); - -#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard - aml_try_factory_sdcard_burning(0, gd->bd); -#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE - //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003' -#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) - if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2)) - { aml_v3_factory_usb_burning(0, gd->bd); } -#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) - - return 0; -} - - -phys_size_t get_effective_memsize(void) -{ -#ifdef UBOOT_RUN_IN_SRAM - return 0x180000; /* SRAM 1.5MB */ -#else - // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 -#if defined(CONFIG_SYS_MEM_TOP_HIDE) - return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; -#else - return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); -#endif /* CONFIG_SYS_MEM_TOP_HIDE */ -#endif /* UBOOT_RUN_IN_SRAM */ -} - -static struct mm_region bd_mem_map[] = { - { - .virt = 0x00000000UL, - .phys = 0x00000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = bd_mem_map; - -int mach_cpu_init(void) { - printf("\nmach_cpu_init\n"); - return 0; -} - -int ft_board_setup(void *blob, bd_t *bd) -{ - /* eg: bl31/32 rsv */ - return 0; -} - -int do_get_hw_id(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) -{ - unsigned int hw_bid = 0, hw_cid = 0, ret = 0; - char hw_id_str[8] = {0}; // eg: 0x0A - - /* - * HW_BID_2 : GPIOD_8 - * HW_BID_1 : GPIOD_5 - * HW_BID_0 : GPIOD_4 - * HW_CID_2 : GPIOX_10 - * HW_CID_1 : GPIOX_9 - * HW_CID_0 : GPIOX_8 - * - */ - /* disable gpio pull */ - ret = readl(PADCTRL_GPIOD_PULL_EN); - writel(ret & (~(0x13 << 4)), PADCTRL_GPIOD_PULL_EN); - ret = readl(PADCTRL_GPIOX_PULL_EN); - writel(ret & (~(0x7 << 8)), PADCTRL_GPIOX_PULL_EN); - - /* pin mux to gpio pin */ - /* GPIOD_4, GPIOD_5 */ - ret = readl(PADCTRL_PIN_MUX_REG0); - writel(ret & (~(0xFF << 16)), PADCTRL_PIN_MUX_REG0); - /* GPIOD_8 */ - ret = readl(PADCTRL_PIN_MUX_REG1); - writel(ret & (~(0xF << 0)), PADCTRL_PIN_MUX_REG1); - /* GPIOX_8, GPIOX_9, GPIOX_10 */ - ret = readl(PADCTRL_PIN_MUX_REG7); - writel(ret & (~(0xFFF << 0)), PADCTRL_PIN_MUX_REG7); - - /* enable input */ - ret = readl(PADCTRL_GPIOD_OEN); - writel(ret | (0x13 << 4), PADCTRL_GPIOD_OEN); - ret = readl(PADCTRL_GPIOX_OEN); - writel(ret | (0x7 << 8), PADCTRL_GPIOX_OEN); - - /* read hw id */ - ret = readl(PADCTRL_GPIOD_I); - hw_bid = (ret >> 4) & 0x3; - hw_bid |= (ret >> 6) & 0x4; - ret = readl(PADCTRL_GPIOX_I); - hw_cid = (ret >> 8) & 0x7; - - if (BLA4_HW_CID != hw_cid) { - pr_err("The image doesn't match the device(CID=0x%x)\n", hw_cid); - sys_led_init(YELLOW); - while(1); - } - - ret = (hw_cid << 0x3) | hw_bid; - snprintf(hw_id_str, sizeof(hw_id_str), "0x%02x", ret); - env_set("hw_id", hw_id_str); - return 0; -} - -U_BOOT_CMD( - get_hw_id, 1, 0, do_get_hw_id, "get HW_ID and env_set 'hw_id'\n", "get_hw_id" -); - -/* partition table */ -/* partition table for spinand flash */ -#ifdef CONFIG_SPI_NAND -static const struct mtd_partition spinand_partitions[] = { - { - .name = "logo", - .offset = 0, - .size = 2 * SZ_1M, - }, - { - .name = "recovery", - .offset = 0, - .size = 16 * SZ_1M, - }, - { - .name = "boot", - .offset = 0, - .size = 16 * SZ_1M, - }, - { - .name = "system", - .offset = 0, - .size = 64 * SZ_1M, - }, - /* last partition get the rest capacity */ - { - .name = "data", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - } -}; -struct mtd_partition *get_partition_table(int *partitions) -{ - *partitions = ARRAY_SIZE(spinand_partitions); - return spinand_partitions; -} -#endif /* CONFIG_SPI_NAND */ - -int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;} - -int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;} - -void __attribute__((weak)) set_working_fdt_addr(ulong addr) {} - -int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;} - -void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c2_bla4_p2/firmware/timing.c b/board/amlogic/c2_bla4_p2/firmware/timing.c deleted file mode 100755 index dfaec2e..0000000 --- a/board/amlogic/c2_bla4_p2/firmware/timing.c +++ /dev/null
@@ -1,1457 +0,0 @@ -/* - * board/amlogic/c2_bla4_p2/firmware/timing.c - * - * Copyright (C) 2015 Amlogic, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -*/ - -#include <asm/arch/secure_apb.h> -#include <asm/arch/timing.h> -#include <asm/arch/ddr_define.h> - -/* board clk defines */ -#define CPU_CLK 1512 -#define TIMMING_MAX_CONFIG 1 -#define ENABLE_DDR3 0 -#define ENABLE_DDR4 1 -#define ENABLE_LPDDR4 0 - -ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = { -#if ENABLE_DDR4 -{ - .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, - .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4, - .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, - .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096 - .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, - .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, - .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, - .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, - .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT, - .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)}, - .cfg_board_common_setting. fast_boot[0] = 0x1, - .cfg_board_common_setting. fast_boot[3] = 0x46, - - //DDR frequercy 1 - .cfg_board_SI_setting_ps[0].DRAMFreq = 1272,//1320,1200,1104,1008,912,792 - .cfg_board_SI_setting_ps[0].PllBypassEn = 0, - .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_48_OHM, - .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, - .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[0].reserve2 = 0, - .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, - .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, - .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, - .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, - .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { - 128,128,128-20,128,128,128,128,128, - 384,384,384,384,384,384,384,384, - 384,384,384,384,384,384,384,384, - 384,384,384,384,384,384,384,384, - 384,384,384,384, - },//total 36 - - .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { - 128,128,128-20,128,128,128,128,128, - 384,384,384,384,384,384,384,384, - 384,384,384,384,384,384,384,384, - 384,384,384,384,384,384,384,384, - 384,384,384,384, - },//total 36 - - .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x0000005f,// 95 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000073,// 115 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x0000005f,// 95 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000087,// 135 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000080,// 128 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000080,// 128 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000080,// 128 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000080,// 128 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000009f,// 159 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000095,// 149 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000092,// 146 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x0000009f,// 159 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000bb,// 187 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000cd,// 205 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000b1,// 177 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000c5,// 197 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000ad,// 173 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000000a1,// 161 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000d3,// 211 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000000a2,// 162 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000d1,// 209 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000000d3,// 211 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000d0,// 208 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000000a7,// 167 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000a9,// 169 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000000b9,// 185 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000000ae,// 174 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000b1,// 177 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000b2,// 178 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000bd,// 189 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000000d1,// 209 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000d0,// 208 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000c6,// 198 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000d1,// 209 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000bf,// 191 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000000c1,// 193 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000d3,// 211 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000000c1,// 193 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000dc,// 220 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000000ae,// 174 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000a1,// 161 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000ab,// 171 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000ac,// 172 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000bd,// 189 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000037a,// 890 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000359,// 857 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000352,// 850 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x0000034f,// 847 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000075,// 117 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x0000006c,// 108 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000058,// 88 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007c,// 124 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000034,// 52 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000033,// 51 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000002b,// 43 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000032,// 50 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000050,// 80 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000062,// 98 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000043,// 67 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000058,// 88 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000028,// 40 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000028,// 40 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000036,// 54 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000044,// 68 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x00000042,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000026,// 38 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000002c,// 44 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x0000002a,// 42 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x00000032,// 50 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000029,// 41 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x0000002c,// 44 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000048,// 72 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000003e,// 62 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x0000003b,// 59 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x0000003b,// 59 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000050,// 80 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003d,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x00000030,// 48 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x0000002e,// 46 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000002f,// 47 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000033,// 51 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0 - - .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { - 0,40,40,40,40,40,40,40,40,40,40, - 40,40,40,40,40,40,40,40,40,40,40, - 40,40,40,40,40,40,40,40,40,40,40, - 40,40,40,40,50,40,50,40,50,40,50},//total 44 - .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { - 0,32,32,32,32,32,32,32,32,32,32, - 32,32,32,32,32,32,32,32,32,32,32, - 32,32,32,32,32,32,32,32,32,32,32, - 32,32,32},//total 36 - .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { - (0 << 7) | 6, (0 << 7) | 6, (1 << 7) | 5, (0 << 7) | 0, - (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, - (1 << 7) | 10, (1 << 7) | 10, (1 << 7) | 10, (1 << 7) | 10, - (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, - }, - - //pinmux setting - .cfg_board_common_setting. ac_pinmux = { - 0, 0, 0, 1, 2, 3, - 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, - }, - .cfg_board_common_setting. ddr_dqs_swap = 0, - - .cfg_board_common_setting. ddr_dq_remap = { - 0,1,2,3,4,5,6,7, - 8,9,10,11,12,13,14,15, - 16,17,18,19,20,21,22,23, - 24,25,26,27,28,29,30,31, - 32,33,34,35 - },//d0-d31 dm0 dm1 dm2 dm3 - - .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start - .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), - .cfg_board_common_setting. timming_struct_version = 0, - .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), - .cfg_board_common_setting. timming_struct_real_size = 0, //0 - .cfg_board_common_setting. ddr_func = 0, - .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, - .cfg_board_common_setting. dram_cs0_base_add = 0, - .cfg_board_common_setting. dram_cs1_base_add = 0, - - .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE, - .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, - .cfg_board_common_setting. org_tdqs2dq = 0, - .cfg_board_common_setting. reserve1_test_function = {0}, - .cfg_board_common_setting. ddr_vddee_setting = {0}, - - //DDR frequercy 2 - .cfg_board_SI_setting_ps[1].DRAMFreq = 600, - .cfg_board_SI_setting_ps[1].PllBypassEn = 0, - .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, - .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, - .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[1].reserve2 = 0, - .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, - .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, - .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, - .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, - .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { - 128,128,128,128,128,128,128,128, - 128,128,128,128,128,128,128,128, - 128,128,128,128,128,128,128,128, - 128,128,128,128,128,128,128,128, - 128,128,128,128, - },//total 36 - - .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { - 128,128,128,128,128,128,128,128, - 128,128,128,128,128,128,128,128, - 128,128,128,128,128,128,128,128, - 128,128,128,128,128,128,128,128, - 128,128,128,128, - },//total 36 - .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, - //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, - .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50,}, - - //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 - .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 - //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 - .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 - .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0},//total 72 - .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { - 40,40,40,40,40,40,40,40,40,40,40, - 40,40,40,40,40,40,40,40,40,40,40, - 40,40,40,40,40,40,40,40,40,40,40, - 40,40,40,40,40,40,40,40,40,40,40},//total 44 - .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { - 32,32,32,32,32,32,32,32,32,32,32, - 32,32,32,32,32,32,32,32,32,32,32, - 32,32,32,32,32,32,32,32,32,32,32, - 32,32,32},//total 36 - - .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end -}, -#endif //end ENABLE_DDR4 -#if ENABLE_DDR3 -{ - .cfg_board_common_setting.timming_magic = 0, - .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, - .cfg_board_common_setting.timming_struct_version = 0, - .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), - .cfg_board_common_setting.timming_struct_real_size = 0, //0 - .cfg_board_common_setting.fast_boot = {0}, - .cfg_board_common_setting.ddr_func = 0, - .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, - .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR3, - .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0, - .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, - .cfg_board_common_setting.dram_cs0_base_add = 0, - .cfg_board_common_setting.dram_cs1_base_add = 0, - .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB, - .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, - .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, - .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE, - .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, - .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, - .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, - .cfg_board_common_setting.org_tdqs2dq = 0, - .cfg_board_common_setting.reserve1_test_function = {0}, - .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT, - .cfg_board_common_setting.ac_pinmux = - { - 0, 0, 0, 1, 2, 3, 0, 1, - 2, 3, 4, 5, 6, 7, 8, 9, - 10, 11, 12, 13, 14, 15, 0, 0, - 0, 0, 20, 21, 22, 0, 0, 25, - 26, 27, 0 - }, - .cfg_board_common_setting.ddr_dqs_swap = 0, - .cfg_board_common_setting.ddr_dq_remap = { - 0, 1, 2, 3, 4, 5, 6, 7, - 8, 9, 10, 11, 12, 13, 14, 15, - 16, 17, 18, 19, 20, 21, 22, 23, - 24, 25, 26, 27, 28, 29, 30, 31, - 32, 33, 34, 35, - }, //d0-d31 dm0 dm1 dm2 dm3 - .cfg_board_common_setting.ddr_vddee_setting = {0}, - .cfg_board_SI_setting_ps[0].DRAMFreq = 912, - .cfg_board_SI_setting_ps[0].PllBypassEn = 0, - .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM, - .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[0].reserve2 = 0, - .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, - .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, - .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, - .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, - .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { - 128, 128, 128 - 20, 128, 128, 128, 128, 128, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, - }, //total 36 - - .cfg_ddr_training_delay_ps[0].ac_trace_delay = { - 128, 128, 128 - 20, 128, 128, 128, 128, 128, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, - }, //total 36 - .cfg_ddr_training_delay_ps[0].write_dqs_delay = { - 128 - 1, 128 - 1, 128 + 48, 128 + 58, 128 + 32, 128 + 32, 128 + 32, 128 + 32 - }, - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay = { - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, - 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, - 128 + 128, 128 + 128, 128 + 128, 128 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - }, - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay = { - 896, 896, 896, 896, 896, 896, 896, 896 - }, //total 8 - .cfg_ddr_training_delay_ps[0].read_dqs_delay = { - 64, 64, 50, 40, 64, 64, 64, 64 - }, //total 8 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay = { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 - }, //total 72 - .cfg_ddr_training_delay_ps[0].soc_bit_vref = { - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32 + 5, 32, 32 + 5, - 32, 32 + 5, 32, 32 + 5 - }, - .cfg_ddr_training_delay_ps[0].dram_bit_vref = { - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32 - }, //total 36 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[0] = 0x0000007d,// 125 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[1] = 0x00000091,// 145 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[2] = 0x00000091,// 145 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[3] = 0x0000009b,// 155 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[4] = 0x000000a0,// 160 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[5] = 0x000000a0,// 160 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[6] = 0x000000a0,// 160 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[7] = 0x000000a0,// 160 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0] = 0x000000c2,// 194 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1] = 0x000000b0,// 176 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2] = 0x000000af,// 175 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3] = 0x000000b0,// 176 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4] = 0x000000c0,// 192 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5] = 0x000000c3,// 195 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6] = 0x000000b4,// 180 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7] = 0x000000be,// 190 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8] = 0x000000ba,// 186 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9] = 0x000000c1,// 193 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10] = 0x000000d5,// 213 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11] = 0x000000c1,// 193 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12] = 0x000000d0,// 208 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13] = 0x000000cc,// 204 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14] = 0x000000c3,// 195 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15] = 0x000000be,// 190 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16] = 0x000000c0,// 192 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17] = 0x000000c8,// 200 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18] = 0x000000e0,// 224 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19] = 0x000000e5,// 229 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20] = 0x000000e2,// 226 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21] = 0x000000ec,// 236 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22] = 0x000000ec,// 236 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23] = 0x000000e7,// 231 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24] = 0x000000e4,// 228 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25] = 0x000000e9,// 233 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26] = 0x000000e6,// 230 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27] = 0x000000eb,// 235 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28] = 0x000000f5,// 245 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29] = 0x000000e7,// 231 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30] = 0x000000fd,// 253 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31] = 0x000000e8,// 232 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32] = 0x000000e4,// 228 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33] = 0x000000ee,// 238 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34] = 0x000000ec,// 236 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35] = 0x000000f2,// 242 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0] = 0x0000038c,// 908 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1] = 0x0000037a,// 890 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2] = 0x0000039a,// 922 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3] = 0x00000395,// 917 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[0] = 0x0000007f-0x30,// 127 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[1] = 0x0000007d-0x30,// 125 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[2] = 0x0000006d-0x30,// 109 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[3] = 0x0000006f-0x30,// 111 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[4] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[5] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[6] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[7] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0] = 0x00000048-0x30,// 72 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1] = 0x00000044-0x30,// 68 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2] = 0x00000038-0x30,// 56 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3] = 0x0000003b-0x30,// 59 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4] = 0x00000049-0x30,// 73 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5] = 0x0000004b-0x30,// 75 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6] = 0x0000003b-0x30,// 59 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7] = 0x00000049-0x30,// 73 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9] = 0x00000040-0x30,// 64 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10] = 0x00000052-0x30,// 82 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11] = 0x00000039-0x30,// 57 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12] = 0x00000040-0x30,// 64 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13] = 0x00000045-0x30,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14] = 0x00000042-0x30,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15] = 0x00000034-0x30,// 52 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16] = 0x0000003c-0x30,// 60 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17] = 0x00000086-0x30,// 134 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18] = 0x0000003f-0x30,// 63 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19] = 0x00000048-0x30,// 72 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20] = 0x00000037-0x30,// 55 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21] = 0x00000048-0x30,// 72 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22] = (0x0000004e)-0x30,// 78 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23] = 0x00000044-0x30,// 68 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24] = 0x00000042-0x30,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25] = 0x00000047-0x30,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26] = 0x0000007f-0x30,// 127 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27] = 0x00000040-0x30,// 64 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28] = 0x00000052-0x30,// 82 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29] = 0x0000003d-0x30,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30] = (0x0000004e)-0x30,// 78 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31] = 0x0000003c-0x30,// 60 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32] = (0x0000003e)-0x30,// 62 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33] = 0x0000003f-0x30,// 63 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34] = 0x0000004c-0x30,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35] = 0x00000091-0x30,// 145 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71] = 0x00000000,// 0 - - .cfg_ddr_training_delay_ps[0].reserve_training_parameter = {0}, - .cfg_board_SI_setting_ps[1].DRAMFreq = 667, - .cfg_board_SI_setting_ps[1].PllBypassEn = 0, - .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, - .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, - .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[1].reserve2 = 0, - .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, - .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, - .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, - .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, - .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, - }, //total 36 - .cfg_ddr_training_delay_ps[1].ac_trace_delay = { - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, - }, //total 36 - .cfg_ddr_training_delay_ps[1].write_dqs_delay = { - 0, 0, 0, 0, 0, 0, 0, 0 - }, - .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50 - }, - .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { - 192, 192, 192, 192, 192, 192, 192, 192 - }, //total 8 - .cfg_ddr_training_delay_ps[1].read_dqs_delay = { - 64, 64, 64, 64, 64, 64, 64, 64 - }, //total 8 - .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 - }, //total 72 - .cfg_ddr_training_delay_ps[1].soc_bit_vref = { - 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40 - }, //total 44 - .cfg_ddr_training_delay_ps[1].dram_bit_vref = { - 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32 - }, //total 36 - .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0}, -}, -#endif - -#if ENABLE_LPDDR4 //LPDDR4 rank0,timing_config -{ - .cfg_board_common_setting.timming_magic = 0, - .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, - .cfg_board_common_setting.timming_struct_version = 0, - .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), - .cfg_board_common_setting.timming_struct_real_size = 0, //0 - .cfg_board_common_setting.fast_boot = { 0 }, - .cfg_board_common_setting.ddr_func = 0, - .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, - .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_LPDDR4, - .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH01, - .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, - .cfg_board_common_setting.dram_cs0_base_add = 0, - .cfg_board_common_setting.dram_cs1_base_add = 0, - .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB, - .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, - .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, - .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_1T_MODE, - .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, - .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, //DDR_WRITE_READ_DBI_DISABLE , - .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, - .cfg_board_common_setting.org_tdqs2dq = 0, - .cfg_board_common_setting.reserve1_test_function = { 0 }, - .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT, -#ifdef CONFIG_DDR_WINDOWING_BOOT - .cfg_board_common_setting.fast_boot[0] = 0x1, - .cfg_board_common_setting.fast_boot[3] = 0x46, -#endif - //lpddr4 ac pinmux - .cfg_board_common_setting.ac_pinmux = { - 0, 0, 0, 1, 0, 1, 1, 3, - 0, 4, 4, 2, 0, 0, 1, 0, - 2, 0, 0, 0, 0, 3, 0, 0, - 0, 0, 5, 5, 0, 0, 0, 0, - 0, 0, - }, - .cfg_board_common_setting.ddr_dqs_swap = 0, - - .cfg_board_common_setting.ddr_dq_remap = { - 1, 0, 3, 2, 7, 5, 6, 4, - 9, 15, 13, 14, 10, 11, 12, 8, - 21, 19, 20, 18, 17, 16, 22, 23, - 25, 26, 24, 27, 31, 29, 30, 28, - 32, 33, 34, 35 - }, //d0-d31 dm0 dm1 dm2 dm3 - - .cfg_board_common_setting.ddr_vddee_setting = { 0 }, - .cfg_board_SI_setting_ps[0].DRAMFreq = 1320, - .cfg_board_SI_setting_ps[0].PllBypassEn = 0, - .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_60_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_LPDDR4_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_LPDDR4_ODT_60_OHM, - .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_LPDDR4_AC_ODT_80_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[0].reserve2 = 0, - .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, //3000/11, - .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, //170, - .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, //280, //330 - .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 }, - .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { - 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 0 + 128, //0,0,0,0,0,0,0,0, - 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128, 128 + 20 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - }, //total 36 - - .cfg_ddr_training_delay_ps[0].ac_trace_delay = { - 64 + 128, 64 + 128, 64 + 128-64, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 128 + 128, //0,0,0,0,0,0,0,0, - 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128-40, 128 + 20 + 128-10, 128 + 0 + 128, 128 + 0 + 128+10, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - }, //total 36 - .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 }, - - .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x000000af,// 175 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x000000cd,// 205 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x000000aa,// 170 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x000000cd,// 205 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x000000af,// 175 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x000000cd,// 205 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x000000aa,// 170 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x000000cd,// 205 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x000001cd,// 461 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x000001cc,// 460 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x000001ba,// 442 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000001d8,// 472 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000001e1,// 481 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000001ce,// 462 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000001c6,// 454 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000001d0,// 464 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000001cc,// 460 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000001d9,// 473 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000001da,// 474 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000001c4,// 452 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000001d5,// 469 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000001ea,// 490 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000001e9,// 489 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000001e2,// 482 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000001ea,// 490 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000001d5,// 469 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000001c6,// 454 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000001ce,// 462 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000001b5,// 437 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000001c7,// 455 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000001d3,// 467 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000001d1,// 465 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000001c4,// 452 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000001eb,// 491 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000001d1,// 465 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000001f7,// 503 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000001d8,// 472 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000001cf,// 463 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000001d3,// 467 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000001c9,// 457 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000001de,// 478 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x000001cd,// 461 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x000001cc,// 460 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x000001ba,// 442 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x000001d8,// 472 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x000001e1,// 481 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x000001ce,// 462 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x000001c6,// 454 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x000001d0,// 464 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x000001cc,// 460 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x000001d9,// 473 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x000001da,// 474 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x000001c4,// 452 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x000001d5,// 469 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x000001ea,// 490 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x000001e9,// 489 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x000001e2,// 482 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x000001ea,// 490 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x000001d5,// 469 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x000001c6,// 454 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x000001ce,// 462 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x000001b5,// 437 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x000001c7,// 455 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x000001d3,// 467 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x000001d1,// 465 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x000001c4,// 452 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x000001eb,// 491 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x000001d1,// 465 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x000001f7,// 503 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x000001d8,// 472 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x000001cf,// 463 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x000001d3,// 467 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x000001c9,// 457 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x000001de,// 478 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x000003ab,// 939 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000383,// 899 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000395,// 917 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x00000378,// 888 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x000003ab,// 939 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000383,// 899 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000395,// 917 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000378,// 888 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x0000007e,// 126 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x00000088,// 136 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000070,// 112 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007a,// 122 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x0000007e,// 126 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000088,// 136 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000070,// 112 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x0000007a,// 122 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000044,// 68 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000051,// 81 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x00000036,// 54 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000054,// 84 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x0000003d,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000045,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000051,// 81 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000037,// 55 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x0000003d,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000052,// 82 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x0000005b,// 91 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x0000004c,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000005a,// 90 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x0000004b,// 75 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000042,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x0000004f,// 79 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000030,// 48 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000042,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000004c,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000041,// 65 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000058,// 88 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000045,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000041,// 65 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000056,// 86 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003f,// 63 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000055,// 85 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x0000003e,// 62 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000034,// 52 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x00000031,// 49 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000036,// 54 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000040,// 64 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000044,// 68 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000051,// 81 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000036,// 54 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000054,// 84 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x0000003d,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000045,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000051,// 81 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000037,// 55 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x0000003d,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000052,// 82 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x0000005b,// 91 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x0000004c,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x0000005a,// 90 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x0000004b,// 75 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000042,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x0000004f,// 79 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000030,// 48 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000042,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x0000004c,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000041,// 65 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000058,// 88 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000045,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000041,// 65 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000056,// 86 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x0000003f,// 63 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000055,// 85 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x0000003e,// 62 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000034,// 52 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000031,// 49 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000036,// 54 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000040,// 64 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[0]=0,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[1]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[2]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[3]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[4]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[5]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[6]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[7]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[8]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[9]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[10]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[11]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[12]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[13]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[14]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[15]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[16]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[17]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[18]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[19]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[20]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[21]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[22]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[23]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[24]=0x00000016,// 22 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[25]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[26]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[27]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[28]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[29]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[30]=0x00000016,// 22 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[31]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[32]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[33]=0x00000016,// 22 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[34]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[35]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[36]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[37]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[38]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[39]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[40]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[41]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[42]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[43]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[0]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[1]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[2]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[3]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[4]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[5]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[6]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[7]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[8]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[9]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[10]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[11]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[12]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[13]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[14]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[15]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[16]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[17]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[18]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[19]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[20]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[21]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[22]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[23]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[24]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[25]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[26]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[27]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[28]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[29]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[30]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[31]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[32]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[33]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[34]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[35]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { - (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, - (1 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, - (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, - (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, - }, - .cfg_board_SI_setting_ps[1].DRAMFreq = 667, - .cfg_board_SI_setting_ps[1].PllBypassEn = 0, - .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, - .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, - .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[1].reserve2 = 0, - .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, - .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, - .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, - .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 }, - .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, - }, //total 36 - .cfg_ddr_training_delay_ps[1].ac_trace_delay = { - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, - }, //total 36 - - .cfg_ddr_training_delay_ps[1].write_dqs_delay = { - 0, 0, 0, 0, 0, 0, 0, 0 - }, - .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - }, - .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { - 192, 192, 192, 192, 192, 192, 192, 192 - }, //total 8 - .cfg_ddr_training_delay_ps[1].read_dqs_delay = { - 64, 64, 64, 64, 64, 64, 64, 64 - }, //total 8 - .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 - }, //total 72 - .cfg_ddr_training_delay_ps[1].soc_bit_vref = { - 0, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40 - }, //total 44 - .cfg_ddr_training_delay_ps[1].dram_bit_vref = { - 0, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32 - }, //total 36 - .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 }, -}, -#endif -}; -//ddr timing end - -pll_set_t __pll_setting = { - .cpu_clk = CPU_CLK / 24 * 24, -#ifdef CONFIG_PXP_EMULATOR - .pxp = 1, -#else - .pxp = 0, -#endif - .spi_ctrl = 0, - .lCustomerID = AML_CUSTOMER_ID, - .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */ - .log_ctrl = (1 << 7) | /* (1<<7), print bl2 log into buffer */ -#ifdef CONFIG_SILENT_CONSOLE - (1<<6), /* do not print log buffer */ -#else - (0<<6), /* print log buffer before run bl31 */ -#endif - .ddr_timming_save_mode = 1, -}; - -ddr_reg_t __ddr_reg[] = { - /* demo, user defined override register */ - {0xaabbccdd, 0, 0, 0, 0, 0}, - {0x11223344, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0}, -}; - - - -#define VCCK_VAL AML_VCCK_INIT_VOLTAGE -#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE -/* VCCK PWM table */ -#if (VCCK_VAL == 1039) - #define VCCK_VAL_REG 0x00000022 -#elif (VCCK_VAL == 1029) - #define VCCK_VAL_REG 0x00010021 -#elif (VCCK_VAL == 1019) - #define VCCK_VAL_REG 0x00020020 -#elif (VCCK_VAL == 1009) - #define VCCK_VAL_REG 0x0003001f -#elif (VCCK_VAL == 999) - #define VCCK_VAL_REG 0x0004001e -#elif (VCCK_VAL == 989) - #define VCCK_VAL_REG 0x0005001d -#elif (VCCK_VAL == 979) - #define VCCK_VAL_REG 0x0006001c -#elif (VCCK_VAL == 969) - #define VCCK_VAL_REG 0x0007001b -#elif (VCCK_VAL == 959) - #define VCCK_VAL_REG 0x0008001a -#elif (VCCK_VAL == 949) - #define VCCK_VAL_REG 0x00090019 -#elif (VCCK_VAL == 939) - #define VCCK_VAL_REG 0x000a0018 -#elif (VCCK_VAL == 929) - #define VCCK_VAL_REG 0x000b0017 -#elif (VCCK_VAL == 919) - #define VCCK_VAL_REG 0x000c0016 -#elif (VCCK_VAL == 909) - #define VCCK_VAL_REG 0x000d0015 -#elif (VCCK_VAL == 899) - #define VCCK_VAL_REG 0x000e0014 -#elif (VCCK_VAL == 889) - #define VCCK_VAL_REG 0x000f0013 -#elif (VCCK_VAL == 879) - #define VCCK_VAL_REG 0x00100012 -#elif (VCCK_VAL == 869) - #define VCCK_VAL_REG 0x00110011 -#elif (VCCK_VAL == 859) - #define VCCK_VAL_REG 0x00120010 -#elif (VCCK_VAL == 849) - #define VCCK_VAL_REG 0x0013000f -#elif (VCCK_VAL == 839) - #define VCCK_VAL_REG 0x0014000e -#elif (VCCK_VAL == 829) - #define VCCK_VAL_REG 0x0015000d -#elif (VCCK_VAL == 819) - #define VCCK_VAL_REG 0x0016000c -#elif (VCCK_VAL == 809) - #define VCCK_VAL_REG 0x0017000b -#elif (VCCK_VAL == 799) - #define VCCK_VAL_REG 0x0018000a -#elif (VCCK_VAL == 789) - #define VCCK_VAL_REG 0x00190009 -#elif (VCCK_VAL == 779) - #define VCCK_VAL_REG 0x001a0008 -#elif (VCCK_VAL == 769) - #define VCCK_VAL_REG 0x001b0007 -#elif (VCCK_VAL == 759) - #define VCCK_VAL_REG 0x001c0006 -#elif (VCCK_VAL == 749) - #define VCCK_VAL_REG 0x001d0005 -#elif (VCCK_VAL == 739) - #define VCCK_VAL_REG 0x001e0004 -#elif (VCCK_VAL == 729) - #define VCCK_VAL_REG 0x001f0003 -#elif (VCCK_VAL == 719) - #define VCCK_VAL_REG 0x00200002 -#elif (VCCK_VAL == 709) - #define VCCK_VAL_REG 0x00210001 -#elif (VCCK_VAL == 699) - #define VCCK_VAL_REG 0x00220000 -#else - #error "VCCK val out of range\n" -#endif - -/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/ -#ifdef CONFIG_I2C_REGULATOR -#if (VDDEE_VAL == 711) - #define VDDEE_VAL_REG 0xb -#elif (VDDEE_VAL == 721) - #define VDDEE_VAL_REG 0xc -#elif (VDDEE_VAL == 731) - #define VDDEE_VAL_REG 0xd -#elif (VDDEE_VAL == 741) - #define VDDEE_VAL_REG 0xe -#elif (VDDEE_VAL == 751) - #define VDDEE_VAL_REG 0xf -#elif (VDDEE_VAL == 761) - #define VDDEE_VAL_REG 0x10 -#elif (VDDEE_VAL == 771) - #define VDDEE_VAL_REG 0x11 -#elif (VDDEE_VAL == 781) - #define VDDEE_VAL_REG 0x12 -#elif (VDDEE_VAL == 791) - #define VDDEE_VAL_REG 0x13 -#elif (VDDEE_VAL == 801) - #define VDDEE_VAL_REG 0x14 -#elif (VDDEE_VAL == 811) - #define VDDEE_VAL_REG 0x15 -#elif (VDDEE_VAL == 821) - #define VDDEE_VAL_REG 0x16 -#elif (VDDEE_VAL == 831) - #define VDDEE_VAL_REG 0x17 -#elif (VDDEE_VAL == 841) - #define VDDEE_VAL_REG 0x18 -#elif (VDDEE_VAL == 851) - #define VDDEE_VAL_REG 0x19 -#elif (VDDEE_VAL == 861) - #define VDDEE_VAL_REG 0x1a -#elif (VDDEE_VAL == 871) - #define VDDEE_VAL_REG 0x1b -#elif (VDDEE_VAL == 881) - #define VDDEE_VAL_REG 0x1c -#elif (VDDEE_VAL == 891) - #define VDDEE_VAL_REG 0x1d -#else - #error "VDDEE val out of range\n" -#endif - -#else - -#if (VDDEE_VAL == 711) - #define VDDEE_VAL_REG 0x120000 -#elif (VDDEE_VAL == 721) - #define VDDEE_VAL_REG 0x110001 -#elif (VDDEE_VAL == 731) - #define VDDEE_VAL_REG 0x100002 -#elif (VDDEE_VAL == 741) - #define VDDEE_VAL_REG 0xf0003 -#elif (VDDEE_VAL == 751) - #define VDDEE_VAL_REG 0xe0004 -#elif (VDDEE_VAL == 761) - #define VDDEE_VAL_REG 0xd0005 -#elif (VDDEE_VAL == 771) - #define VDDEE_VAL_REG 0xc0006 -#elif (VDDEE_VAL == 781) - #define VDDEE_VAL_REG 0xb0007 -#elif (VDDEE_VAL == 791) - #define VDDEE_VAL_REG 0xa0008 -#elif (VDDEE_VAL == 801) - #define VDDEE_VAL_REG 0x90009 -#elif (VDDEE_VAL == 811) - #define VDDEE_VAL_REG 0x8000a -#elif (VDDEE_VAL == 821) - #define VDDEE_VAL_REG 0x7000b -#elif (VDDEE_VAL == 831) - #define VDDEE_VAL_REG 0x6000c -#elif (VDDEE_VAL == 841) - #define VDDEE_VAL_REG 0x5000d -#elif (VDDEE_VAL == 851) - #define VDDEE_VAL_REG 0x4000e -#elif (VDDEE_VAL == 861) - #define VDDEE_VAL_REG 0x3000f -#elif (VDDEE_VAL == 871) - #define VDDEE_VAL_REG 0x20010 -#elif (VDDEE_VAL == 881) - #define VDDEE_VAL_REG 0x10011 -#elif (VDDEE_VAL == 891) - #define VDDEE_VAL_REG 0x12 -#else - #error "VDDEE val out of range\n" -#endif -#endif - -/* for PWM use */ -/* - * GPIOE_0 PWM_A VDDEE_PWM - * - * GPIOE_1 PWM_B VCCK_PWM - */ -/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */ -#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400) -#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400) - -/* pwm clock and pwm controller */ -#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800) -#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400) -#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400) -#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400) - -bl2_reg_t __bl2_reg[] = { -#ifdef CONFIG_I2C_REGULATOR - /* demo, user defined override register */ - {0, 0, 0xffffffff, 0, 0, 0}, - {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, - {PWMAB_MISC_REG_AB, 0x1 << 1, 0x1 << 1, 0, BL2_INIT_STAGE_1, 0}, - /* Set GPIOA_5 low */ - {PADCTRL_GPIOA_O, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_GPIOA_OEN, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, - /* Set GPIOD_10 low */ - {PADCTRL_GPIOD_O, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, - /* Set GPIOX_11 low */ - {PADCTRL_GPIOX_O, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_GPIOX_OEN, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, - /* set pwm A and pwm B clock rate to 24M, enable them */ - {CLKTREE_PWM_CLK_AB_CTRL, 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, - /* set GPIOE_0 GPIOE_1 drive strength to 3*/ - {PADCTRL_GPIOE_DS, 0x3 << 2, 0x3 << 2, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, -#ifdef CONFIG_PDVFS_ENABLE - /* table_id, ee_voltage, ...... */ - {1, 0x11, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, - {2, 0x14, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, - {3, 0x16, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, -#else - {0x0, VDDEE_VAL_REG, 0x0, 0, BL2_INIT_STAGE_I2C_REGULATOR, 0}, -#endif -#else - /* demo, user defined override register */ - {0, 0, 0xffffffff, 0, 0, 0}, -#ifdef CONFIG_PDVFS_ENABLE - {PWMAB_PWM_A, 0x000c0006, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, - {PWMAB_PWM_A, 0x00090009, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, - {PWMAB_PWM_A, 0x0007000b, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, -#else - {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, -#endif - {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, - {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0}, - /* enable vddcpu dc-dc, set GPIOD_10 high */ - {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, - /* set pwm A and pwm B clock rate to 24M, enable them */ - {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, - /* set GPIOE_0 GPIOE_1 drive strength to 3*/ - {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, -#endif -};
diff --git a/board/amlogic/c2_xua4_bx/Kconfig b/board/amlogic/c2_xua4_bx/Kconfig deleted file mode 100644 index b0dde4b..0000000 --- a/board/amlogic/c2_xua4_bx/Kconfig +++ /dev/null
@@ -1,37 +0,0 @@ -if TARGET_C2_XUA4_BX - -config SYS_SOC - default "c2" - -config SYS_BOARD - default "c2_xua4_bx" - -config SYS_VENDOR - default "amlogic" - -config SYS_CONFIG_NAME - default "c2_xua4_bx" - -config DTB_BIND_KERNEL - bool "load dtb from boot part but not flash rsv" - default n - -config CMD_PLLTEST - bool "support plltest command" - default y - help - support plltest command - -config I2C_REGULATOR - bool "use i2c regulator to configure vddee" - default n - -config DDR_WINDOWING_BOOT - bool "enable/disable ddr windowing boot" - default n - -config LED_AW2026 - bool "enable/disable AW2026 LED" - default y - -endif
diff --git a/board/amlogic/c2_xua4_bx/Makefile b/board/amlogic/c2_xua4_bx/Makefile deleted file mode 100644 index 0403c0c..0000000 --- a/board/amlogic/c2_xua4_bx/Makefile +++ /dev/null
@@ -1 +0,0 @@ -obj-y += $(BOARD).o
diff --git a/board/amlogic/c2_xua4_bx/aml-user-key.sig b/board/amlogic/c2_xua4_bx/aml-user-key.sig deleted file mode 100644 index 0f89a75..0000000 --- a/board/amlogic/c2_xua4_bx/aml-user-key.sig +++ /dev/null Binary files differ
diff --git a/board/amlogic/c2_xua4_bx/c2_xua4_bx.c b/board/amlogic/c2_xua4_bx/c2_xua4_bx.c deleted file mode 100644 index 9e8cf44..0000000 --- a/board/amlogic/c2_xua4_bx/c2_xua4_bx.c +++ /dev/null
@@ -1,319 +0,0 @@ - -/* - * Copyright (C) 2015 Amlogic, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -*/ - -#include <common.h> -#include <asm/io.h> -#include <malloc.h> -#include <errno.h> -#include <environment.h> -#include <fdt_support.h> -#include <linux/libfdt.h> -#include <amlogic/cpu_id.h> -#include <asm/arch/secure_apb.h> -#include <asm/arch/pinctrl_init.h> -#include <linux/sizes.h> -#include <asm-generic/gpio.h> -#include <dm.h> -#include <asm/armv8/mmu.h> -#include <amlogic/aml_v3_burning.h> -#include <amlogic/aml_v2_burning.h> -#include <amlogic/leds-aw2026.h> -#include <linux/mtd/partitions.h> -#include <linux/ssr/ps13216.h> - -DECLARE_GLOBAL_DATA_PTR; - -int serial_set_pin_port(unsigned long port_base) -{ - return 0; -} - -int dram_init(void) -{ - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -unsigned int get_dram_size(void) -{ - // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 -#if defined(CONFIG_SYS_MEM_TOP_HIDE) - return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; -#else - return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); -#endif /* CONFIG_SYS_MEM_TOP_HIDE */ -} - - -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = get_dram_size(); - return 0; -} - -/* secondary_boot_func - * this function should be write with asm, here, is is only for compiling pass - * */ -void secondary_boot_func(void) -{ -} - -int board_eth_init(bd_t *bis) -{ - return 0; -} - -int active_clk(void) -{ - struct udevice *clk = NULL; - int err; - - err = uclass_get_device_by_name(UCLASS_CLK, - "xtal-clk", &clk); - if (err) { - pr_err("Can't find xtal-clk clock (%d)\n", err); - return err; - } - err = uclass_get_device_by_name(UCLASS_CLK, - "clock-controller@0", &clk); - if (err) { - pr_err("Can't find clock-controller@0 clock (%d)\n", err); - return err; - } - - return 0; -} - -void board_init_mem(void) { - /* config bootm low size, make sure whole dram/psram space can be used */ - phys_size_t ram_size; - char *env_tmp; - env_tmp = env_get("bootm_size"); - if (!env_tmp) { - ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); - env_set_hex("bootm_low", 0); - env_set_hex("bootm_size", ram_size); - } -} - -int board_init(void) -{ - unsigned int value; - - printf("board init\n"); - - /* set GPIOB_3 to low before emmc init */ - value = readl(PADCTRL_PIN_MUX_REG3); - /* set to gpio pin */ - writel(value & ~(0xf << 12), PADCTRL_PIN_MUX_REG3); - value = readl(PADCTRL_GPIOB_OEN); - /* enable gpio output */ - writel(value & ~(0x1 << 3), PADCTRL_GPIOB_OEN); - value = readl(PADCTRL_GPIOB_O); - /* set output value to low */ - writel(value & ~(0x1 << 3), PADCTRL_GPIOB_O); - udelay(20000); - - //Please keep try usb boot first in board_init, as other init before usb may cause burning failure -#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) - if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2))) - { aml_v3_factory_usb_burning(0, gd->bd); } -#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) - - pinctrl_devices_active(PIN_CONTROLLER_NUM); - active_clk(); - - // set to white by default - sys_led_init(WHITE); - return 0; -} - -int board_late_init(void) -{ - board_init_mem(); - -#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard - aml_try_factory_sdcard_burning(0, gd->bd); -#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE - //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003' -#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) - if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2)) - { aml_v3_factory_usb_burning(0, gd->bd); } -#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) - - return 0; -} - - -phys_size_t get_effective_memsize(void) -{ -#ifdef UBOOT_RUN_IN_SRAM - return 0x180000; /* SRAM 1.5MB */ -#else - // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 -#if defined(CONFIG_SYS_MEM_TOP_HIDE) - return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; -#else - return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); -#endif /* CONFIG_SYS_MEM_TOP_HIDE */ -#endif /* UBOOT_RUN_IN_SRAM */ -} - -static struct mm_region bd_mem_map[] = { - { - .virt = 0x00000000UL, - .phys = 0x00000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = bd_mem_map; - -int mach_cpu_init(void) { - printf("\nmach_cpu_init\n"); - return 0; -} - -int ft_board_setup(void *blob, bd_t *bd) -{ - /* eg: bl31/32 rsv */ - return 0; -} - -int do_get_hw_id(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) -{ - unsigned int hw_bid = 0, hw_cid = 0, ret = 0; - char hw_id_str[8] = {0}; // eg: 0x0A - - /* - * HW_BID_2 : GPIOD_8 - * HW_BID_1 : GPIOD_5 - * HW_BID_0 : GPIOD_4 - * HW_CID_2 : GPIOX_10 - * HW_CID_1 : GPIOX_9 - * HW_CID_0 : GPIOX_8 - * - */ - /* disable gpio pull */ - ret = readl(PADCTRL_GPIOD_PULL_EN); - writel(ret & (~(0x13 << 4)), PADCTRL_GPIOD_PULL_EN); - ret = readl(PADCTRL_GPIOX_PULL_EN); - writel(ret & (~(0x7 << 8)), PADCTRL_GPIOX_PULL_EN); - - /* pin mux to gpio pin */ - /* GPIOD_4, GPIOD_5 */ - ret = readl(PADCTRL_PIN_MUX_REG0); - writel(ret & (~(0xFF << 16)), PADCTRL_PIN_MUX_REG0); - /* GPIOD_8 */ - ret = readl(PADCTRL_PIN_MUX_REG1); - writel(ret & (~(0xF << 0)), PADCTRL_PIN_MUX_REG1); - /* GPIOX_8, GPIOX_9, GPIOX_10 */ - ret = readl(PADCTRL_PIN_MUX_REG7); - writel(ret & (~(0xFFF << 0)), PADCTRL_PIN_MUX_REG7); - - /* enable input */ - ret = readl(PADCTRL_GPIOD_OEN); - writel(ret | (0x13 << 4), PADCTRL_GPIOD_OEN); - ret = readl(PADCTRL_GPIOX_OEN); - writel(ret | (0x7 << 8), PADCTRL_GPIOX_OEN); - - /* read hw id */ - ret = readl(PADCTRL_GPIOD_I); - hw_bid = (ret >> 4) & 0x3; - hw_bid |= (ret >> 6) & 0x4; - ret = readl(PADCTRL_GPIOX_I); - hw_cid = (ret >> 8) & 0x7; - - if (XUA4_HW_CID != hw_cid) { - pr_err("The image doesn't match the device(CID=0x%x)\n", hw_cid); - sys_led_init(YELLOW); - while(1); - } - - ret = (hw_cid << 0x3) | hw_bid; - snprintf(hw_id_str, sizeof(hw_id_str), "0x%02x", ret); - env_set("hw_id", hw_id_str); - return 0; -} - -U_BOOT_CMD( - get_hw_id, 1, 0, do_get_hw_id, "get HW_ID and env_set 'hw_id'\n", "get_hw_id" -); - -/* partition table */ -/* partition table for spinand flash */ -#ifdef CONFIG_SPI_NAND -static const struct mtd_partition spinand_partitions[] = { - { - .name = "logo", - .offset = 0, - .size = 2 * SZ_1M, - }, - { - .name = "recovery", - .offset = 0, - .size = 16 * SZ_1M, - }, - { - .name = "boot", - .offset = 0, - .size = 16 * SZ_1M, - }, - { - .name = "system", - .offset = 0, - .size = 64 * SZ_1M, - }, - /* last partition get the rest capacity */ - { - .name = "data", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - } -}; -struct mtd_partition *get_partition_table(int *partitions) -{ - *partitions = ARRAY_SIZE(spinand_partitions); - return spinand_partitions; -} -#endif /* CONFIG_SPI_NAND */ - -int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;} - -int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;} - -void __attribute__((weak)) set_working_fdt_addr(ulong addr) {} - -int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;} - -void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c2_xua4_bx/firmware/timing.c b/board/amlogic/c2_xua4_bx/firmware/timing.c deleted file mode 100755 index 6e35a04..0000000 --- a/board/amlogic/c2_xua4_bx/firmware/timing.c +++ /dev/null
@@ -1,1457 +0,0 @@ -/* - * board/amlogic/c2_xua4_bx/firmware/timing.c - * - * Copyright (C) 2015 Amlogic, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -*/ - -#include <asm/arch/secure_apb.h> -#include <asm/arch/timing.h> -#include <asm/arch/ddr_define.h> - -/* board clk defines */ -#define CPU_CLK 1512 -#define TIMMING_MAX_CONFIG 1 -#define ENABLE_DDR3 0 -#define ENABLE_DDR4 1 -#define ENABLE_LPDDR4 0 - -ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = { -#if ENABLE_DDR4 -{ - .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, - .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4, - .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, - .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096 - .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, - .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, - .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, - .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, - .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT, - .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)}, - .cfg_board_common_setting. fast_boot[0] = 0x1, - .cfg_board_common_setting. fast_boot[3] = 0x46, - - //DDR frequercy 1 - .cfg_board_SI_setting_ps[0].DRAMFreq = 1272,//1320,1200,1104,1008,912,792 - .cfg_board_SI_setting_ps[0].PllBypassEn = 0, - .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_48_OHM, - .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, - .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[0].reserve2 = 0, - .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, - .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, - .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, - .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, - .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { - 128,128,128-20,128,128,128,128,128, - 384,384,384,384,384,384,384,384, - 384,384,384,384,384,384,384,384, - 384,384,384,384,384,384,384,384, - 384,384,384,384, - },//total 36 - - .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { - 128,128,128-50,128,128,128,128,128, - 384,384,384,384,384,384,384,384, - 384,384,384,384,384,384,384,384, - 384,384,384,384,384,384,384,384, - 384,384,384,384, - },//total 36 - - .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x0000005f,// 95 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000073,// 115 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x0000005f,// 95 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000087,// 135 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000080,// 128 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000080,// 128 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000080,// 128 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000080,// 128 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000009f,// 159 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000095,// 149 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000092,// 146 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x0000009f,// 159 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000bb,// 187 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000cd,// 205 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000b1,// 177 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000c5,// 197 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000ad,// 173 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000000a1,// 161 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000d3,// 211 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000000a2,// 162 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000d1,// 209 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000000d3,// 211 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000d0,// 208 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000000a7,// 167 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000a9,// 169 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000000b9,// 185 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000000ae,// 174 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000b1,// 177 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000b2,// 178 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000bd,// 189 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000000d1,// 209 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000d0,// 208 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000c6,// 198 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000d1,// 209 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000bf,// 191 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000000c1,// 193 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000d3,// 211 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000000c1,// 193 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000dc,// 220 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000000ae,// 174 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000a1,// 161 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000ab,// 171 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000ac,// 172 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000bd,// 189 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000037a,// 890 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000359,// 857 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000352,// 850 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x0000034f,// 847 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000075,// 117 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x0000006c,// 108 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000058,// 88 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007c,// 124 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000034,// 52 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000033,// 51 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000002b,// 43 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000032,// 50 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000050,// 80 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000062,// 98 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000043,// 67 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000058,// 88 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000028,// 40 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000028,// 40 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000036,// 54 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000044,// 68 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x00000042,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000026,// 38 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000002c,// 44 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x0000002a,// 42 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x00000032,// 50 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000029,// 41 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x0000002c,// 44 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000048,// 72 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000003e,// 62 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x0000003b,// 59 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x0000003b,// 59 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000050,// 80 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003d,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x00000030,// 48 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x0000002e,// 46 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000002f,// 47 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000033,// 51 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0 - - .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { - 0,40,40,40,40,40,40,40,40,40,40, - 40,40,40,40,40,40,40,40,40,40,40, - 40,40,40,40,40,40,40,40,40,40,40, - 40,40,40,40,50,40,50,40,50,40,50},//total 44 - .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { - 0,32,32,32,32,32,32,32,32,32,32, - 32,32,32,32,32,32,32,32,32,32,32, - 32,32,32,32,32,32,32,32,32,32,32, - 32,32,32},//total 36 - .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { - (0 << 7) | 6, (0 << 7) | 6, (1 << 7) | 5, (0 << 7) | 0, - (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, - (1 << 7) | 10, (1 << 7) | 10, (1 << 7) | 10, (1 << 7) | 10, - (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, - }, - - //pinmux setting - .cfg_board_common_setting. ac_pinmux = { - 0, 0, 0, 1, 2, 3, - 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, - }, - .cfg_board_common_setting. ddr_dqs_swap = 0, - - .cfg_board_common_setting. ddr_dq_remap = { - 0,1,2,3,4,5,6,7, - 8,9,10,11,12,13,14,15, - 16,17,18,19,20,21,22,23, - 24,25,26,27,28,29,30,31, - 32,33,34,35 - },//d0-d31 dm0 dm1 dm2 dm3 - - .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start - .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), - .cfg_board_common_setting. timming_struct_version = 0, - .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), - .cfg_board_common_setting. timming_struct_real_size = 0, //0 - .cfg_board_common_setting. ddr_func = 0, - .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, - .cfg_board_common_setting. dram_cs0_base_add = 0, - .cfg_board_common_setting. dram_cs1_base_add = 0, - - .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE, - .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, - .cfg_board_common_setting. org_tdqs2dq = 0, - .cfg_board_common_setting. reserve1_test_function = {0}, - .cfg_board_common_setting. ddr_vddee_setting = {0}, - - //DDR frequercy 2 - .cfg_board_SI_setting_ps[1].DRAMFreq = 600, - .cfg_board_SI_setting_ps[1].PllBypassEn = 0, - .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, - .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, - .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[1].reserve2 = 0, - .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, - .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, - .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, - .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, - .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { - 128,128,128,128,128,128,128,128, - 128,128,128,128,128,128,128,128, - 128,128,128,128,128,128,128,128, - 128,128,128,128,128,128,128,128, - 128,128,128,128, - },//total 36 - - .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { - 128,128,128,128,128,128,128,128, - 128,128,128,128,128,128,128,128, - 128,128,128,128,128,128,128,128, - 128,128,128,128,128,128,128,128, - 128,128,128,128, - },//total 36 - .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, - //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, - .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50,}, - - //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 - .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 - //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 - .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 - .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0},//total 72 - .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { - 40,40,40,40,40,40,40,40,40,40,40, - 40,40,40,40,40,40,40,40,40,40,40, - 40,40,40,40,40,40,40,40,40,40,40, - 40,40,40,40,40,40,40,40,40,40,40},//total 44 - .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { - 32,32,32,32,32,32,32,32,32,32,32, - 32,32,32,32,32,32,32,32,32,32,32, - 32,32,32,32,32,32,32,32,32,32,32, - 32,32,32},//total 36 - - .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end -}, -#endif //end ENABLE_DDR4 -#if ENABLE_DDR3 -{ - .cfg_board_common_setting.timming_magic = 0, - .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, - .cfg_board_common_setting.timming_struct_version = 0, - .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), - .cfg_board_common_setting.timming_struct_real_size = 0, //0 - .cfg_board_common_setting.fast_boot = {0}, - .cfg_board_common_setting.ddr_func = 0, - .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, - .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR3, - .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0, - .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, - .cfg_board_common_setting.dram_cs0_base_add = 0, - .cfg_board_common_setting.dram_cs1_base_add = 0, - .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB, - .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, - .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, - .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE, - .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, - .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, - .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, - .cfg_board_common_setting.org_tdqs2dq = 0, - .cfg_board_common_setting.reserve1_test_function = {0}, - .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT, - .cfg_board_common_setting.ac_pinmux = - { - 0, 0, 0, 1, 2, 3, 0, 1, - 2, 3, 4, 5, 6, 7, 8, 9, - 10, 11, 12, 13, 14, 15, 0, 0, - 0, 0, 20, 21, 22, 0, 0, 25, - 26, 27, 0 - }, - .cfg_board_common_setting.ddr_dqs_swap = 0, - .cfg_board_common_setting.ddr_dq_remap = { - 0, 1, 2, 3, 4, 5, 6, 7, - 8, 9, 10, 11, 12, 13, 14, 15, - 16, 17, 18, 19, 20, 21, 22, 23, - 24, 25, 26, 27, 28, 29, 30, 31, - 32, 33, 34, 35, - }, //d0-d31 dm0 dm1 dm2 dm3 - .cfg_board_common_setting.ddr_vddee_setting = {0}, - .cfg_board_SI_setting_ps[0].DRAMFreq = 912, - .cfg_board_SI_setting_ps[0].PllBypassEn = 0, - .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM, - .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[0].reserve2 = 0, - .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, - .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, - .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, - .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, - .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { - 128, 128, 128 - 20, 128, 128, 128, 128, 128, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, - }, //total 36 - - .cfg_ddr_training_delay_ps[0].ac_trace_delay = { - 128, 128, 128 - 20, 128, 128, 128, 128, 128, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, - }, //total 36 - .cfg_ddr_training_delay_ps[0].write_dqs_delay = { - 128 - 1, 128 - 1, 128 + 48, 128 + 58, 128 + 32, 128 + 32, 128 + 32, 128 + 32 - }, - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay = { - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, - 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, - 128 + 128, 128 + 128, 128 + 128, 128 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - }, - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay = { - 896, 896, 896, 896, 896, 896, 896, 896 - }, //total 8 - .cfg_ddr_training_delay_ps[0].read_dqs_delay = { - 64, 64, 50, 40, 64, 64, 64, 64 - }, //total 8 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay = { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 - }, //total 72 - .cfg_ddr_training_delay_ps[0].soc_bit_vref = { - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32 + 5, 32, 32 + 5, - 32, 32 + 5, 32, 32 + 5 - }, - .cfg_ddr_training_delay_ps[0].dram_bit_vref = { - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32 - }, //total 36 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[0] = 0x0000007d,// 125 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[1] = 0x00000091,// 145 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[2] = 0x00000091,// 145 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[3] = 0x0000009b,// 155 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[4] = 0x000000a0,// 160 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[5] = 0x000000a0,// 160 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[6] = 0x000000a0,// 160 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[7] = 0x000000a0,// 160 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0] = 0x000000c2,// 194 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1] = 0x000000b0,// 176 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2] = 0x000000af,// 175 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3] = 0x000000b0,// 176 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4] = 0x000000c0,// 192 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5] = 0x000000c3,// 195 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6] = 0x000000b4,// 180 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7] = 0x000000be,// 190 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8] = 0x000000ba,// 186 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9] = 0x000000c1,// 193 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10] = 0x000000d5,// 213 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11] = 0x000000c1,// 193 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12] = 0x000000d0,// 208 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13] = 0x000000cc,// 204 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14] = 0x000000c3,// 195 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15] = 0x000000be,// 190 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16] = 0x000000c0,// 192 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17] = 0x000000c8,// 200 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18] = 0x000000e0,// 224 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19] = 0x000000e5,// 229 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20] = 0x000000e2,// 226 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21] = 0x000000ec,// 236 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22] = 0x000000ec,// 236 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23] = 0x000000e7,// 231 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24] = 0x000000e4,// 228 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25] = 0x000000e9,// 233 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26] = 0x000000e6,// 230 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27] = 0x000000eb,// 235 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28] = 0x000000f5,// 245 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29] = 0x000000e7,// 231 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30] = 0x000000fd,// 253 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31] = 0x000000e8,// 232 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32] = 0x000000e4,// 228 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33] = 0x000000ee,// 238 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34] = 0x000000ec,// 236 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35] = 0x000000f2,// 242 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0] = 0x0000038c,// 908 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1] = 0x0000037a,// 890 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2] = 0x0000039a,// 922 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3] = 0x00000395,// 917 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[0] = 0x0000007f-0x30,// 127 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[1] = 0x0000007d-0x30,// 125 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[2] = 0x0000006d-0x30,// 109 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[3] = 0x0000006f-0x30,// 111 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[4] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[5] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[6] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[7] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0] = 0x00000048-0x30,// 72 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1] = 0x00000044-0x30,// 68 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2] = 0x00000038-0x30,// 56 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3] = 0x0000003b-0x30,// 59 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4] = 0x00000049-0x30,// 73 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5] = 0x0000004b-0x30,// 75 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6] = 0x0000003b-0x30,// 59 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7] = 0x00000049-0x30,// 73 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9] = 0x00000040-0x30,// 64 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10] = 0x00000052-0x30,// 82 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11] = 0x00000039-0x30,// 57 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12] = 0x00000040-0x30,// 64 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13] = 0x00000045-0x30,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14] = 0x00000042-0x30,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15] = 0x00000034-0x30,// 52 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16] = 0x0000003c-0x30,// 60 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17] = 0x00000086-0x30,// 134 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18] = 0x0000003f-0x30,// 63 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19] = 0x00000048-0x30,// 72 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20] = 0x00000037-0x30,// 55 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21] = 0x00000048-0x30,// 72 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22] = (0x0000004e)-0x30,// 78 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23] = 0x00000044-0x30,// 68 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24] = 0x00000042-0x30,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25] = 0x00000047-0x30,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26] = 0x0000007f-0x30,// 127 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27] = 0x00000040-0x30,// 64 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28] = 0x00000052-0x30,// 82 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29] = 0x0000003d-0x30,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30] = (0x0000004e)-0x30,// 78 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31] = 0x0000003c-0x30,// 60 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32] = (0x0000003e)-0x30,// 62 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33] = 0x0000003f-0x30,// 63 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34] = 0x0000004c-0x30,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35] = 0x00000091-0x30,// 145 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71] = 0x00000000,// 0 - - .cfg_ddr_training_delay_ps[0].reserve_training_parameter = {0}, - .cfg_board_SI_setting_ps[1].DRAMFreq = 667, - .cfg_board_SI_setting_ps[1].PllBypassEn = 0, - .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, - .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, - .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[1].reserve2 = 0, - .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, - .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, - .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, - .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, - .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, - }, //total 36 - .cfg_ddr_training_delay_ps[1].ac_trace_delay = { - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, - }, //total 36 - .cfg_ddr_training_delay_ps[1].write_dqs_delay = { - 0, 0, 0, 0, 0, 0, 0, 0 - }, - .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50 - }, - .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { - 192, 192, 192, 192, 192, 192, 192, 192 - }, //total 8 - .cfg_ddr_training_delay_ps[1].read_dqs_delay = { - 64, 64, 64, 64, 64, 64, 64, 64 - }, //total 8 - .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 - }, //total 72 - .cfg_ddr_training_delay_ps[1].soc_bit_vref = { - 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40 - }, //total 44 - .cfg_ddr_training_delay_ps[1].dram_bit_vref = { - 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32 - }, //total 36 - .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0}, -}, -#endif - -#if ENABLE_LPDDR4 //LPDDR4 rank0,timing_config -{ - .cfg_board_common_setting.timming_magic = 0, - .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, - .cfg_board_common_setting.timming_struct_version = 0, - .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), - .cfg_board_common_setting.timming_struct_real_size = 0, //0 - .cfg_board_common_setting.fast_boot = { 0 }, - .cfg_board_common_setting.ddr_func = 0, - .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, - .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_LPDDR4, - .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH01, - .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, - .cfg_board_common_setting.dram_cs0_base_add = 0, - .cfg_board_common_setting.dram_cs1_base_add = 0, - .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB, - .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, - .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, - .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_1T_MODE, - .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, - .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, //DDR_WRITE_READ_DBI_DISABLE , - .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, - .cfg_board_common_setting.org_tdqs2dq = 0, - .cfg_board_common_setting.reserve1_test_function = { 0 }, - .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT, -#ifdef CONFIG_DDR_WINDOWING_BOOT - .cfg_board_common_setting.fast_boot[0] = 0x1, - .cfg_board_common_setting.fast_boot[3] = 0x46, -#endif - //lpddr4 ac pinmux - .cfg_board_common_setting.ac_pinmux = { - 0, 0, 0, 1, 0, 1, 1, 3, - 0, 4, 4, 2, 0, 0, 1, 0, - 2, 0, 0, 0, 0, 3, 0, 0, - 0, 0, 5, 5, 0, 0, 0, 0, - 0, 0, - }, - .cfg_board_common_setting.ddr_dqs_swap = 0, - - .cfg_board_common_setting.ddr_dq_remap = { - 1, 0, 3, 2, 7, 5, 6, 4, - 9, 15, 13, 14, 10, 11, 12, 8, - 21, 19, 20, 18, 17, 16, 22, 23, - 25, 26, 24, 27, 31, 29, 30, 28, - 32, 33, 34, 35 - }, //d0-d31 dm0 dm1 dm2 dm3 - - .cfg_board_common_setting.ddr_vddee_setting = { 0 }, - .cfg_board_SI_setting_ps[0].DRAMFreq = 1320, - .cfg_board_SI_setting_ps[0].PllBypassEn = 0, - .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_60_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_LPDDR4_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_LPDDR4_ODT_60_OHM, - .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_LPDDR4_AC_ODT_80_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[0].reserve2 = 0, - .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, //3000/11, - .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, //170, - .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, //280, //330 - .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 }, - .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { - 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 0 + 128, //0,0,0,0,0,0,0,0, - 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128, 128 + 20 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - }, //total 36 - - .cfg_ddr_training_delay_ps[0].ac_trace_delay = { - 64 + 128, 64 + 128, 64 + 128-64, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 128 + 128, //0,0,0,0,0,0,0,0, - 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128-40, 128 + 20 + 128-10, 128 + 0 + 128, 128 + 0 + 128+10, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - }, //total 36 - .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 }, - - .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x000000af,// 175 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x000000cd,// 205 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x000000aa,// 170 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x000000cd,// 205 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x000000af,// 175 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x000000cd,// 205 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x000000aa,// 170 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x000000cd,// 205 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x000001cd,// 461 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x000001cc,// 460 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x000001ba,// 442 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000001d8,// 472 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000001e1,// 481 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000001ce,// 462 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000001c6,// 454 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000001d0,// 464 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000001cc,// 460 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000001d9,// 473 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000001da,// 474 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000001c4,// 452 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000001d5,// 469 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000001ea,// 490 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000001e9,// 489 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000001e2,// 482 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000001ea,// 490 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000001d5,// 469 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000001c6,// 454 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000001ce,// 462 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000001b5,// 437 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000001c7,// 455 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000001d3,// 467 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000001d1,// 465 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000001c4,// 452 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000001eb,// 491 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000001d1,// 465 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000001f7,// 503 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000001d8,// 472 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000001cf,// 463 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000001d3,// 467 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000001c9,// 457 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000001de,// 478 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x000001cd,// 461 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x000001cc,// 460 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x000001ba,// 442 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x000001d8,// 472 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x000001e1,// 481 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x000001ce,// 462 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x000001c6,// 454 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x000001d0,// 464 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x000001cc,// 460 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x000001d9,// 473 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x000001da,// 474 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x000001c4,// 452 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x000001d5,// 469 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x000001ea,// 490 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x000001e9,// 489 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x000001e2,// 482 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x000001ea,// 490 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x000001d5,// 469 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x000001c6,// 454 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x000001ce,// 462 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x000001b5,// 437 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x000001c7,// 455 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x000001d3,// 467 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x000001d1,// 465 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x000001c4,// 452 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x000001eb,// 491 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x000001d1,// 465 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x000001f7,// 503 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x000001d8,// 472 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x000001cf,// 463 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x000001d3,// 467 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x000001c9,// 457 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x000001de,// 478 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x000003ab,// 939 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000383,// 899 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000395,// 917 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x00000378,// 888 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x000003ab,// 939 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000383,// 899 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000395,// 917 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000378,// 888 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x0000007e,// 126 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x00000088,// 136 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000070,// 112 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007a,// 122 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x0000007e,// 126 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000088,// 136 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000070,// 112 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x0000007a,// 122 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000044,// 68 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000051,// 81 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x00000036,// 54 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000054,// 84 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x0000003d,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000045,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000051,// 81 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000037,// 55 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x0000003d,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000052,// 82 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x0000005b,// 91 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x0000004c,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000005a,// 90 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x0000004b,// 75 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000042,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x0000004f,// 79 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000030,// 48 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000042,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000004c,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000041,// 65 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000058,// 88 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000045,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000041,// 65 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000056,// 86 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003f,// 63 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000055,// 85 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x0000003e,// 62 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000034,// 52 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x00000031,// 49 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000036,// 54 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000040,// 64 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000044,// 68 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000051,// 81 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000036,// 54 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000054,// 84 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x0000003d,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000045,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000051,// 81 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000037,// 55 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x0000003d,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000052,// 82 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x0000005b,// 91 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x0000004c,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x0000005a,// 90 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x0000004b,// 75 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000042,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x0000004f,// 79 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000030,// 48 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000042,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x0000004c,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000041,// 65 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000058,// 88 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000045,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000041,// 65 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000056,// 86 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x0000003f,// 63 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000055,// 85 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x0000003e,// 62 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000034,// 52 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000031,// 49 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000036,// 54 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000040,// 64 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[0]=0,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[1]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[2]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[3]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[4]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[5]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[6]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[7]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[8]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[9]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[10]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[11]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[12]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[13]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[14]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[15]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[16]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[17]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[18]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[19]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[20]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[21]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[22]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[23]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[24]=0x00000016,// 22 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[25]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[26]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[27]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[28]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[29]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[30]=0x00000016,// 22 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[31]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[32]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[33]=0x00000016,// 22 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[34]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[35]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[36]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[37]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[38]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[39]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[40]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[41]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[42]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[43]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[0]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[1]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[2]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[3]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[4]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[5]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[6]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[7]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[8]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[9]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[10]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[11]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[12]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[13]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[14]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[15]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[16]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[17]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[18]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[19]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[20]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[21]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[22]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[23]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[24]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[25]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[26]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[27]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[28]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[29]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[30]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[31]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[32]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[33]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[34]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[35]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { - (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, - (1 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, - (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, - (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, - }, - .cfg_board_SI_setting_ps[1].DRAMFreq = 667, - .cfg_board_SI_setting_ps[1].PllBypassEn = 0, - .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, - .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, - .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[1].reserve2 = 0, - .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, - .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, - .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, - .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 }, - .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, - }, //total 36 - .cfg_ddr_training_delay_ps[1].ac_trace_delay = { - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, - }, //total 36 - - .cfg_ddr_training_delay_ps[1].write_dqs_delay = { - 0, 0, 0, 0, 0, 0, 0, 0 - }, - .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - }, - .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { - 192, 192, 192, 192, 192, 192, 192, 192 - }, //total 8 - .cfg_ddr_training_delay_ps[1].read_dqs_delay = { - 64, 64, 64, 64, 64, 64, 64, 64 - }, //total 8 - .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 - }, //total 72 - .cfg_ddr_training_delay_ps[1].soc_bit_vref = { - 0, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40 - }, //total 44 - .cfg_ddr_training_delay_ps[1].dram_bit_vref = { - 0, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32 - }, //total 36 - .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 }, -}, -#endif -}; -//ddr timing end - -pll_set_t __pll_setting = { - .cpu_clk = CPU_CLK / 24 * 24, -#ifdef CONFIG_PXP_EMULATOR - .pxp = 1, -#else - .pxp = 0, -#endif - .spi_ctrl = 0, - .lCustomerID = AML_CUSTOMER_ID, - .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */ - .log_ctrl = (1 << 7) | /* (1<<7), print bl2 log into buffer */ -#ifdef CONFIG_SILENT_CONSOLE - (1<<6), /* do not print log buffer */ -#else - (0<<6), /* print log buffer before run bl31 */ -#endif - .ddr_timming_save_mode = 1, -}; - -ddr_reg_t __ddr_reg[] = { - /* demo, user defined override register */ - {0xaabbccdd, 0, 0, 0, 0, 0}, - {0x11223344, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0}, -}; - - - -#define VCCK_VAL AML_VCCK_INIT_VOLTAGE -#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE -/* VCCK PWM table */ -#if (VCCK_VAL == 1039) - #define VCCK_VAL_REG 0x00000022 -#elif (VCCK_VAL == 1029) - #define VCCK_VAL_REG 0x00010021 -#elif (VCCK_VAL == 1019) - #define VCCK_VAL_REG 0x00020020 -#elif (VCCK_VAL == 1009) - #define VCCK_VAL_REG 0x0003001f -#elif (VCCK_VAL == 999) - #define VCCK_VAL_REG 0x0004001e -#elif (VCCK_VAL == 989) - #define VCCK_VAL_REG 0x0005001d -#elif (VCCK_VAL == 979) - #define VCCK_VAL_REG 0x0006001c -#elif (VCCK_VAL == 969) - #define VCCK_VAL_REG 0x0007001b -#elif (VCCK_VAL == 959) - #define VCCK_VAL_REG 0x0008001a -#elif (VCCK_VAL == 949) - #define VCCK_VAL_REG 0x00090019 -#elif (VCCK_VAL == 939) - #define VCCK_VAL_REG 0x000a0018 -#elif (VCCK_VAL == 929) - #define VCCK_VAL_REG 0x000b0017 -#elif (VCCK_VAL == 919) - #define VCCK_VAL_REG 0x000c0016 -#elif (VCCK_VAL == 909) - #define VCCK_VAL_REG 0x000d0015 -#elif (VCCK_VAL == 899) - #define VCCK_VAL_REG 0x000e0014 -#elif (VCCK_VAL == 889) - #define VCCK_VAL_REG 0x000f0013 -#elif (VCCK_VAL == 879) - #define VCCK_VAL_REG 0x00100012 -#elif (VCCK_VAL == 869) - #define VCCK_VAL_REG 0x00110011 -#elif (VCCK_VAL == 859) - #define VCCK_VAL_REG 0x00120010 -#elif (VCCK_VAL == 849) - #define VCCK_VAL_REG 0x0013000f -#elif (VCCK_VAL == 839) - #define VCCK_VAL_REG 0x0014000e -#elif (VCCK_VAL == 829) - #define VCCK_VAL_REG 0x0015000d -#elif (VCCK_VAL == 819) - #define VCCK_VAL_REG 0x0016000c -#elif (VCCK_VAL == 809) - #define VCCK_VAL_REG 0x0017000b -#elif (VCCK_VAL == 799) - #define VCCK_VAL_REG 0x0018000a -#elif (VCCK_VAL == 789) - #define VCCK_VAL_REG 0x00190009 -#elif (VCCK_VAL == 779) - #define VCCK_VAL_REG 0x001a0008 -#elif (VCCK_VAL == 769) - #define VCCK_VAL_REG 0x001b0007 -#elif (VCCK_VAL == 759) - #define VCCK_VAL_REG 0x001c0006 -#elif (VCCK_VAL == 749) - #define VCCK_VAL_REG 0x001d0005 -#elif (VCCK_VAL == 739) - #define VCCK_VAL_REG 0x001e0004 -#elif (VCCK_VAL == 729) - #define VCCK_VAL_REG 0x001f0003 -#elif (VCCK_VAL == 719) - #define VCCK_VAL_REG 0x00200002 -#elif (VCCK_VAL == 709) - #define VCCK_VAL_REG 0x00210001 -#elif (VCCK_VAL == 699) - #define VCCK_VAL_REG 0x00220000 -#else - #error "VCCK val out of range\n" -#endif - -/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/ -#ifdef CONFIG_I2C_REGULATOR -#if (VDDEE_VAL == 711) - #define VDDEE_VAL_REG 0xb -#elif (VDDEE_VAL == 721) - #define VDDEE_VAL_REG 0xc -#elif (VDDEE_VAL == 731) - #define VDDEE_VAL_REG 0xd -#elif (VDDEE_VAL == 741) - #define VDDEE_VAL_REG 0xe -#elif (VDDEE_VAL == 751) - #define VDDEE_VAL_REG 0xf -#elif (VDDEE_VAL == 761) - #define VDDEE_VAL_REG 0x10 -#elif (VDDEE_VAL == 771) - #define VDDEE_VAL_REG 0x11 -#elif (VDDEE_VAL == 781) - #define VDDEE_VAL_REG 0x12 -#elif (VDDEE_VAL == 791) - #define VDDEE_VAL_REG 0x13 -#elif (VDDEE_VAL == 801) - #define VDDEE_VAL_REG 0x14 -#elif (VDDEE_VAL == 811) - #define VDDEE_VAL_REG 0x15 -#elif (VDDEE_VAL == 821) - #define VDDEE_VAL_REG 0x16 -#elif (VDDEE_VAL == 831) - #define VDDEE_VAL_REG 0x17 -#elif (VDDEE_VAL == 841) - #define VDDEE_VAL_REG 0x18 -#elif (VDDEE_VAL == 851) - #define VDDEE_VAL_REG 0x19 -#elif (VDDEE_VAL == 861) - #define VDDEE_VAL_REG 0x1a -#elif (VDDEE_VAL == 871) - #define VDDEE_VAL_REG 0x1b -#elif (VDDEE_VAL == 881) - #define VDDEE_VAL_REG 0x1c -#elif (VDDEE_VAL == 891) - #define VDDEE_VAL_REG 0x1d -#else - #error "VDDEE val out of range\n" -#endif - -#else - -#if (VDDEE_VAL == 711) - #define VDDEE_VAL_REG 0x120000 -#elif (VDDEE_VAL == 721) - #define VDDEE_VAL_REG 0x110001 -#elif (VDDEE_VAL == 731) - #define VDDEE_VAL_REG 0x100002 -#elif (VDDEE_VAL == 741) - #define VDDEE_VAL_REG 0xf0003 -#elif (VDDEE_VAL == 751) - #define VDDEE_VAL_REG 0xe0004 -#elif (VDDEE_VAL == 761) - #define VDDEE_VAL_REG 0xd0005 -#elif (VDDEE_VAL == 771) - #define VDDEE_VAL_REG 0xc0006 -#elif (VDDEE_VAL == 781) - #define VDDEE_VAL_REG 0xb0007 -#elif (VDDEE_VAL == 791) - #define VDDEE_VAL_REG 0xa0008 -#elif (VDDEE_VAL == 801) - #define VDDEE_VAL_REG 0x90009 -#elif (VDDEE_VAL == 811) - #define VDDEE_VAL_REG 0x8000a -#elif (VDDEE_VAL == 821) - #define VDDEE_VAL_REG 0x7000b -#elif (VDDEE_VAL == 831) - #define VDDEE_VAL_REG 0x6000c -#elif (VDDEE_VAL == 841) - #define VDDEE_VAL_REG 0x5000d -#elif (VDDEE_VAL == 851) - #define VDDEE_VAL_REG 0x4000e -#elif (VDDEE_VAL == 861) - #define VDDEE_VAL_REG 0x3000f -#elif (VDDEE_VAL == 871) - #define VDDEE_VAL_REG 0x20010 -#elif (VDDEE_VAL == 881) - #define VDDEE_VAL_REG 0x10011 -#elif (VDDEE_VAL == 891) - #define VDDEE_VAL_REG 0x12 -#else - #error "VDDEE val out of range\n" -#endif -#endif - -/* for PWM use */ -/* - * GPIOE_0 PWM_A VDDEE_PWM - * - * GPIOE_1 PWM_B VCCK_PWM - */ -/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */ -#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400) -#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400) - -/* pwm clock and pwm controller */ -#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800) -#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400) -#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400) -#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400) - -bl2_reg_t __bl2_reg[] = { -#ifdef CONFIG_I2C_REGULATOR - /* demo, user defined override register */ - {0, 0, 0xffffffff, 0, 0, 0}, - {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, - {PWMAB_MISC_REG_AB, 0x1 << 1, 0x1 << 1, 0, BL2_INIT_STAGE_1, 0}, - /* Set GPIOA_5 low */ - {PADCTRL_GPIOA_O, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_GPIOA_OEN, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, - /* Set GPIOD_10 low */ - {PADCTRL_GPIOD_O, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, - /* Set GPIOX_11 low */ - {PADCTRL_GPIOX_O, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_GPIOX_OEN, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, - /* set pwm A and pwm B clock rate to 24M, enable them */ - {CLKTREE_PWM_CLK_AB_CTRL, 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, - /* set GPIOE_0 GPIOE_1 drive strength to 3*/ - {PADCTRL_GPIOE_DS, 0x3 << 2, 0x3 << 2, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, -#ifdef CONFIG_PDVFS_ENABLE - /* table_id, ee_voltage, ...... */ - {1, 0x11, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, - {2, 0x14, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, - {3, 0x16, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, -#else - {0x0, VDDEE_VAL_REG, 0x0, 0, BL2_INIT_STAGE_I2C_REGULATOR, 0}, -#endif -#else - /* demo, user defined override register */ - {0, 0, 0xffffffff, 0, 0, 0}, -#ifdef CONFIG_PDVFS_ENABLE - {PWMAB_PWM_A, 0x000c0006, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, - {PWMAB_PWM_A, 0x00090009, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, - {PWMAB_PWM_A, 0x0007000b, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, -#else - {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, -#endif - {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, - {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0}, - /* enable vddcpu dc-dc, set GPIOD_10 high */ - {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, - /* set pwm A and pwm B clock rate to 24M, enable them */ - {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, - /* set GPIOE_0 GPIOE_1 drive strength to 3*/ - {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, -#endif -};
diff --git a/board/amlogic/c2_xua4_p1/Kconfig b/board/amlogic/c2_xua4_p1/Kconfig deleted file mode 100644 index 3af9170..0000000 --- a/board/amlogic/c2_xua4_p1/Kconfig +++ /dev/null
@@ -1,37 +0,0 @@ -if TARGET_C2_XUA4_P1 - -config SYS_SOC - default "c2" - -config SYS_BOARD - default "c2_xua4_p1" - -config SYS_VENDOR - default "amlogic" - -config SYS_CONFIG_NAME - default "c2_xua4_p1" - -config DTB_BIND_KERNEL - bool "load dtb from boot part but not flash rsv" - default n - -config CMD_PLLTEST - bool "support plltest command" - default y - help - support plltest command - -config I2C_REGULATOR - bool "use i2c regulator to configure vddee" - default n - -config DDR_WINDOWING_BOOT - bool "enable/disable ddr windowing boot" - default n - -config LED_AW2026 - bool "enable/disable AW2026 LED" - default y - -endif
diff --git a/board/amlogic/c2_xua4_p1/Makefile b/board/amlogic/c2_xua4_p1/Makefile deleted file mode 100644 index 0403c0c..0000000 --- a/board/amlogic/c2_xua4_p1/Makefile +++ /dev/null
@@ -1 +0,0 @@ -obj-y += $(BOARD).o
diff --git a/board/amlogic/c2_xua4_p1/aml-user-key.sig b/board/amlogic/c2_xua4_p1/aml-user-key.sig deleted file mode 100644 index 0f89a75..0000000 --- a/board/amlogic/c2_xua4_p1/aml-user-key.sig +++ /dev/null Binary files differ
diff --git a/board/amlogic/c2_xua4_p1/c2_xua4_p1.c b/board/amlogic/c2_xua4_p1/c2_xua4_p1.c deleted file mode 100644 index 9e8cf44..0000000 --- a/board/amlogic/c2_xua4_p1/c2_xua4_p1.c +++ /dev/null
@@ -1,319 +0,0 @@ - -/* - * Copyright (C) 2015 Amlogic, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -*/ - -#include <common.h> -#include <asm/io.h> -#include <malloc.h> -#include <errno.h> -#include <environment.h> -#include <fdt_support.h> -#include <linux/libfdt.h> -#include <amlogic/cpu_id.h> -#include <asm/arch/secure_apb.h> -#include <asm/arch/pinctrl_init.h> -#include <linux/sizes.h> -#include <asm-generic/gpio.h> -#include <dm.h> -#include <asm/armv8/mmu.h> -#include <amlogic/aml_v3_burning.h> -#include <amlogic/aml_v2_burning.h> -#include <amlogic/leds-aw2026.h> -#include <linux/mtd/partitions.h> -#include <linux/ssr/ps13216.h> - -DECLARE_GLOBAL_DATA_PTR; - -int serial_set_pin_port(unsigned long port_base) -{ - return 0; -} - -int dram_init(void) -{ - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -unsigned int get_dram_size(void) -{ - // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 -#if defined(CONFIG_SYS_MEM_TOP_HIDE) - return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; -#else - return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); -#endif /* CONFIG_SYS_MEM_TOP_HIDE */ -} - - -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = get_dram_size(); - return 0; -} - -/* secondary_boot_func - * this function should be write with asm, here, is is only for compiling pass - * */ -void secondary_boot_func(void) -{ -} - -int board_eth_init(bd_t *bis) -{ - return 0; -} - -int active_clk(void) -{ - struct udevice *clk = NULL; - int err; - - err = uclass_get_device_by_name(UCLASS_CLK, - "xtal-clk", &clk); - if (err) { - pr_err("Can't find xtal-clk clock (%d)\n", err); - return err; - } - err = uclass_get_device_by_name(UCLASS_CLK, - "clock-controller@0", &clk); - if (err) { - pr_err("Can't find clock-controller@0 clock (%d)\n", err); - return err; - } - - return 0; -} - -void board_init_mem(void) { - /* config bootm low size, make sure whole dram/psram space can be used */ - phys_size_t ram_size; - char *env_tmp; - env_tmp = env_get("bootm_size"); - if (!env_tmp) { - ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); - env_set_hex("bootm_low", 0); - env_set_hex("bootm_size", ram_size); - } -} - -int board_init(void) -{ - unsigned int value; - - printf("board init\n"); - - /* set GPIOB_3 to low before emmc init */ - value = readl(PADCTRL_PIN_MUX_REG3); - /* set to gpio pin */ - writel(value & ~(0xf << 12), PADCTRL_PIN_MUX_REG3); - value = readl(PADCTRL_GPIOB_OEN); - /* enable gpio output */ - writel(value & ~(0x1 << 3), PADCTRL_GPIOB_OEN); - value = readl(PADCTRL_GPIOB_O); - /* set output value to low */ - writel(value & ~(0x1 << 3), PADCTRL_GPIOB_O); - udelay(20000); - - //Please keep try usb boot first in board_init, as other init before usb may cause burning failure -#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) - if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2))) - { aml_v3_factory_usb_burning(0, gd->bd); } -#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) - - pinctrl_devices_active(PIN_CONTROLLER_NUM); - active_clk(); - - // set to white by default - sys_led_init(WHITE); - return 0; -} - -int board_late_init(void) -{ - board_init_mem(); - -#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard - aml_try_factory_sdcard_burning(0, gd->bd); -#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE - //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003' -#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) - if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2)) - { aml_v3_factory_usb_burning(0, gd->bd); } -#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) - - return 0; -} - - -phys_size_t get_effective_memsize(void) -{ -#ifdef UBOOT_RUN_IN_SRAM - return 0x180000; /* SRAM 1.5MB */ -#else - // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 -#if defined(CONFIG_SYS_MEM_TOP_HIDE) - return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; -#else - return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); -#endif /* CONFIG_SYS_MEM_TOP_HIDE */ -#endif /* UBOOT_RUN_IN_SRAM */ -} - -static struct mm_region bd_mem_map[] = { - { - .virt = 0x00000000UL, - .phys = 0x00000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = bd_mem_map; - -int mach_cpu_init(void) { - printf("\nmach_cpu_init\n"); - return 0; -} - -int ft_board_setup(void *blob, bd_t *bd) -{ - /* eg: bl31/32 rsv */ - return 0; -} - -int do_get_hw_id(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) -{ - unsigned int hw_bid = 0, hw_cid = 0, ret = 0; - char hw_id_str[8] = {0}; // eg: 0x0A - - /* - * HW_BID_2 : GPIOD_8 - * HW_BID_1 : GPIOD_5 - * HW_BID_0 : GPIOD_4 - * HW_CID_2 : GPIOX_10 - * HW_CID_1 : GPIOX_9 - * HW_CID_0 : GPIOX_8 - * - */ - /* disable gpio pull */ - ret = readl(PADCTRL_GPIOD_PULL_EN); - writel(ret & (~(0x13 << 4)), PADCTRL_GPIOD_PULL_EN); - ret = readl(PADCTRL_GPIOX_PULL_EN); - writel(ret & (~(0x7 << 8)), PADCTRL_GPIOX_PULL_EN); - - /* pin mux to gpio pin */ - /* GPIOD_4, GPIOD_5 */ - ret = readl(PADCTRL_PIN_MUX_REG0); - writel(ret & (~(0xFF << 16)), PADCTRL_PIN_MUX_REG0); - /* GPIOD_8 */ - ret = readl(PADCTRL_PIN_MUX_REG1); - writel(ret & (~(0xF << 0)), PADCTRL_PIN_MUX_REG1); - /* GPIOX_8, GPIOX_9, GPIOX_10 */ - ret = readl(PADCTRL_PIN_MUX_REG7); - writel(ret & (~(0xFFF << 0)), PADCTRL_PIN_MUX_REG7); - - /* enable input */ - ret = readl(PADCTRL_GPIOD_OEN); - writel(ret | (0x13 << 4), PADCTRL_GPIOD_OEN); - ret = readl(PADCTRL_GPIOX_OEN); - writel(ret | (0x7 << 8), PADCTRL_GPIOX_OEN); - - /* read hw id */ - ret = readl(PADCTRL_GPIOD_I); - hw_bid = (ret >> 4) & 0x3; - hw_bid |= (ret >> 6) & 0x4; - ret = readl(PADCTRL_GPIOX_I); - hw_cid = (ret >> 8) & 0x7; - - if (XUA4_HW_CID != hw_cid) { - pr_err("The image doesn't match the device(CID=0x%x)\n", hw_cid); - sys_led_init(YELLOW); - while(1); - } - - ret = (hw_cid << 0x3) | hw_bid; - snprintf(hw_id_str, sizeof(hw_id_str), "0x%02x", ret); - env_set("hw_id", hw_id_str); - return 0; -} - -U_BOOT_CMD( - get_hw_id, 1, 0, do_get_hw_id, "get HW_ID and env_set 'hw_id'\n", "get_hw_id" -); - -/* partition table */ -/* partition table for spinand flash */ -#ifdef CONFIG_SPI_NAND -static const struct mtd_partition spinand_partitions[] = { - { - .name = "logo", - .offset = 0, - .size = 2 * SZ_1M, - }, - { - .name = "recovery", - .offset = 0, - .size = 16 * SZ_1M, - }, - { - .name = "boot", - .offset = 0, - .size = 16 * SZ_1M, - }, - { - .name = "system", - .offset = 0, - .size = 64 * SZ_1M, - }, - /* last partition get the rest capacity */ - { - .name = "data", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - } -}; -struct mtd_partition *get_partition_table(int *partitions) -{ - *partitions = ARRAY_SIZE(spinand_partitions); - return spinand_partitions; -} -#endif /* CONFIG_SPI_NAND */ - -int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;} - -int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;} - -void __attribute__((weak)) set_working_fdt_addr(ulong addr) {} - -int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;} - -void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c2_xua4_p1/firmware/timing.c b/board/amlogic/c2_xua4_p1/firmware/timing.c deleted file mode 100755 index 716d683..0000000 --- a/board/amlogic/c2_xua4_p1/firmware/timing.c +++ /dev/null
@@ -1,1457 +0,0 @@ -/* - * board/amlogic/c2_xua4_p1/firmware/timing.c - * - * Copyright (C) 2015 Amlogic, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -*/ - -#include <asm/arch/secure_apb.h> -#include <asm/arch/timing.h> -#include <asm/arch/ddr_define.h> - -/* board clk defines */ -#define CPU_CLK 1512 -#define TIMMING_MAX_CONFIG 1 -#define ENABLE_DDR3 0 -#define ENABLE_DDR4 1 -#define ENABLE_LPDDR4 0 - -ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = { -#if ENABLE_DDR4 -{ - .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, - .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4, - .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, - .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096 - .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, - .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, - .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, - .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, - .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT, - .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)}, - .cfg_board_common_setting. fast_boot[0] = 0x1, - .cfg_board_common_setting. fast_boot[3] = 0x46, - - //DDR frequercy 1 - .cfg_board_SI_setting_ps[0].DRAMFreq = 1272,//1320,1200,1104,1008,912,792 - .cfg_board_SI_setting_ps[0].PllBypassEn = 0, - .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_48_OHM, - .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, - .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[0].reserve2 = 0, - .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, - .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, - .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, - .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, - .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { - 128,128,128-20,128,128,128,128,128, - 384,384,384,384,384,384,384,384, - 384,384,384,384,384,384,384,384, - 384,384,384,384,384,384,384,384, - 384,384,384,384, - },//total 36 - - .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { - 128,128,128-50,128,128,128,128,128, - 384,384,384,384,384,384,384,384, - 384,384,384,384,384,384,384,384, - 384,384,384,384,384,384,384,384, - 384,384,384,384, - },//total 36 - - .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x0000005f,// 95 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000073,// 115 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x0000005f,// 95 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000087,// 135 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000080,// 128 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000080,// 128 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000080,// 128 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000080,// 128 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000009f,// 159 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000095,// 149 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000092,// 146 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x0000009f,// 159 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000bb,// 187 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000cd,// 205 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000b1,// 177 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000c5,// 197 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000ad,// 173 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000000a1,// 161 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000d3,// 211 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000000a2,// 162 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000d1,// 209 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000000d3,// 211 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000d0,// 208 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000000a7,// 167 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000a9,// 169 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000000b9,// 185 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000000ae,// 174 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000b1,// 177 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000b2,// 178 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000bd,// 189 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000000d1,// 209 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000d0,// 208 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000c6,// 198 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000d1,// 209 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000bf,// 191 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000000c1,// 193 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000d3,// 211 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000000c1,// 193 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000dc,// 220 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000000ae,// 174 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000a1,// 161 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000ab,// 171 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000ac,// 172 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000bd,// 189 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000037a,// 890 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000359,// 857 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000352,// 850 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x0000034f,// 847 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000075,// 117 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x0000006c,// 108 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000058,// 88 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007c,// 124 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000034,// 52 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000033,// 51 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000002b,// 43 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000032,// 50 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000050,// 80 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000062,// 98 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000043,// 67 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000058,// 88 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000028,// 40 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000028,// 40 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000036,// 54 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000044,// 68 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x00000042,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000026,// 38 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000002c,// 44 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x0000002a,// 42 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x00000032,// 50 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000029,// 41 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x0000002c,// 44 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000048,// 72 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000003e,// 62 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x0000003b,// 59 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x0000003b,// 59 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000050,// 80 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003d,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x00000030,// 48 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x0000002e,// 46 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000002f,// 47 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000033,// 51 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0 - - .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { - 0,40,40,40,40,40,40,40,40,40,40, - 40,40,40,40,40,40,40,40,40,40,40, - 40,40,40,40,40,40,40,40,40,40,40, - 40,40,40,40,50,40,50,40,50,40,50},//total 44 - .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { - 0,32,32,32,32,32,32,32,32,32,32, - 32,32,32,32,32,32,32,32,32,32,32, - 32,32,32,32,32,32,32,32,32,32,32, - 32,32,32},//total 36 - .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { - (0 << 7) | 6, (0 << 7) | 6, (1 << 7) | 5, (0 << 7) | 0, - (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, - (1 << 7) | 10, (1 << 7) | 10, (1 << 7) | 10, (1 << 7) | 10, - (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, - }, - - //pinmux setting - .cfg_board_common_setting. ac_pinmux = { - 0, 0, 0, 1, 2, 3, - 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, - }, - .cfg_board_common_setting. ddr_dqs_swap = 0, - - .cfg_board_common_setting. ddr_dq_remap = { - 0,1,2,3,4,5,6,7, - 8,9,10,11,12,13,14,15, - 16,17,18,19,20,21,22,23, - 24,25,26,27,28,29,30,31, - 32,33,34,35 - },//d0-d31 dm0 dm1 dm2 dm3 - - .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start - .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), - .cfg_board_common_setting. timming_struct_version = 0, - .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), - .cfg_board_common_setting. timming_struct_real_size = 0, //0 - .cfg_board_common_setting. ddr_func = 0, - .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, - .cfg_board_common_setting. dram_cs0_base_add = 0, - .cfg_board_common_setting. dram_cs1_base_add = 0, - - .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE, - .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, - .cfg_board_common_setting. org_tdqs2dq = 0, - .cfg_board_common_setting. reserve1_test_function = {0}, - .cfg_board_common_setting. ddr_vddee_setting = {0}, - - //DDR frequercy 2 - .cfg_board_SI_setting_ps[1].DRAMFreq = 600, - .cfg_board_SI_setting_ps[1].PllBypassEn = 0, - .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, - .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, - .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[1].reserve2 = 0, - .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, - .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, - .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, - .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, - .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { - 128,128,128,128,128,128,128,128, - 128,128,128,128,128,128,128,128, - 128,128,128,128,128,128,128,128, - 128,128,128,128,128,128,128,128, - 128,128,128,128, - },//total 36 - - .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { - 128,128,128,128,128,128,128,128, - 128,128,128,128,128,128,128,128, - 128,128,128,128,128,128,128,128, - 128,128,128,128,128,128,128,128, - 128,128,128,128, - },//total 36 - .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, - //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, - .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50, - 50,50,50,50,50,50,50,50,}, - - //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 - .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 - //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 - .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 - .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0},//total 72 - .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { - 40,40,40,40,40,40,40,40,40,40,40, - 40,40,40,40,40,40,40,40,40,40,40, - 40,40,40,40,40,40,40,40,40,40,40, - 40,40,40,40,40,40,40,40,40,40,40},//total 44 - .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { - 32,32,32,32,32,32,32,32,32,32,32, - 32,32,32,32,32,32,32,32,32,32,32, - 32,32,32,32,32,32,32,32,32,32,32, - 32,32,32},//total 36 - - .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end -}, -#endif //end ENABLE_DDR4 -#if ENABLE_DDR3 -{ - .cfg_board_common_setting.timming_magic = 0, - .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, - .cfg_board_common_setting.timming_struct_version = 0, - .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), - .cfg_board_common_setting.timming_struct_real_size = 0, //0 - .cfg_board_common_setting.fast_boot = {0}, - .cfg_board_common_setting.ddr_func = 0, - .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, - .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR3, - .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0, - .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, - .cfg_board_common_setting.dram_cs0_base_add = 0, - .cfg_board_common_setting.dram_cs1_base_add = 0, - .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB, - .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, - .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, - .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE, - .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, - .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, - .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, - .cfg_board_common_setting.org_tdqs2dq = 0, - .cfg_board_common_setting.reserve1_test_function = {0}, - .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT, - .cfg_board_common_setting.ac_pinmux = - { - 0, 0, 0, 1, 2, 3, 0, 1, - 2, 3, 4, 5, 6, 7, 8, 9, - 10, 11, 12, 13, 14, 15, 0, 0, - 0, 0, 20, 21, 22, 0, 0, 25, - 26, 27, 0 - }, - .cfg_board_common_setting.ddr_dqs_swap = 0, - .cfg_board_common_setting.ddr_dq_remap = { - 0, 1, 2, 3, 4, 5, 6, 7, - 8, 9, 10, 11, 12, 13, 14, 15, - 16, 17, 18, 19, 20, 21, 22, 23, - 24, 25, 26, 27, 28, 29, 30, 31, - 32, 33, 34, 35, - }, //d0-d31 dm0 dm1 dm2 dm3 - .cfg_board_common_setting.ddr_vddee_setting = {0}, - .cfg_board_SI_setting_ps[0].DRAMFreq = 912, - .cfg_board_SI_setting_ps[0].PllBypassEn = 0, - .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM, - .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[0].reserve2 = 0, - .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, - .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, - .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, - .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, - .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { - 128, 128, 128 - 20, 128, 128, 128, 128, 128, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, - }, //total 36 - - .cfg_ddr_training_delay_ps[0].ac_trace_delay = { - 128, 128, 128 - 20, 128, 128, 128, 128, 128, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, 384, 384, 384, 384, - 384, 384, 384, 384, - }, //total 36 - .cfg_ddr_training_delay_ps[0].write_dqs_delay = { - 128 - 1, 128 - 1, 128 + 48, 128 + 58, 128 + 32, 128 + 32, 128 + 32, 128 + 32 - }, - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay = { - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, - 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, - 128 + 128, 128 + 128, 128 + 128, 128 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, - }, - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay = { - 896, 896, 896, 896, 896, 896, 896, 896 - }, //total 8 - .cfg_ddr_training_delay_ps[0].read_dqs_delay = { - 64, 64, 50, 40, 64, 64, 64, 64 - }, //total 8 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay = { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 - }, //total 72 - .cfg_ddr_training_delay_ps[0].soc_bit_vref = { - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32 + 5, 32, 32 + 5, - 32, 32 + 5, 32, 32 + 5 - }, - .cfg_ddr_training_delay_ps[0].dram_bit_vref = { - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32 - }, //total 36 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[0] = 0x0000007d,// 125 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[1] = 0x00000091,// 145 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[2] = 0x00000091,// 145 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[3] = 0x0000009b,// 155 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[4] = 0x000000a0,// 160 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[5] = 0x000000a0,// 160 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[6] = 0x000000a0,// 160 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[7] = 0x000000a0,// 160 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0] = 0x000000c2,// 194 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1] = 0x000000b0,// 176 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2] = 0x000000af,// 175 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3] = 0x000000b0,// 176 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4] = 0x000000c0,// 192 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5] = 0x000000c3,// 195 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6] = 0x000000b4,// 180 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7] = 0x000000be,// 190 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8] = 0x000000ba,// 186 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9] = 0x000000c1,// 193 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10] = 0x000000d5,// 213 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11] = 0x000000c1,// 193 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12] = 0x000000d0,// 208 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13] = 0x000000cc,// 204 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14] = 0x000000c3,// 195 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15] = 0x000000be,// 190 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16] = 0x000000c0,// 192 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17] = 0x000000c8,// 200 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18] = 0x000000e0,// 224 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19] = 0x000000e5,// 229 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20] = 0x000000e2,// 226 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21] = 0x000000ec,// 236 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22] = 0x000000ec,// 236 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23] = 0x000000e7,// 231 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24] = 0x000000e4,// 228 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25] = 0x000000e9,// 233 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26] = 0x000000e6,// 230 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27] = 0x000000eb,// 235 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28] = 0x000000f5,// 245 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29] = 0x000000e7,// 231 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30] = 0x000000fd,// 253 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31] = 0x000000e8,// 232 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32] = 0x000000e4,// 228 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33] = 0x000000ee,// 238 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34] = 0x000000ec,// 236 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35] = 0x000000f2,// 242 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0] = 0x0000038c,// 908 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1] = 0x0000037a,// 890 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2] = 0x0000039a,// 922 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3] = 0x00000395,// 917 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[0] = 0x0000007f-0x30,// 127 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[1] = 0x0000007d-0x30,// 125 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[2] = 0x0000006d-0x30,// 109 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[3] = 0x0000006f-0x30,// 111 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[4] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[5] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[6] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[7] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0] = 0x00000048-0x30,// 72 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1] = 0x00000044-0x30,// 68 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2] = 0x00000038-0x30,// 56 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3] = 0x0000003b-0x30,// 59 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4] = 0x00000049-0x30,// 73 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5] = 0x0000004b-0x30,// 75 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6] = 0x0000003b-0x30,// 59 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7] = 0x00000049-0x30,// 73 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9] = 0x00000040-0x30,// 64 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10] = 0x00000052-0x30,// 82 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11] = 0x00000039-0x30,// 57 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12] = 0x00000040-0x30,// 64 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13] = 0x00000045-0x30,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14] = 0x00000042-0x30,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15] = 0x00000034-0x30,// 52 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16] = 0x0000003c-0x30,// 60 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17] = 0x00000086-0x30,// 134 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18] = 0x0000003f-0x30,// 63 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19] = 0x00000048-0x30,// 72 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20] = 0x00000037-0x30,// 55 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21] = 0x00000048-0x30,// 72 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22] = (0x0000004e)-0x30,// 78 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23] = 0x00000044-0x30,// 68 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24] = 0x00000042-0x30,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25] = 0x00000047-0x30,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26] = 0x0000007f-0x30,// 127 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27] = 0x00000040-0x30,// 64 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28] = 0x00000052-0x30,// 82 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29] = 0x0000003d-0x30,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30] = (0x0000004e)-0x30,// 78 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31] = 0x0000003c-0x30,// 60 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32] = (0x0000003e)-0x30,// 62 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33] = 0x0000003f-0x30,// 63 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34] = 0x0000004c-0x30,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35] = 0x00000091-0x30,// 145 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70] = 0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71] = 0x00000000,// 0 - - .cfg_ddr_training_delay_ps[0].reserve_training_parameter = {0}, - .cfg_board_SI_setting_ps[1].DRAMFreq = 667, - .cfg_board_SI_setting_ps[1].PllBypassEn = 0, - .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, - .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, - .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[1].reserve2 = 0, - .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, - .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, - .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, - .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, - .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, - }, //total 36 - .cfg_ddr_training_delay_ps[1].ac_trace_delay = { - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, - }, //total 36 - .cfg_ddr_training_delay_ps[1].write_dqs_delay = { - 0, 0, 0, 0, 0, 0, 0, 0 - }, - .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50 - }, - .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { - 192, 192, 192, 192, 192, 192, 192, 192 - }, //total 8 - .cfg_ddr_training_delay_ps[1].read_dqs_delay = { - 64, 64, 64, 64, 64, 64, 64, 64 - }, //total 8 - .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 - }, //total 72 - .cfg_ddr_training_delay_ps[1].soc_bit_vref = { - 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40 - }, //total 44 - .cfg_ddr_training_delay_ps[1].dram_bit_vref = { - 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32 - }, //total 36 - .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0}, -}, -#endif - -#if ENABLE_LPDDR4 //LPDDR4 rank0,timing_config -{ - .cfg_board_common_setting.timming_magic = 0, - .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, - .cfg_board_common_setting.timming_struct_version = 0, - .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), - .cfg_board_common_setting.timming_struct_real_size = 0, //0 - .cfg_board_common_setting.fast_boot = { 0 }, - .cfg_board_common_setting.ddr_func = 0, - .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, - .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_LPDDR4, - .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH01, - .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, - .cfg_board_common_setting.dram_cs0_base_add = 0, - .cfg_board_common_setting.dram_cs1_base_add = 0, - .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB, - .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, - .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, - .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_1T_MODE, - .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, - .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, //DDR_WRITE_READ_DBI_DISABLE , - .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, - .cfg_board_common_setting.org_tdqs2dq = 0, - .cfg_board_common_setting.reserve1_test_function = { 0 }, - .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT, -#ifdef CONFIG_DDR_WINDOWING_BOOT - .cfg_board_common_setting.fast_boot[0] = 0x1, - .cfg_board_common_setting.fast_boot[3] = 0x46, -#endif - //lpddr4 ac pinmux - .cfg_board_common_setting.ac_pinmux = { - 0, 0, 0, 1, 0, 1, 1, 3, - 0, 4, 4, 2, 0, 0, 1, 0, - 2, 0, 0, 0, 0, 3, 0, 0, - 0, 0, 5, 5, 0, 0, 0, 0, - 0, 0, - }, - .cfg_board_common_setting.ddr_dqs_swap = 0, - - .cfg_board_common_setting.ddr_dq_remap = { - 1, 0, 3, 2, 7, 5, 6, 4, - 9, 15, 13, 14, 10, 11, 12, 8, - 21, 19, 20, 18, 17, 16, 22, 23, - 25, 26, 24, 27, 31, 29, 30, 28, - 32, 33, 34, 35 - }, //d0-d31 dm0 dm1 dm2 dm3 - - .cfg_board_common_setting.ddr_vddee_setting = { 0 }, - .cfg_board_SI_setting_ps[0].DRAMFreq = 1320, - .cfg_board_SI_setting_ps[0].PllBypassEn = 0, - .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_60_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_LPDDR4_DRV_40_OHM, - .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_LPDDR4_ODT_60_OHM, - .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_LPDDR4_AC_ODT_80_OHM, - .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[0].reserve2 = 0, - .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, //3000/11, - .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, //170, - .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, //280, //330 - .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 }, - .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { - 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 0 + 128, //0,0,0,0,0,0,0,0, - 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128, 128 + 20 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - }, //total 36 - - .cfg_ddr_training_delay_ps[0].ac_trace_delay = { - 64 + 128, 64 + 128, 64 + 128-64, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 128 + 128, //0,0,0,0,0,0,0,0, - 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128-40, 128 + 20 + 128-10, 128 + 0 + 128, 128 + 0 + 128+10, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, - }, //total 36 - .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 }, - - .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x000000af,// 175 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x000000cd,// 205 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x000000aa,// 170 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x000000cd,// 205 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x000000af,// 175 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x000000cd,// 205 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x000000aa,// 170 - .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x000000cd,// 205 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x000001cd,// 461 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x000001cc,// 460 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x000001ba,// 442 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000001d8,// 472 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000001e1,// 481 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000001ce,// 462 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000001c6,// 454 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000001d0,// 464 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000001cc,// 460 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000001d9,// 473 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000001da,// 474 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000001c4,// 452 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000001d5,// 469 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000001ea,// 490 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000001e9,// 489 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000001e2,// 482 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000001ea,// 490 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000001d5,// 469 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000001c6,// 454 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000001ce,// 462 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000001b5,// 437 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000001c7,// 455 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000001d3,// 467 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000001d1,// 465 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000001c4,// 452 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000001eb,// 491 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000001d1,// 465 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000001f7,// 503 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000001d8,// 472 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000001cf,// 463 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000001d3,// 467 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000001c9,// 457 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000001de,// 478 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x000001cd,// 461 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x000001cc,// 460 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x000001ba,// 442 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x000001d8,// 472 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x000001e1,// 481 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x000001ce,// 462 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x000001c6,// 454 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x000001d0,// 464 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x000001cc,// 460 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x000001d9,// 473 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x000001da,// 474 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x000001c4,// 452 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x000001d5,// 469 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x000001ea,// 490 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x000001e9,// 489 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x000001e2,// 482 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x000001ea,// 490 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x000001d5,// 469 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x000001c6,// 454 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x000001ce,// 462 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x000001b5,// 437 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x000001c7,// 455 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x000001d3,// 467 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x000001d1,// 465 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x000001c4,// 452 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x000001d7,// 471 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x000001eb,// 491 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x000001d1,// 465 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x000001f7,// 503 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x000001d8,// 472 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x000001cf,// 463 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x000001d3,// 467 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x000001c9,// 457 - .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x000001de,// 478 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x000003ab,// 939 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000383,// 899 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000395,// 917 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x00000378,// 888 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x000003ab,// 939 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000383,// 899 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000395,// 917 - .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000378,// 888 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x0000007e,// 126 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x00000088,// 136 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000070,// 112 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007a,// 122 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x0000007e,// 126 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000088,// 136 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000070,// 112 - .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x0000007a,// 122 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000044,// 68 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000051,// 81 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x00000036,// 54 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000054,// 84 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x0000003d,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000045,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000051,// 81 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000037,// 55 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x0000003d,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000052,// 82 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x0000005b,// 91 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x0000004c,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000005a,// 90 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x0000004b,// 75 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000042,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x0000004f,// 79 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000030,// 48 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000042,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000004c,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000041,// 65 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000058,// 88 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000045,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000041,// 65 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000056,// 86 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003f,// 63 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000055,// 85 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x0000003e,// 62 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000034,// 52 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x00000031,// 49 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000036,// 54 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000040,// 64 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000044,// 68 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000051,// 81 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000036,// 54 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000054,// 84 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x0000003d,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000045,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000047,// 71 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000051,// 81 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000037,// 55 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x0000003d,// 61 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000052,// 82 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x0000005b,// 91 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x0000004c,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x0000005a,// 90 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x0000004b,// 75 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000042,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x0000004f,// 79 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000030,// 48 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000046,// 70 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000042,// 66 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x0000004c,// 76 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000041,// 65 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000058,// 88 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000045,// 69 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000041,// 65 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000056,// 86 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x0000003f,// 63 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000055,// 85 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x0000003e,// 62 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000034,// 52 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000031,// 49 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000036,// 54 - .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000040,// 64 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[0]=0,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[1]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[2]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[3]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[4]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[5]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[6]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[7]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[8]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[9]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[10]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[11]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[12]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[13]=0x00000013,// 19 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[14]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[15]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[16]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[17]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[18]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[19]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[20]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[21]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[22]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[23]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[24]=0x00000016,// 22 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[25]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[26]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[27]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[28]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[29]=0x00000014,// 20 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[30]=0x00000016,// 22 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[31]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[32]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[33]=0x00000016,// 22 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[34]=0x00000015,// 21 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[35]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[36]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[37]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[38]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[39]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[40]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[41]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[42]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].soc_bit_vref[43]=0x00000010,// 16 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[0]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[1]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[2]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[3]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[4]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[5]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[6]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[7]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[8]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[9]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[10]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[11]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[12]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[13]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[14]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[15]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[16]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[17]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[18]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[19]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[20]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[21]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[22]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[23]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[24]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[25]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[26]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[27]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[28]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[29]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[30]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[31]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[32]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[33]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[34]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].dram_bit_vref[35]=0x00000000,// 0 - .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { - (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, - (1 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, - (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, - (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, - }, - .cfg_board_SI_setting_ps[1].DRAMFreq = 667, - .cfg_board_SI_setting_ps[1].PllBypassEn = 0, - .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, - .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, - .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, - .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, - .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, - .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, - .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, - .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, - .cfg_board_SI_setting_ps[1].reserve2 = 0, - .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, - .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, - .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, - .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, - .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 }, - .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, - }, //total 36 - .cfg_ddr_training_delay_ps[1].ac_trace_delay = { - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, 128, 128, 128, 128, - 128, 128, 128, 128, - }, //total 36 - - .cfg_ddr_training_delay_ps[1].write_dqs_delay = { - 0, 0, 0, 0, 0, 0, 0, 0 - }, - .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - 50, 50, 50, 50, 50, 50, 50, 50, - }, - .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { - 192, 192, 192, 192, 192, 192, 192, 192 - }, //total 8 - .cfg_ddr_training_delay_ps[1].read_dqs_delay = { - 64, 64, 64, 64, 64, 64, 64, 64 - }, //total 8 - .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 - }, //total 72 - .cfg_ddr_training_delay_ps[1].soc_bit_vref = { - 0, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40 - }, //total 44 - .cfg_ddr_training_delay_ps[1].dram_bit_vref = { - 0, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32 - }, //total 36 - .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 }, -}, -#endif -}; -//ddr timing end - -pll_set_t __pll_setting = { - .cpu_clk = CPU_CLK / 24 * 24, -#ifdef CONFIG_PXP_EMULATOR - .pxp = 1, -#else - .pxp = 0, -#endif - .spi_ctrl = 0, - .lCustomerID = AML_CUSTOMER_ID, - .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */ - .log_ctrl = (1 << 7) | /* (1<<7), print bl2 log into buffer */ -#ifdef CONFIG_SILENT_CONSOLE - (1<<6), /* do not print log buffer */ -#else - (0<<6), /* print log buffer before run bl31 */ -#endif - .ddr_timming_save_mode = 1, -}; - -ddr_reg_t __ddr_reg[] = { - /* demo, user defined override register */ - {0xaabbccdd, 0, 0, 0, 0, 0}, - {0x11223344, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0}, -}; - - - -#define VCCK_VAL AML_VCCK_INIT_VOLTAGE -#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE -/* VCCK PWM table */ -#if (VCCK_VAL == 1039) - #define VCCK_VAL_REG 0x00000022 -#elif (VCCK_VAL == 1029) - #define VCCK_VAL_REG 0x00010021 -#elif (VCCK_VAL == 1019) - #define VCCK_VAL_REG 0x00020020 -#elif (VCCK_VAL == 1009) - #define VCCK_VAL_REG 0x0003001f -#elif (VCCK_VAL == 999) - #define VCCK_VAL_REG 0x0004001e -#elif (VCCK_VAL == 989) - #define VCCK_VAL_REG 0x0005001d -#elif (VCCK_VAL == 979) - #define VCCK_VAL_REG 0x0006001c -#elif (VCCK_VAL == 969) - #define VCCK_VAL_REG 0x0007001b -#elif (VCCK_VAL == 959) - #define VCCK_VAL_REG 0x0008001a -#elif (VCCK_VAL == 949) - #define VCCK_VAL_REG 0x00090019 -#elif (VCCK_VAL == 939) - #define VCCK_VAL_REG 0x000a0018 -#elif (VCCK_VAL == 929) - #define VCCK_VAL_REG 0x000b0017 -#elif (VCCK_VAL == 919) - #define VCCK_VAL_REG 0x000c0016 -#elif (VCCK_VAL == 909) - #define VCCK_VAL_REG 0x000d0015 -#elif (VCCK_VAL == 899) - #define VCCK_VAL_REG 0x000e0014 -#elif (VCCK_VAL == 889) - #define VCCK_VAL_REG 0x000f0013 -#elif (VCCK_VAL == 879) - #define VCCK_VAL_REG 0x00100012 -#elif (VCCK_VAL == 869) - #define VCCK_VAL_REG 0x00110011 -#elif (VCCK_VAL == 859) - #define VCCK_VAL_REG 0x00120010 -#elif (VCCK_VAL == 849) - #define VCCK_VAL_REG 0x0013000f -#elif (VCCK_VAL == 839) - #define VCCK_VAL_REG 0x0014000e -#elif (VCCK_VAL == 829) - #define VCCK_VAL_REG 0x0015000d -#elif (VCCK_VAL == 819) - #define VCCK_VAL_REG 0x0016000c -#elif (VCCK_VAL == 809) - #define VCCK_VAL_REG 0x0017000b -#elif (VCCK_VAL == 799) - #define VCCK_VAL_REG 0x0018000a -#elif (VCCK_VAL == 789) - #define VCCK_VAL_REG 0x00190009 -#elif (VCCK_VAL == 779) - #define VCCK_VAL_REG 0x001a0008 -#elif (VCCK_VAL == 769) - #define VCCK_VAL_REG 0x001b0007 -#elif (VCCK_VAL == 759) - #define VCCK_VAL_REG 0x001c0006 -#elif (VCCK_VAL == 749) - #define VCCK_VAL_REG 0x001d0005 -#elif (VCCK_VAL == 739) - #define VCCK_VAL_REG 0x001e0004 -#elif (VCCK_VAL == 729) - #define VCCK_VAL_REG 0x001f0003 -#elif (VCCK_VAL == 719) - #define VCCK_VAL_REG 0x00200002 -#elif (VCCK_VAL == 709) - #define VCCK_VAL_REG 0x00210001 -#elif (VCCK_VAL == 699) - #define VCCK_VAL_REG 0x00220000 -#else - #error "VCCK val out of range\n" -#endif - -/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/ -#ifdef CONFIG_I2C_REGULATOR -#if (VDDEE_VAL == 711) - #define VDDEE_VAL_REG 0xb -#elif (VDDEE_VAL == 721) - #define VDDEE_VAL_REG 0xc -#elif (VDDEE_VAL == 731) - #define VDDEE_VAL_REG 0xd -#elif (VDDEE_VAL == 741) - #define VDDEE_VAL_REG 0xe -#elif (VDDEE_VAL == 751) - #define VDDEE_VAL_REG 0xf -#elif (VDDEE_VAL == 761) - #define VDDEE_VAL_REG 0x10 -#elif (VDDEE_VAL == 771) - #define VDDEE_VAL_REG 0x11 -#elif (VDDEE_VAL == 781) - #define VDDEE_VAL_REG 0x12 -#elif (VDDEE_VAL == 791) - #define VDDEE_VAL_REG 0x13 -#elif (VDDEE_VAL == 801) - #define VDDEE_VAL_REG 0x14 -#elif (VDDEE_VAL == 811) - #define VDDEE_VAL_REG 0x15 -#elif (VDDEE_VAL == 821) - #define VDDEE_VAL_REG 0x16 -#elif (VDDEE_VAL == 831) - #define VDDEE_VAL_REG 0x17 -#elif (VDDEE_VAL == 841) - #define VDDEE_VAL_REG 0x18 -#elif (VDDEE_VAL == 851) - #define VDDEE_VAL_REG 0x19 -#elif (VDDEE_VAL == 861) - #define VDDEE_VAL_REG 0x1a -#elif (VDDEE_VAL == 871) - #define VDDEE_VAL_REG 0x1b -#elif (VDDEE_VAL == 881) - #define VDDEE_VAL_REG 0x1c -#elif (VDDEE_VAL == 891) - #define VDDEE_VAL_REG 0x1d -#else - #error "VDDEE val out of range\n" -#endif - -#else - -#if (VDDEE_VAL == 711) - #define VDDEE_VAL_REG 0x120000 -#elif (VDDEE_VAL == 721) - #define VDDEE_VAL_REG 0x110001 -#elif (VDDEE_VAL == 731) - #define VDDEE_VAL_REG 0x100002 -#elif (VDDEE_VAL == 741) - #define VDDEE_VAL_REG 0xf0003 -#elif (VDDEE_VAL == 751) - #define VDDEE_VAL_REG 0xe0004 -#elif (VDDEE_VAL == 761) - #define VDDEE_VAL_REG 0xd0005 -#elif (VDDEE_VAL == 771) - #define VDDEE_VAL_REG 0xc0006 -#elif (VDDEE_VAL == 781) - #define VDDEE_VAL_REG 0xb0007 -#elif (VDDEE_VAL == 791) - #define VDDEE_VAL_REG 0xa0008 -#elif (VDDEE_VAL == 801) - #define VDDEE_VAL_REG 0x90009 -#elif (VDDEE_VAL == 811) - #define VDDEE_VAL_REG 0x8000a -#elif (VDDEE_VAL == 821) - #define VDDEE_VAL_REG 0x7000b -#elif (VDDEE_VAL == 831) - #define VDDEE_VAL_REG 0x6000c -#elif (VDDEE_VAL == 841) - #define VDDEE_VAL_REG 0x5000d -#elif (VDDEE_VAL == 851) - #define VDDEE_VAL_REG 0x4000e -#elif (VDDEE_VAL == 861) - #define VDDEE_VAL_REG 0x3000f -#elif (VDDEE_VAL == 871) - #define VDDEE_VAL_REG 0x20010 -#elif (VDDEE_VAL == 881) - #define VDDEE_VAL_REG 0x10011 -#elif (VDDEE_VAL == 891) - #define VDDEE_VAL_REG 0x12 -#else - #error "VDDEE val out of range\n" -#endif -#endif - -/* for PWM use */ -/* - * GPIOE_0 PWM_A VDDEE_PWM - * - * GPIOE_1 PWM_B VCCK_PWM - */ -/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */ -#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400) -#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400) - -/* pwm clock and pwm controller */ -#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800) -#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400) -#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400) -#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400) - -bl2_reg_t __bl2_reg[] = { -#ifdef CONFIG_I2C_REGULATOR - /* demo, user defined override register */ - {0, 0, 0xffffffff, 0, 0, 0}, - {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, - {PWMAB_MISC_REG_AB, 0x1 << 1, 0x1 << 1, 0, BL2_INIT_STAGE_1, 0}, - /* Set GPIOA_5 low */ - {PADCTRL_GPIOA_O, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_GPIOA_OEN, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, - /* Set GPIOD_10 low */ - {PADCTRL_GPIOD_O, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, - /* Set GPIOX_11 low */ - {PADCTRL_GPIOX_O, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_GPIOX_OEN, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, - /* set pwm A and pwm B clock rate to 24M, enable them */ - {CLKTREE_PWM_CLK_AB_CTRL, 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, - /* set GPIOE_0 GPIOE_1 drive strength to 3*/ - {PADCTRL_GPIOE_DS, 0x3 << 2, 0x3 << 2, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, -#ifdef CONFIG_PDVFS_ENABLE - /* table_id, ee_voltage, ...... */ - {1, 0x11, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, - {2, 0x14, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, - {3, 0x16, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, -#else - {0x0, VDDEE_VAL_REG, 0x0, 0, BL2_INIT_STAGE_I2C_REGULATOR, 0}, -#endif -#else - /* demo, user defined override register */ - {0, 0, 0xffffffff, 0, 0, 0}, -#ifdef CONFIG_PDVFS_ENABLE - {PWMAB_PWM_A, 0x000c0006, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, - {PWMAB_PWM_A, 0x00090009, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, - {PWMAB_PWM_A, 0x0007000b, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, -#else - {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, -#endif - {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, - {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0}, - /* enable vddcpu dc-dc, set GPIOD_10 high */ - {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, - /* set pwm A and pwm B clock rate to 24M, enable them */ - {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, - /* set GPIOE_0 GPIOE_1 drive strength to 3*/ - {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0}, - {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, -#endif -};
diff --git a/board/amlogic/configs/c2_2rs4_p1.h b/board/amlogic/configs/c2_2rs4_p1.h deleted file mode 100644 index 79d08c4..0000000 --- a/board/amlogic/configs/c2_2rs4_p1.h +++ /dev/null
@@ -1,464 +0,0 @@ - -/* - * Copyright (C) 2015 Amlogic, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -*/ - -#ifndef __BOARD_CFG_H__ -#define __BOARD_CFG_H__ - -#include <asm/arch/cpu.h> - -/* UBOOT Facotry usb burning config */ -#ifndef AML_DISABLE_UPDATE_MODE -#define CONFIG_AML_V3_FACTORY_BURN 1 -#define CONFIG_AML_V3_USB_TOOl 1 -#define CONFIG_USB_GADGET_DOWNLOAD 1 -#define CONFIG_FASTBOOT_DWC_PCD 1 -#define CONFIG_USB_DEVICE_V2 1 -#endif - -/* enable command line for bringup */ -#ifdef CONFIG_ENABLE_UBOOT_CLI -#define CONFIG_CLI_ENABLED 1 -#endif - -/* - * platform power init config - */ - -#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage -#define AML_VDDEE_INIT_VOLTAGE 801 // VDDEE power up voltage -/*if CONFIG_PDVFS_ENABLE is defined, AML_VCCK_INIT_VOLTAGE will be invalid*/ -#define CONFIG_PDVFS_ENABLE - - -/* SMP Definitinos */ -#define CPU_RELEASE_ADDR secondary_boot_func - -/* Bootloader Control Block function - That is used for recovery and the bootloader to talk to each other - */ -#if 0 -#define CONFIG_BOOTLOADER_CONTROL_BLOCK -#endif - -/* Serial config */ -#define CONFIG_CONS_INDEX 2 -#define CONFIG_BAUDRATE 115200 - -/* Enable ir remote wake up for bl30 */ -#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power -#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+ -#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch- -#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power -#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04 -#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF -#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF -#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF -#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF - -/*config the default parameters for adc power key*/ -#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ -#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ - -#define CONFIG_BOOTLOADER_CONTROL_BLOCK - -#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition -#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}" -#else -#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}" -#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition - -#ifdef AML_ENABLE_PRODUCTION_MODE -#define JUDGE_MODE "echo this is production mode;" -#define CONFIG_AML_PRODUCT_MODE 1 -#ifdef CONFIG_FASTBOOT -#define CONFIG_NO_FASTBOOT_FLASHING 1 -#endif //CONFIG_FASTBOOT -#ifdef CONFIG_MESON_SERIAL -#define CONFIG_DISABLE_AML_SERIAL 1 -#endif //CONFIG_MESON_SERIAL -#define USB_BURNING_OPTION "echo productmode" -#else //AML_ENABLE_PRODUCTION_MODE -#define JUDGE_MODE "echo this is not production mode;" -#define CONFIG_CMD_BOOTD 1 -#if (defined(CONFIG_ARM) && !defined(CONFIG_ARM64)) -#define CONFIG_CMD_BOOTZ 1 -#endif //defined(CONFIG_ARM) && !defined(CONFIG_ARM64) -#ifdef CONFIG_ARM64 -#define CONFIG_CMD_BOOTI 1 -#endif //CONFIG_ARM64 -#define CONFIG_CMD_MEMORY 1 -#define CONFIG_CMD_SOURCE 1 -#ifdef CONFIG_MISC -#define CONFIG_CMD_JTAG 1 -#endif //CONFIG_MISC -#ifdef CONFIG_CMD_BOOTI -#define CONFIG_CMD_LZMADEC 1 -#define CONFIG_CMD_UNZIP 1 -#define CONFIG_LZMA 1 -#endif //CONFIG_CMD_BOOTI -#define USB_BURNING_OPTION "adnl" - -#endif //AML_ENABLE_PRODUCTION_MODE - -/* args/envs */ -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_EXTRA_ENV_SETTINGS \ - "firstboot=1\0"\ - "jtag=disable\0"\ - "loadaddr=0x00020000\0"\ - "loadaddr_kernel=0x01080000\0"\ - "loadaddr_dspa=0x06000000\0"\ - "otg_device=1\0" \ - "usb_burning=" USB_BURNING_OPTION "\0" \ - "fdt_high=0x20000000\0"\ - "EnableSelinux=enforcing\0" \ - "boot_part=boot_a\0"\ - "active_slot=_a\0"\ - "Irq_check_en=0\0"\ - "fatload_dev=usb\0"\ - "initargs="\ - "\0"\ - "upgrade_check="\ - "echo recovery_status=${recovery_status};"\ - "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\ - "run storeargs; run recovery_from_flash;"\ - "else fi;"\ - "echo upgrade_step=${upgrade_step}; "\ - "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\ - "\0"\ - "run_dspa="\ - "unzip 0x6400000 ${loadaddr_dspa};"\ - "dspset 0 1 0;dspset 0 1 1;dsprun 0 ${loadaddr_dspa}; "\ - "\0"\ - "storeargs="\ - "get_rebootmode;"\ - "get_chiptype;"\ - "get_cpu_rev;"\ - "get_ee_vol;"\ - "if test ${reboot_mode} = fastboot; then "\ - "setenv reboot_mode warm_reboot;"\ - "fi;"\ - "setenv bootargs ${initargs} otg_device=${otg_device} "\ - "gpt " \ - "androidboot.reboot_mode=${reboot_mode} "\ - "hw_id=${hw_id} "\ - "boot_ac_voltage=${boot_ac_voltage} "\ - "chip_type=${chip_type} "\ - "cpu_rev=${cpu_rev} "\ - "vddee=${vddee_voltage} "\ - "irq_check_en=${Irq_check_en} "\ - "androidboot.hardware="__stringify(BOARD_NAME)" "\ - "androidboot.bl2_boot_part=${bl2_part} "\ - "androidboot.slot_suffix=${active_slot} "\ - "androidboot.firstboot=${firstboot} jtag=${jtag}; "\ - "setenv bootargs ${bootargs};"\ - "\0"\ - "switch_bootmode="\ - "get_rebootmode;"\ - "echo reboot_mode:${reboot_mode};"\ - "if test ${reboot_mode} = factory_boot; then " \ - "setenv bootargs ${bootargs} androidboot.real_reboot_mode=${real_reboot_mode};"\ - "if imgread kernel system_b ${loadaddr_kernel}; then " \ - "bootm ${loadaddr_kernel};"\ - "fi;" \ - "else if test ${reboot_mode} = update; then "\ - "run update;"\ - "else if test ${reboot_mode} = delayed_reboot; then "\ - "delayed_reboot;"\ - "else if test ${reboot_mode} = quiescent; then "\ - "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ - "else if test ${reboot_mode} = cold_boot; then "\ - "fi;fi;fi;fi;fi;"\ - "\0" \ - "storeboot="\ - JUDGE_MODE \ - "setenv loadaddr ${loadaddr_kernel};"\ - "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ - "echo try upgrade as booting failure; run update;"\ - "\0" \ - "update="\ - /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ - "run usb_burning; "\ - "run recovery_from_udisk;"\ - "\0"\ - "recovery_from_fat_dev="\ - "setenv loadaddr ${loadaddr_kernel};"\ - "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img 0x10000000 0; then "\ - "bootm ${loadaddr};fi;"\ - "\0"\ - "recovery_from_udisk="\ - "setenv fatload_dev usb;"\ - "if usb start 0; then run recovery_from_fat_dev; fi;"\ - "\0"\ - "bcb_cmd="\ - "get_valid_slot;"\ - "\0"\ - "ddr_windowing_boot="\ - "ddr_auto_fast_boot_check 6;"\ - "\0"\ - "oqc_check="\ - "setenv test_mode false;"\ - "setenv fatload_dev usb;"\ - "if usb start 0; then "\ - "if fatload ${fatload_dev} 0 ${loadaddr} OQC.txt 0x100000 0; then "\ - "setenv test_mode true;"\ - "fi;"\ - "fi;"\ - "setenv bootargs ${bootargs} androidboot.test_mode=${test_mode};"\ - "\0"\ - "upgrade_and_oqc_key_check="\ - "if gpio input GPIOX_12; then "\ - "echo RESET KEY pressed;"\ - "setenv boot_external_image 1;"\ - "run recovery_from_udisk;"\ - "setenv boot_external_image 0;"\ - "run oqc_check;"\ - "else "\ - "echo RESET KEY not pressed;"\ - "fi;"\ - "\0"\ - "cmdline_keys="\ - "setenv usid 1234567890; setenv region_code US;"\ - "if keyman init 0x1234; then "\ - "if keyman read usid ${loadaddr} str; then fi;"\ - "if keyman read region_code ${loadaddr} str; then fi;"\ - "if keyman read mac ${loadaddr} str; then "\ - "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ - "fi;"\ - "if keyman read deviceid ${loadaddr} str; then "\ - "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ - "fi;"\ - "fi;"\ - "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\ - "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\ - "setenv serial ${usid}; setenv serial# ${usid};"\ - "\0"\ - -#ifdef CONFIG_DDR_WINDOWING_BOOT -#define CONFIG_PREBOOT \ - "run bcb_cmd; "\ - "run run_dspa; "\ - "get_hw_id;" \ - "get_boot_ac_voltage;" \ - "run storeargs;"\ - "run upgrade_and_oqc_key_check;"\ - "run ddr_windowing_boot;"\ - "run switch_bootmode;" -#else -#define CONFIG_PREBOOT \ - "run bcb_cmd; "\ - "run run_dspa; "\ - "get_hw_id;" \ - "get_boot_ac_voltage;" \ - "run storeargs;"\ - "run upgrade_and_oqc_key_check;"\ - "run switch_bootmode;" -#endif - -/* #define CONFIG_ENV_IS_NOWHERE 1 */ -#define CONFIG_ENV_SIZE (8*1024) -#define CONFIG_FIT 1 -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_ANDROID_BOOT_IMAGE 1 -#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ - -/* ATTENTION */ -/* DDR configs move to board/amlogic/[board]/firmware/timing.c */ - -/* running in sram */ -//#define UBOOT_RUN_IN_SRAM -#ifdef UBOOT_RUN_IN_SRAM -#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (256*1024) -#else -#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) -#define CONFIG_SYS_MALLOC_LEN (64*1024*1024) -#endif - -//#define CONFIG_NR_DRAM_BANKS 1 -/* ddr functions */ -#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test -#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp -#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down -#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref -#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function -#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function - -/* storage: emmc/nand/sd */ -#define CONFIG_ENV_OVERWRITE -/* #define CONFIG_CMD_SAVEENV */ -/* fixme, need fix*/ - -#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) -#error env in amlnand/mmc already be compatible; -#endif - -/* -* storage -* |---------|---------| -* | | -* emmc<--Compatible-->nand -* |-------|-------| -* | | -* MTD<-Exclusive->NFTL -* | -* |***************|***************| -* slc-nand SPI-nand SPI-nor -* (raw nand) -*/ -/* axg only support slc nand */ -/* swither for mtd nand which is for slc only. */ - - -#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC) -#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; -#endif - -#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MESON_NFC) -#error CONFIG_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; -#endif - -/* #define CONFIG_AML_SD_EMMC 1 */ -#ifdef CONFIG_AML_SD_EMMC - #define CONFIG_GENERIC_MMC 1 - #define CONFIG_CMD_MMC 1 - #define CONFIG_CMD_GPT 1 - #define CONFIG_SYS_MMC_ENV_DEV 1 - #define CONFIG_EMMC_DDR52_EN 0 - #define CONFIG_EMMC_DDR52_CLK 35000000 -#endif -#define CONFIG_PARTITIONS 1 -#if 0 -#define CONFIG_SYS_NO_FLASH 1 -#endif - -#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND - #define CONFIG_SYS_MAX_NAND_DEVICE 2 -#endif - -/* vpu */ -#define AML_VPU_CLK_LEVEL_DFT 7 - -/* osd */ -#define OSD_SCALE_ENABLE -#define AML_OSD_HIGH_VERSION - -/* USB - * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard - * Enable CONFIG_MUSB_UDD for Device functionalities. - */ -/* #define CONFIG_MUSB_UDC 1 */ -/* #define CONFIG_CMD_USB 1 */ - -#define USB_PHY2_PLL_PARAMETER_1 0x09400414 -#define USB_PHY2_PLL_PARAMETER_2 0x927e0000 -#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5 - -#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18) -#define USB_G12x_PHY_PLL_SETTING_2 (0xfff) -#define USB_G12x_PHY_PLL_SETTING_3 (0x78000) -#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004) -#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c) - -#define AML_TXLX_USB 1 -#define AML_USB_V2 1 -#define USB_GENERAL_BIT 3 -#define USB_PHY21_BIT 4 - -/* UBOOT fastboot config */ - - -/* UBOOT Facotry usb/sdcard burning config */ - -/* net */ -/* #define CONFIG_CMD_NET 1 */ -#define CONFIG_ETH_DESIGNWARE -#if defined(CONFIG_CMD_NET) - #define CONFIG_DESIGNWARE_ETH 1 - #define CONFIG_PHYLIB 1 - #define CONFIG_NET_MULTI 1 - #define CONFIG_CMD_PING 1 - #define CONFIG_CMD_DHCP 1 - #define CONFIG_CMD_RARP 1 - #define CONFIG_HOSTNAME "arm_gxbb" -#if 0 - #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ -#endif - #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ - #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ - #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ - #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ - #define CONFIG_NETMASK 255.255.255.0 -#endif /* (CONFIG_CMD_NET) */ - -#define MAC_ADDR_NEW 1 - -/* other devices */ -#define CONFIG_SHA1 1 -#define CONFIG_MD5 1 - -/* commands */ - -/*file system*/ -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_EFI_PARTITION 1 -/* #define CONFIG_MMC 1 */ -#define CONFIG_FS_FAT 1 -#define CONFIG_FS_EXT4 1 -#define CONFIG_LZO 1 - -/* Cache Definitions */ -/* #define CONFIG_SYS_DCACHE_OFF */ -/* #define CONFIG_SYS_ICACHE_OFF */ - -/* other functions */ -#define CONFIG_LIBAVB 1 -/* top hide for NBG file */ -#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000 - -#define CONFIG_CPU_ARMV8 - -//use sha2 command -#define CONFIG_CMD_SHA2 - -//use hardware sha2 -#define CONFIG_AML_HW_SHA2 - -/* #define CONFIG_MULTI_DTB 1 */ - -/* support secure boot */ -#define CONFIG_AML_SECURE_UBOOT 1 - -#if defined(CONFIG_AML_SECURE_UBOOT) - -/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */ -#define CONFIG_AML_CRYPTO_UBOOT 1 -//#define CONFIG_AML_SIGNED_UBOOT 1 -/* unify build for generate encrypted kernel image - SRC : "board/amlogic/(board)/boot.img" - DST : "fip/boot.img.encrypt" */ -/* #define CONFIG_AML_CRYPTO_IMG 1 */ - -#endif /* CONFIG_AML_SECURE_UBOOT */ - -#define CONFIG_FIP_IMG_SUPPORT 1 - -#endif -
diff --git a/board/amlogic/configs/c2_2rs4_p2.h b/board/amlogic/configs/c2_2rs4_p2.h deleted file mode 100644 index 79d08c4..0000000 --- a/board/amlogic/configs/c2_2rs4_p2.h +++ /dev/null
@@ -1,464 +0,0 @@ - -/* - * Copyright (C) 2015 Amlogic, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -*/ - -#ifndef __BOARD_CFG_H__ -#define __BOARD_CFG_H__ - -#include <asm/arch/cpu.h> - -/* UBOOT Facotry usb burning config */ -#ifndef AML_DISABLE_UPDATE_MODE -#define CONFIG_AML_V3_FACTORY_BURN 1 -#define CONFIG_AML_V3_USB_TOOl 1 -#define CONFIG_USB_GADGET_DOWNLOAD 1 -#define CONFIG_FASTBOOT_DWC_PCD 1 -#define CONFIG_USB_DEVICE_V2 1 -#endif - -/* enable command line for bringup */ -#ifdef CONFIG_ENABLE_UBOOT_CLI -#define CONFIG_CLI_ENABLED 1 -#endif - -/* - * platform power init config - */ - -#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage -#define AML_VDDEE_INIT_VOLTAGE 801 // VDDEE power up voltage -/*if CONFIG_PDVFS_ENABLE is defined, AML_VCCK_INIT_VOLTAGE will be invalid*/ -#define CONFIG_PDVFS_ENABLE - - -/* SMP Definitinos */ -#define CPU_RELEASE_ADDR secondary_boot_func - -/* Bootloader Control Block function - That is used for recovery and the bootloader to talk to each other - */ -#if 0 -#define CONFIG_BOOTLOADER_CONTROL_BLOCK -#endif - -/* Serial config */ -#define CONFIG_CONS_INDEX 2 -#define CONFIG_BAUDRATE 115200 - -/* Enable ir remote wake up for bl30 */ -#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power -#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+ -#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch- -#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power -#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04 -#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF -#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF -#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF -#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF - -/*config the default parameters for adc power key*/ -#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ -#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ - -#define CONFIG_BOOTLOADER_CONTROL_BLOCK - -#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition -#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}" -#else -#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}" -#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition - -#ifdef AML_ENABLE_PRODUCTION_MODE -#define JUDGE_MODE "echo this is production mode;" -#define CONFIG_AML_PRODUCT_MODE 1 -#ifdef CONFIG_FASTBOOT -#define CONFIG_NO_FASTBOOT_FLASHING 1 -#endif //CONFIG_FASTBOOT -#ifdef CONFIG_MESON_SERIAL -#define CONFIG_DISABLE_AML_SERIAL 1 -#endif //CONFIG_MESON_SERIAL -#define USB_BURNING_OPTION "echo productmode" -#else //AML_ENABLE_PRODUCTION_MODE -#define JUDGE_MODE "echo this is not production mode;" -#define CONFIG_CMD_BOOTD 1 -#if (defined(CONFIG_ARM) && !defined(CONFIG_ARM64)) -#define CONFIG_CMD_BOOTZ 1 -#endif //defined(CONFIG_ARM) && !defined(CONFIG_ARM64) -#ifdef CONFIG_ARM64 -#define CONFIG_CMD_BOOTI 1 -#endif //CONFIG_ARM64 -#define CONFIG_CMD_MEMORY 1 -#define CONFIG_CMD_SOURCE 1 -#ifdef CONFIG_MISC -#define CONFIG_CMD_JTAG 1 -#endif //CONFIG_MISC -#ifdef CONFIG_CMD_BOOTI -#define CONFIG_CMD_LZMADEC 1 -#define CONFIG_CMD_UNZIP 1 -#define CONFIG_LZMA 1 -#endif //CONFIG_CMD_BOOTI -#define USB_BURNING_OPTION "adnl" - -#endif //AML_ENABLE_PRODUCTION_MODE - -/* args/envs */ -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_EXTRA_ENV_SETTINGS \ - "firstboot=1\0"\ - "jtag=disable\0"\ - "loadaddr=0x00020000\0"\ - "loadaddr_kernel=0x01080000\0"\ - "loadaddr_dspa=0x06000000\0"\ - "otg_device=1\0" \ - "usb_burning=" USB_BURNING_OPTION "\0" \ - "fdt_high=0x20000000\0"\ - "EnableSelinux=enforcing\0" \ - "boot_part=boot_a\0"\ - "active_slot=_a\0"\ - "Irq_check_en=0\0"\ - "fatload_dev=usb\0"\ - "initargs="\ - "\0"\ - "upgrade_check="\ - "echo recovery_status=${recovery_status};"\ - "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\ - "run storeargs; run recovery_from_flash;"\ - "else fi;"\ - "echo upgrade_step=${upgrade_step}; "\ - "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\ - "\0"\ - "run_dspa="\ - "unzip 0x6400000 ${loadaddr_dspa};"\ - "dspset 0 1 0;dspset 0 1 1;dsprun 0 ${loadaddr_dspa}; "\ - "\0"\ - "storeargs="\ - "get_rebootmode;"\ - "get_chiptype;"\ - "get_cpu_rev;"\ - "get_ee_vol;"\ - "if test ${reboot_mode} = fastboot; then "\ - "setenv reboot_mode warm_reboot;"\ - "fi;"\ - "setenv bootargs ${initargs} otg_device=${otg_device} "\ - "gpt " \ - "androidboot.reboot_mode=${reboot_mode} "\ - "hw_id=${hw_id} "\ - "boot_ac_voltage=${boot_ac_voltage} "\ - "chip_type=${chip_type} "\ - "cpu_rev=${cpu_rev} "\ - "vddee=${vddee_voltage} "\ - "irq_check_en=${Irq_check_en} "\ - "androidboot.hardware="__stringify(BOARD_NAME)" "\ - "androidboot.bl2_boot_part=${bl2_part} "\ - "androidboot.slot_suffix=${active_slot} "\ - "androidboot.firstboot=${firstboot} jtag=${jtag}; "\ - "setenv bootargs ${bootargs};"\ - "\0"\ - "switch_bootmode="\ - "get_rebootmode;"\ - "echo reboot_mode:${reboot_mode};"\ - "if test ${reboot_mode} = factory_boot; then " \ - "setenv bootargs ${bootargs} androidboot.real_reboot_mode=${real_reboot_mode};"\ - "if imgread kernel system_b ${loadaddr_kernel}; then " \ - "bootm ${loadaddr_kernel};"\ - "fi;" \ - "else if test ${reboot_mode} = update; then "\ - "run update;"\ - "else if test ${reboot_mode} = delayed_reboot; then "\ - "delayed_reboot;"\ - "else if test ${reboot_mode} = quiescent; then "\ - "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ - "else if test ${reboot_mode} = cold_boot; then "\ - "fi;fi;fi;fi;fi;"\ - "\0" \ - "storeboot="\ - JUDGE_MODE \ - "setenv loadaddr ${loadaddr_kernel};"\ - "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ - "echo try upgrade as booting failure; run update;"\ - "\0" \ - "update="\ - /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ - "run usb_burning; "\ - "run recovery_from_udisk;"\ - "\0"\ - "recovery_from_fat_dev="\ - "setenv loadaddr ${loadaddr_kernel};"\ - "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img 0x10000000 0; then "\ - "bootm ${loadaddr};fi;"\ - "\0"\ - "recovery_from_udisk="\ - "setenv fatload_dev usb;"\ - "if usb start 0; then run recovery_from_fat_dev; fi;"\ - "\0"\ - "bcb_cmd="\ - "get_valid_slot;"\ - "\0"\ - "ddr_windowing_boot="\ - "ddr_auto_fast_boot_check 6;"\ - "\0"\ - "oqc_check="\ - "setenv test_mode false;"\ - "setenv fatload_dev usb;"\ - "if usb start 0; then "\ - "if fatload ${fatload_dev} 0 ${loadaddr} OQC.txt 0x100000 0; then "\ - "setenv test_mode true;"\ - "fi;"\ - "fi;"\ - "setenv bootargs ${bootargs} androidboot.test_mode=${test_mode};"\ - "\0"\ - "upgrade_and_oqc_key_check="\ - "if gpio input GPIOX_12; then "\ - "echo RESET KEY pressed;"\ - "setenv boot_external_image 1;"\ - "run recovery_from_udisk;"\ - "setenv boot_external_image 0;"\ - "run oqc_check;"\ - "else "\ - "echo RESET KEY not pressed;"\ - "fi;"\ - "\0"\ - "cmdline_keys="\ - "setenv usid 1234567890; setenv region_code US;"\ - "if keyman init 0x1234; then "\ - "if keyman read usid ${loadaddr} str; then fi;"\ - "if keyman read region_code ${loadaddr} str; then fi;"\ - "if keyman read mac ${loadaddr} str; then "\ - "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ - "fi;"\ - "if keyman read deviceid ${loadaddr} str; then "\ - "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ - "fi;"\ - "fi;"\ - "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\ - "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\ - "setenv serial ${usid}; setenv serial# ${usid};"\ - "\0"\ - -#ifdef CONFIG_DDR_WINDOWING_BOOT -#define CONFIG_PREBOOT \ - "run bcb_cmd; "\ - "run run_dspa; "\ - "get_hw_id;" \ - "get_boot_ac_voltage;" \ - "run storeargs;"\ - "run upgrade_and_oqc_key_check;"\ - "run ddr_windowing_boot;"\ - "run switch_bootmode;" -#else -#define CONFIG_PREBOOT \ - "run bcb_cmd; "\ - "run run_dspa; "\ - "get_hw_id;" \ - "get_boot_ac_voltage;" \ - "run storeargs;"\ - "run upgrade_and_oqc_key_check;"\ - "run switch_bootmode;" -#endif - -/* #define CONFIG_ENV_IS_NOWHERE 1 */ -#define CONFIG_ENV_SIZE (8*1024) -#define CONFIG_FIT 1 -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_ANDROID_BOOT_IMAGE 1 -#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ - -/* ATTENTION */ -/* DDR configs move to board/amlogic/[board]/firmware/timing.c */ - -/* running in sram */ -//#define UBOOT_RUN_IN_SRAM -#ifdef UBOOT_RUN_IN_SRAM -#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (256*1024) -#else -#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) -#define CONFIG_SYS_MALLOC_LEN (64*1024*1024) -#endif - -//#define CONFIG_NR_DRAM_BANKS 1 -/* ddr functions */ -#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test -#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp -#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down -#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref -#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function -#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function - -/* storage: emmc/nand/sd */ -#define CONFIG_ENV_OVERWRITE -/* #define CONFIG_CMD_SAVEENV */ -/* fixme, need fix*/ - -#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) -#error env in amlnand/mmc already be compatible; -#endif - -/* -* storage -* |---------|---------| -* | | -* emmc<--Compatible-->nand -* |-------|-------| -* | | -* MTD<-Exclusive->NFTL -* | -* |***************|***************| -* slc-nand SPI-nand SPI-nor -* (raw nand) -*/ -/* axg only support slc nand */ -/* swither for mtd nand which is for slc only. */ - - -#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC) -#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; -#endif - -#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MESON_NFC) -#error CONFIG_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; -#endif - -/* #define CONFIG_AML_SD_EMMC 1 */ -#ifdef CONFIG_AML_SD_EMMC - #define CONFIG_GENERIC_MMC 1 - #define CONFIG_CMD_MMC 1 - #define CONFIG_CMD_GPT 1 - #define CONFIG_SYS_MMC_ENV_DEV 1 - #define CONFIG_EMMC_DDR52_EN 0 - #define CONFIG_EMMC_DDR52_CLK 35000000 -#endif -#define CONFIG_PARTITIONS 1 -#if 0 -#define CONFIG_SYS_NO_FLASH 1 -#endif - -#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND - #define CONFIG_SYS_MAX_NAND_DEVICE 2 -#endif - -/* vpu */ -#define AML_VPU_CLK_LEVEL_DFT 7 - -/* osd */ -#define OSD_SCALE_ENABLE -#define AML_OSD_HIGH_VERSION - -/* USB - * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard - * Enable CONFIG_MUSB_UDD for Device functionalities. - */ -/* #define CONFIG_MUSB_UDC 1 */ -/* #define CONFIG_CMD_USB 1 */ - -#define USB_PHY2_PLL_PARAMETER_1 0x09400414 -#define USB_PHY2_PLL_PARAMETER_2 0x927e0000 -#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5 - -#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18) -#define USB_G12x_PHY_PLL_SETTING_2 (0xfff) -#define USB_G12x_PHY_PLL_SETTING_3 (0x78000) -#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004) -#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c) - -#define AML_TXLX_USB 1 -#define AML_USB_V2 1 -#define USB_GENERAL_BIT 3 -#define USB_PHY21_BIT 4 - -/* UBOOT fastboot config */ - - -/* UBOOT Facotry usb/sdcard burning config */ - -/* net */ -/* #define CONFIG_CMD_NET 1 */ -#define CONFIG_ETH_DESIGNWARE -#if defined(CONFIG_CMD_NET) - #define CONFIG_DESIGNWARE_ETH 1 - #define CONFIG_PHYLIB 1 - #define CONFIG_NET_MULTI 1 - #define CONFIG_CMD_PING 1 - #define CONFIG_CMD_DHCP 1 - #define CONFIG_CMD_RARP 1 - #define CONFIG_HOSTNAME "arm_gxbb" -#if 0 - #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ -#endif - #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ - #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ - #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ - #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ - #define CONFIG_NETMASK 255.255.255.0 -#endif /* (CONFIG_CMD_NET) */ - -#define MAC_ADDR_NEW 1 - -/* other devices */ -#define CONFIG_SHA1 1 -#define CONFIG_MD5 1 - -/* commands */ - -/*file system*/ -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_EFI_PARTITION 1 -/* #define CONFIG_MMC 1 */ -#define CONFIG_FS_FAT 1 -#define CONFIG_FS_EXT4 1 -#define CONFIG_LZO 1 - -/* Cache Definitions */ -/* #define CONFIG_SYS_DCACHE_OFF */ -/* #define CONFIG_SYS_ICACHE_OFF */ - -/* other functions */ -#define CONFIG_LIBAVB 1 -/* top hide for NBG file */ -#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000 - -#define CONFIG_CPU_ARMV8 - -//use sha2 command -#define CONFIG_CMD_SHA2 - -//use hardware sha2 -#define CONFIG_AML_HW_SHA2 - -/* #define CONFIG_MULTI_DTB 1 */ - -/* support secure boot */ -#define CONFIG_AML_SECURE_UBOOT 1 - -#if defined(CONFIG_AML_SECURE_UBOOT) - -/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */ -#define CONFIG_AML_CRYPTO_UBOOT 1 -//#define CONFIG_AML_SIGNED_UBOOT 1 -/* unify build for generate encrypted kernel image - SRC : "board/amlogic/(board)/boot.img" - DST : "fip/boot.img.encrypt" */ -/* #define CONFIG_AML_CRYPTO_IMG 1 */ - -#endif /* CONFIG_AML_SECURE_UBOOT */ - -#define CONFIG_FIP_IMG_SUPPORT 1 - -#endif -
diff --git a/board/amlogic/configs/c2_bla4_bx.h b/board/amlogic/configs/c2_bla4_bx.h deleted file mode 100644 index 5e5026e..0000000 --- a/board/amlogic/configs/c2_bla4_bx.h +++ /dev/null
@@ -1,466 +0,0 @@ - -/* - * Copyright (C) 2015 Amlogic, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -*/ - -#ifndef __BOARD_CFG_H__ -#define __BOARD_CFG_H__ - -#include <asm/arch/cpu.h> - -#define BLA4_HW_CID 0x0 - -/* UBOOT Facotry usb burning config */ -#ifndef AML_DISABLE_UPDATE_MODE -#define CONFIG_AML_V3_FACTORY_BURN 1 -#define CONFIG_AML_V3_USB_TOOl 1 -#define CONFIG_USB_GADGET_DOWNLOAD 1 -#define CONFIG_FASTBOOT_DWC_PCD 1 -#define CONFIG_USB_DEVICE_V2 1 -#endif - -/* enable command line for bringup */ -#ifdef CONFIG_ENABLE_UBOOT_CLI -#define CONFIG_CLI_ENABLED 1 -#endif - -/* - * platform power init config - */ - -#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage -#define AML_VDDEE_INIT_VOLTAGE 801 // VDDEE power up voltage -/*if CONFIG_PDVFS_ENABLE is defined, AML_VCCK_INIT_VOLTAGE will be invalid*/ -#define CONFIG_PDVFS_ENABLE - - -/* SMP Definitinos */ -#define CPU_RELEASE_ADDR secondary_boot_func - -/* Bootloader Control Block function - That is used for recovery and the bootloader to talk to each other - */ -#if 0 -#define CONFIG_BOOTLOADER_CONTROL_BLOCK -#endif - -/* Serial config */ -#define CONFIG_CONS_INDEX 2 -#define CONFIG_BAUDRATE 115200 - -/* Enable ir remote wake up for bl30 */ -#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power -#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+ -#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch- -#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power -#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04 -#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF -#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF -#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF -#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF - -/*config the default parameters for adc power key*/ -#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ -#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ - -#define CONFIG_BOOTLOADER_CONTROL_BLOCK - -#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition -#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}" -#else -#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}" -#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition - -#ifdef AML_ENABLE_PRODUCTION_MODE -#define JUDGE_MODE "echo this is production mode;" -#define CONFIG_AML_PRODUCT_MODE 1 -#ifdef CONFIG_FASTBOOT -#define CONFIG_NO_FASTBOOT_FLASHING 1 -#endif //CONFIG_FASTBOOT -#ifdef CONFIG_MESON_SERIAL -#define CONFIG_DISABLE_AML_SERIAL 1 -#endif //CONFIG_MESON_SERIAL -#define USB_BURNING_OPTION "echo productmode" -#else //AML_ENABLE_PRODUCTION_MODE -#define JUDGE_MODE "echo this is not production mode;" -#define CONFIG_CMD_BOOTD 1 -#if (defined(CONFIG_ARM) && !defined(CONFIG_ARM64)) -#define CONFIG_CMD_BOOTZ 1 -#endif //defined(CONFIG_ARM) && !defined(CONFIG_ARM64) -#ifdef CONFIG_ARM64 -#define CONFIG_CMD_BOOTI 1 -#endif //CONFIG_ARM64 -#define CONFIG_CMD_MEMORY 1 -#define CONFIG_CMD_SOURCE 1 -#ifdef CONFIG_MISC -#define CONFIG_CMD_JTAG 1 -#endif //CONFIG_MISC -#ifdef CONFIG_CMD_BOOTI -#define CONFIG_CMD_LZMADEC 1 -#define CONFIG_CMD_UNZIP 1 -#define CONFIG_LZMA 1 -#endif //CONFIG_CMD_BOOTI -#define USB_BURNING_OPTION "adnl" - -#endif //AML_ENABLE_PRODUCTION_MODE - -/* args/envs */ -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_EXTRA_ENV_SETTINGS \ - "firstboot=1\0"\ - "jtag=disable\0"\ - "loadaddr=0x00020000\0"\ - "loadaddr_kernel=0x01080000\0"\ - "loadaddr_dspa=0x06000000\0"\ - "otg_device=1\0" \ - "usb_burning=" USB_BURNING_OPTION "\0" \ - "fdt_high=0x20000000\0"\ - "EnableSelinux=enforcing\0" \ - "boot_part=boot_a\0"\ - "active_slot=_a\0"\ - "Irq_check_en=0\0"\ - "fatload_dev=usb\0"\ - "initargs="\ - "\0"\ - "upgrade_check="\ - "echo recovery_status=${recovery_status};"\ - "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\ - "run storeargs; run recovery_from_flash;"\ - "else fi;"\ - "echo upgrade_step=${upgrade_step}; "\ - "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\ - "\0"\ - "run_dspa="\ - "unzip 0x6400000 ${loadaddr_dspa};"\ - "dspset 0 1 0;dspset 0 1 1;dsprun 0 ${loadaddr_dspa}; "\ - "\0"\ - "storeargs="\ - "get_rebootmode;"\ - "get_chiptype;"\ - "get_cpu_rev;"\ - "get_ee_vol;"\ - "if test ${reboot_mode} = fastboot; then "\ - "setenv reboot_mode warm_reboot;"\ - "fi;"\ - "setenv bootargs ${initargs} otg_device=${otg_device} "\ - "gpt " \ - "androidboot.reboot_mode=${reboot_mode} "\ - "hw_id=${hw_id} "\ - "boot_ac_voltage=${boot_ac_voltage} "\ - "chip_type=${chip_type} "\ - "cpu_rev=${cpu_rev} "\ - "vddee=${vddee_voltage} "\ - "irq_check_en=${Irq_check_en} "\ - "androidboot.hardware="__stringify(BOARD_NAME)" "\ - "androidboot.bl2_boot_part=${bl2_part} "\ - "androidboot.slot_suffix=${active_slot} "\ - "androidboot.firstboot=${firstboot} jtag=${jtag}; "\ - "setenv bootargs ${bootargs};"\ - "\0"\ - "switch_bootmode="\ - "get_rebootmode;"\ - "echo reboot_mode:${reboot_mode};"\ - "if test ${reboot_mode} = factory_boot; then " \ - "setenv bootargs ${bootargs} androidboot.real_reboot_mode=${real_reboot_mode};"\ - "if imgread kernel system_b ${loadaddr_kernel}; then " \ - "bootm ${loadaddr_kernel};"\ - "fi;" \ - "else if test ${reboot_mode} = update; then "\ - "run update;"\ - "else if test ${reboot_mode} = delayed_reboot; then "\ - "delayed_reboot;"\ - "else if test ${reboot_mode} = quiescent; then "\ - "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ - "else if test ${reboot_mode} = cold_boot; then "\ - "fi;fi;fi;fi;fi;"\ - "\0" \ - "storeboot="\ - JUDGE_MODE \ - "setenv loadaddr ${loadaddr_kernel};"\ - "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ - "echo try upgrade as booting failure; run update;"\ - "\0" \ - "update="\ - /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ - "run usb_burning; "\ - "run recovery_from_udisk;"\ - "\0"\ - "recovery_from_fat_dev="\ - "setenv loadaddr ${loadaddr_kernel};"\ - "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img 0x10000000 0; then "\ - "bootm ${loadaddr};fi;"\ - "\0"\ - "recovery_from_udisk="\ - "setenv fatload_dev usb;"\ - "if usb start 0; then run recovery_from_fat_dev; fi;"\ - "\0"\ - "bcb_cmd="\ - "get_valid_slot;"\ - "\0"\ - "ddr_windowing_boot="\ - "ddr_auto_fast_boot_check 6;"\ - "\0"\ - "oqc_check="\ - "setenv test_mode false;"\ - "setenv fatload_dev usb;"\ - "if usb start 0; then "\ - "if fatload ${fatload_dev} 0 ${loadaddr} OQC.txt 0x100000 0; then "\ - "setenv test_mode true;"\ - "fi;"\ - "fi;"\ - "setenv bootargs ${bootargs} androidboot.test_mode=${test_mode};"\ - "\0"\ - "upgrade_and_oqc_key_check="\ - "if gpio input GPIOD_2; then "\ - "echo RESET KEY not pressed;"\ - "else "\ - "echo RESET KEY pressed;"\ - "setenv boot_external_image 1;"\ - "run recovery_from_udisk;"\ - "setenv boot_external_image 0;"\ - "run oqc_check;"\ - "fi;"\ - "\0"\ - "cmdline_keys="\ - "setenv usid 1234567890; setenv region_code US;"\ - "if keyman init 0x1234; then "\ - "if keyman read usid ${loadaddr} str; then fi;"\ - "if keyman read region_code ${loadaddr} str; then fi;"\ - "if keyman read mac ${loadaddr} str; then "\ - "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ - "fi;"\ - "if keyman read deviceid ${loadaddr} str; then "\ - "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ - "fi;"\ - "fi;"\ - "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\ - "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\ - "setenv serial ${usid}; setenv serial# ${usid};"\ - "\0"\ - -#ifdef CONFIG_DDR_WINDOWING_BOOT -#define CONFIG_PREBOOT \ - "run bcb_cmd; "\ - "run run_dspa; "\ - "get_hw_id;" \ - "get_boot_ac_voltage;" \ - "run storeargs;"\ - "run upgrade_and_oqc_key_check;"\ - "run ddr_windowing_boot;"\ - "run switch_bootmode;" -#else -#define CONFIG_PREBOOT \ - "run bcb_cmd; "\ - "run run_dspa; "\ - "get_hw_id;" \ - "get_boot_ac_voltage;" \ - "run storeargs;"\ - "run upgrade_and_oqc_key_check;"\ - "run switch_bootmode;" -#endif - -/* #define CONFIG_ENV_IS_NOWHERE 1 */ -#define CONFIG_ENV_SIZE (8*1024) -#define CONFIG_FIT 1 -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_ANDROID_BOOT_IMAGE 1 -#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ - -/* ATTENTION */ -/* DDR configs move to board/amlogic/[board]/firmware/timing.c */ - -/* running in sram */ -//#define UBOOT_RUN_IN_SRAM -#ifdef UBOOT_RUN_IN_SRAM -#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (256*1024) -#else -#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) -#define CONFIG_SYS_MALLOC_LEN (64*1024*1024) -#endif - -//#define CONFIG_NR_DRAM_BANKS 1 -/* ddr functions */ -#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test -#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp -#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down -#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref -#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function -#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function - -/* storage: emmc/nand/sd */ -#define CONFIG_ENV_OVERWRITE -/* #define CONFIG_CMD_SAVEENV */ -/* fixme, need fix*/ - -#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) -#error env in amlnand/mmc already be compatible; -#endif - -/* -* storage -* |---------|---------| -* | | -* emmc<--Compatible-->nand -* |-------|-------| -* | | -* MTD<-Exclusive->NFTL -* | -* |***************|***************| -* slc-nand SPI-nand SPI-nor -* (raw nand) -*/ -/* axg only support slc nand */ -/* swither for mtd nand which is for slc only. */ - - -#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC) -#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; -#endif - -#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MESON_NFC) -#error CONFIG_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; -#endif - -/* #define CONFIG_AML_SD_EMMC 1 */ -#ifdef CONFIG_AML_SD_EMMC - #define CONFIG_GENERIC_MMC 1 - #define CONFIG_CMD_MMC 1 - #define CONFIG_CMD_GPT 1 - #define CONFIG_SYS_MMC_ENV_DEV 1 - #define CONFIG_EMMC_DDR52_EN 0 - #define CONFIG_EMMC_DDR52_CLK 35000000 -#endif -#define CONFIG_PARTITIONS 1 -#if 0 -#define CONFIG_SYS_NO_FLASH 1 -#endif - -#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND - #define CONFIG_SYS_MAX_NAND_DEVICE 2 -#endif - -/* vpu */ -#define AML_VPU_CLK_LEVEL_DFT 7 - -/* osd */ -#define OSD_SCALE_ENABLE -#define AML_OSD_HIGH_VERSION - -/* USB - * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard - * Enable CONFIG_MUSB_UDD for Device functionalities. - */ -/* #define CONFIG_MUSB_UDC 1 */ -/* #define CONFIG_CMD_USB 1 */ - -#define USB_PHY2_PLL_PARAMETER_1 0x09400414 -#define USB_PHY2_PLL_PARAMETER_2 0x927e0000 -#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5 - -#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18) -#define USB_G12x_PHY_PLL_SETTING_2 (0xfff) -#define USB_G12x_PHY_PLL_SETTING_3 (0x78000) -#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004) -#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c) - -#define AML_TXLX_USB 1 -#define AML_USB_V2 1 -#define USB_GENERAL_BIT 3 -#define USB_PHY21_BIT 4 - -/* UBOOT fastboot config */ - - -/* UBOOT Facotry usb/sdcard burning config */ - -/* net */ -/* #define CONFIG_CMD_NET 1 */ -#define CONFIG_ETH_DESIGNWARE -#if defined(CONFIG_CMD_NET) - #define CONFIG_DESIGNWARE_ETH 1 - #define CONFIG_PHYLIB 1 - #define CONFIG_NET_MULTI 1 - #define CONFIG_CMD_PING 1 - #define CONFIG_CMD_DHCP 1 - #define CONFIG_CMD_RARP 1 - #define CONFIG_HOSTNAME "arm_gxbb" -#if 0 - #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ -#endif - #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ - #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ - #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ - #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ - #define CONFIG_NETMASK 255.255.255.0 -#endif /* (CONFIG_CMD_NET) */ - -#define MAC_ADDR_NEW 1 - -/* other devices */ -#define CONFIG_SHA1 1 -#define CONFIG_MD5 1 - -/* commands */ - -/*file system*/ -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_EFI_PARTITION 1 -/* #define CONFIG_MMC 1 */ -#define CONFIG_FS_FAT 1 -#define CONFIG_FS_EXT4 1 -#define CONFIG_LZO 1 - -/* Cache Definitions */ -/* #define CONFIG_SYS_DCACHE_OFF */ -/* #define CONFIG_SYS_ICACHE_OFF */ - -/* other functions */ -#define CONFIG_LIBAVB 1 -/* top hide for NBG file */ -#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000 - -#define CONFIG_CPU_ARMV8 - -//use sha2 command -#define CONFIG_CMD_SHA2 - -//use hardware sha2 -#define CONFIG_AML_HW_SHA2 - -/* #define CONFIG_MULTI_DTB 1 */ - -/* support secure boot */ -#define CONFIG_AML_SECURE_UBOOT 1 - -#if defined(CONFIG_AML_SECURE_UBOOT) - -/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */ -#define CONFIG_AML_CRYPTO_UBOOT 1 -//#define CONFIG_AML_SIGNED_UBOOT 1 -/* unify build for generate encrypted kernel image - SRC : "board/amlogic/(board)/boot.img" - DST : "fip/boot.img.encrypt" */ -/* #define CONFIG_AML_CRYPTO_IMG 1 */ - -#endif /* CONFIG_AML_SECURE_UBOOT */ - -#define CONFIG_FIP_IMG_SUPPORT 1 - -#endif -
diff --git a/board/amlogic/configs/c2_bla4_p0.h b/board/amlogic/configs/c2_bla4_p0.h deleted file mode 100644 index 5e5026e..0000000 --- a/board/amlogic/configs/c2_bla4_p0.h +++ /dev/null
@@ -1,466 +0,0 @@ - -/* - * Copyright (C) 2015 Amlogic, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -*/ - -#ifndef __BOARD_CFG_H__ -#define __BOARD_CFG_H__ - -#include <asm/arch/cpu.h> - -#define BLA4_HW_CID 0x0 - -/* UBOOT Facotry usb burning config */ -#ifndef AML_DISABLE_UPDATE_MODE -#define CONFIG_AML_V3_FACTORY_BURN 1 -#define CONFIG_AML_V3_USB_TOOl 1 -#define CONFIG_USB_GADGET_DOWNLOAD 1 -#define CONFIG_FASTBOOT_DWC_PCD 1 -#define CONFIG_USB_DEVICE_V2 1 -#endif - -/* enable command line for bringup */ -#ifdef CONFIG_ENABLE_UBOOT_CLI -#define CONFIG_CLI_ENABLED 1 -#endif - -/* - * platform power init config - */ - -#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage -#define AML_VDDEE_INIT_VOLTAGE 801 // VDDEE power up voltage -/*if CONFIG_PDVFS_ENABLE is defined, AML_VCCK_INIT_VOLTAGE will be invalid*/ -#define CONFIG_PDVFS_ENABLE - - -/* SMP Definitinos */ -#define CPU_RELEASE_ADDR secondary_boot_func - -/* Bootloader Control Block function - That is used for recovery and the bootloader to talk to each other - */ -#if 0 -#define CONFIG_BOOTLOADER_CONTROL_BLOCK -#endif - -/* Serial config */ -#define CONFIG_CONS_INDEX 2 -#define CONFIG_BAUDRATE 115200 - -/* Enable ir remote wake up for bl30 */ -#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power -#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+ -#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch- -#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power -#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04 -#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF -#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF -#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF -#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF - -/*config the default parameters for adc power key*/ -#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ -#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ - -#define CONFIG_BOOTLOADER_CONTROL_BLOCK - -#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition -#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}" -#else -#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}" -#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition - -#ifdef AML_ENABLE_PRODUCTION_MODE -#define JUDGE_MODE "echo this is production mode;" -#define CONFIG_AML_PRODUCT_MODE 1 -#ifdef CONFIG_FASTBOOT -#define CONFIG_NO_FASTBOOT_FLASHING 1 -#endif //CONFIG_FASTBOOT -#ifdef CONFIG_MESON_SERIAL -#define CONFIG_DISABLE_AML_SERIAL 1 -#endif //CONFIG_MESON_SERIAL -#define USB_BURNING_OPTION "echo productmode" -#else //AML_ENABLE_PRODUCTION_MODE -#define JUDGE_MODE "echo this is not production mode;" -#define CONFIG_CMD_BOOTD 1 -#if (defined(CONFIG_ARM) && !defined(CONFIG_ARM64)) -#define CONFIG_CMD_BOOTZ 1 -#endif //defined(CONFIG_ARM) && !defined(CONFIG_ARM64) -#ifdef CONFIG_ARM64 -#define CONFIG_CMD_BOOTI 1 -#endif //CONFIG_ARM64 -#define CONFIG_CMD_MEMORY 1 -#define CONFIG_CMD_SOURCE 1 -#ifdef CONFIG_MISC -#define CONFIG_CMD_JTAG 1 -#endif //CONFIG_MISC -#ifdef CONFIG_CMD_BOOTI -#define CONFIG_CMD_LZMADEC 1 -#define CONFIG_CMD_UNZIP 1 -#define CONFIG_LZMA 1 -#endif //CONFIG_CMD_BOOTI -#define USB_BURNING_OPTION "adnl" - -#endif //AML_ENABLE_PRODUCTION_MODE - -/* args/envs */ -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_EXTRA_ENV_SETTINGS \ - "firstboot=1\0"\ - "jtag=disable\0"\ - "loadaddr=0x00020000\0"\ - "loadaddr_kernel=0x01080000\0"\ - "loadaddr_dspa=0x06000000\0"\ - "otg_device=1\0" \ - "usb_burning=" USB_BURNING_OPTION "\0" \ - "fdt_high=0x20000000\0"\ - "EnableSelinux=enforcing\0" \ - "boot_part=boot_a\0"\ - "active_slot=_a\0"\ - "Irq_check_en=0\0"\ - "fatload_dev=usb\0"\ - "initargs="\ - "\0"\ - "upgrade_check="\ - "echo recovery_status=${recovery_status};"\ - "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\ - "run storeargs; run recovery_from_flash;"\ - "else fi;"\ - "echo upgrade_step=${upgrade_step}; "\ - "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\ - "\0"\ - "run_dspa="\ - "unzip 0x6400000 ${loadaddr_dspa};"\ - "dspset 0 1 0;dspset 0 1 1;dsprun 0 ${loadaddr_dspa}; "\ - "\0"\ - "storeargs="\ - "get_rebootmode;"\ - "get_chiptype;"\ - "get_cpu_rev;"\ - "get_ee_vol;"\ - "if test ${reboot_mode} = fastboot; then "\ - "setenv reboot_mode warm_reboot;"\ - "fi;"\ - "setenv bootargs ${initargs} otg_device=${otg_device} "\ - "gpt " \ - "androidboot.reboot_mode=${reboot_mode} "\ - "hw_id=${hw_id} "\ - "boot_ac_voltage=${boot_ac_voltage} "\ - "chip_type=${chip_type} "\ - "cpu_rev=${cpu_rev} "\ - "vddee=${vddee_voltage} "\ - "irq_check_en=${Irq_check_en} "\ - "androidboot.hardware="__stringify(BOARD_NAME)" "\ - "androidboot.bl2_boot_part=${bl2_part} "\ - "androidboot.slot_suffix=${active_slot} "\ - "androidboot.firstboot=${firstboot} jtag=${jtag}; "\ - "setenv bootargs ${bootargs};"\ - "\0"\ - "switch_bootmode="\ - "get_rebootmode;"\ - "echo reboot_mode:${reboot_mode};"\ - "if test ${reboot_mode} = factory_boot; then " \ - "setenv bootargs ${bootargs} androidboot.real_reboot_mode=${real_reboot_mode};"\ - "if imgread kernel system_b ${loadaddr_kernel}; then " \ - "bootm ${loadaddr_kernel};"\ - "fi;" \ - "else if test ${reboot_mode} = update; then "\ - "run update;"\ - "else if test ${reboot_mode} = delayed_reboot; then "\ - "delayed_reboot;"\ - "else if test ${reboot_mode} = quiescent; then "\ - "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ - "else if test ${reboot_mode} = cold_boot; then "\ - "fi;fi;fi;fi;fi;"\ - "\0" \ - "storeboot="\ - JUDGE_MODE \ - "setenv loadaddr ${loadaddr_kernel};"\ - "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ - "echo try upgrade as booting failure; run update;"\ - "\0" \ - "update="\ - /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ - "run usb_burning; "\ - "run recovery_from_udisk;"\ - "\0"\ - "recovery_from_fat_dev="\ - "setenv loadaddr ${loadaddr_kernel};"\ - "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img 0x10000000 0; then "\ - "bootm ${loadaddr};fi;"\ - "\0"\ - "recovery_from_udisk="\ - "setenv fatload_dev usb;"\ - "if usb start 0; then run recovery_from_fat_dev; fi;"\ - "\0"\ - "bcb_cmd="\ - "get_valid_slot;"\ - "\0"\ - "ddr_windowing_boot="\ - "ddr_auto_fast_boot_check 6;"\ - "\0"\ - "oqc_check="\ - "setenv test_mode false;"\ - "setenv fatload_dev usb;"\ - "if usb start 0; then "\ - "if fatload ${fatload_dev} 0 ${loadaddr} OQC.txt 0x100000 0; then "\ - "setenv test_mode true;"\ - "fi;"\ - "fi;"\ - "setenv bootargs ${bootargs} androidboot.test_mode=${test_mode};"\ - "\0"\ - "upgrade_and_oqc_key_check="\ - "if gpio input GPIOD_2; then "\ - "echo RESET KEY not pressed;"\ - "else "\ - "echo RESET KEY pressed;"\ - "setenv boot_external_image 1;"\ - "run recovery_from_udisk;"\ - "setenv boot_external_image 0;"\ - "run oqc_check;"\ - "fi;"\ - "\0"\ - "cmdline_keys="\ - "setenv usid 1234567890; setenv region_code US;"\ - "if keyman init 0x1234; then "\ - "if keyman read usid ${loadaddr} str; then fi;"\ - "if keyman read region_code ${loadaddr} str; then fi;"\ - "if keyman read mac ${loadaddr} str; then "\ - "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ - "fi;"\ - "if keyman read deviceid ${loadaddr} str; then "\ - "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ - "fi;"\ - "fi;"\ - "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\ - "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\ - "setenv serial ${usid}; setenv serial# ${usid};"\ - "\0"\ - -#ifdef CONFIG_DDR_WINDOWING_BOOT -#define CONFIG_PREBOOT \ - "run bcb_cmd; "\ - "run run_dspa; "\ - "get_hw_id;" \ - "get_boot_ac_voltage;" \ - "run storeargs;"\ - "run upgrade_and_oqc_key_check;"\ - "run ddr_windowing_boot;"\ - "run switch_bootmode;" -#else -#define CONFIG_PREBOOT \ - "run bcb_cmd; "\ - "run run_dspa; "\ - "get_hw_id;" \ - "get_boot_ac_voltage;" \ - "run storeargs;"\ - "run upgrade_and_oqc_key_check;"\ - "run switch_bootmode;" -#endif - -/* #define CONFIG_ENV_IS_NOWHERE 1 */ -#define CONFIG_ENV_SIZE (8*1024) -#define CONFIG_FIT 1 -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_ANDROID_BOOT_IMAGE 1 -#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ - -/* ATTENTION */ -/* DDR configs move to board/amlogic/[board]/firmware/timing.c */ - -/* running in sram */ -//#define UBOOT_RUN_IN_SRAM -#ifdef UBOOT_RUN_IN_SRAM -#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (256*1024) -#else -#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) -#define CONFIG_SYS_MALLOC_LEN (64*1024*1024) -#endif - -//#define CONFIG_NR_DRAM_BANKS 1 -/* ddr functions */ -#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test -#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp -#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down -#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref -#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function -#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function - -/* storage: emmc/nand/sd */ -#define CONFIG_ENV_OVERWRITE -/* #define CONFIG_CMD_SAVEENV */ -/* fixme, need fix*/ - -#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) -#error env in amlnand/mmc already be compatible; -#endif - -/* -* storage -* |---------|---------| -* | | -* emmc<--Compatible-->nand -* |-------|-------| -* | | -* MTD<-Exclusive->NFTL -* | -* |***************|***************| -* slc-nand SPI-nand SPI-nor -* (raw nand) -*/ -/* axg only support slc nand */ -/* swither for mtd nand which is for slc only. */ - - -#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC) -#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; -#endif - -#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MESON_NFC) -#error CONFIG_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; -#endif - -/* #define CONFIG_AML_SD_EMMC 1 */ -#ifdef CONFIG_AML_SD_EMMC - #define CONFIG_GENERIC_MMC 1 - #define CONFIG_CMD_MMC 1 - #define CONFIG_CMD_GPT 1 - #define CONFIG_SYS_MMC_ENV_DEV 1 - #define CONFIG_EMMC_DDR52_EN 0 - #define CONFIG_EMMC_DDR52_CLK 35000000 -#endif -#define CONFIG_PARTITIONS 1 -#if 0 -#define CONFIG_SYS_NO_FLASH 1 -#endif - -#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND - #define CONFIG_SYS_MAX_NAND_DEVICE 2 -#endif - -/* vpu */ -#define AML_VPU_CLK_LEVEL_DFT 7 - -/* osd */ -#define OSD_SCALE_ENABLE -#define AML_OSD_HIGH_VERSION - -/* USB - * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard - * Enable CONFIG_MUSB_UDD for Device functionalities. - */ -/* #define CONFIG_MUSB_UDC 1 */ -/* #define CONFIG_CMD_USB 1 */ - -#define USB_PHY2_PLL_PARAMETER_1 0x09400414 -#define USB_PHY2_PLL_PARAMETER_2 0x927e0000 -#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5 - -#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18) -#define USB_G12x_PHY_PLL_SETTING_2 (0xfff) -#define USB_G12x_PHY_PLL_SETTING_3 (0x78000) -#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004) -#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c) - -#define AML_TXLX_USB 1 -#define AML_USB_V2 1 -#define USB_GENERAL_BIT 3 -#define USB_PHY21_BIT 4 - -/* UBOOT fastboot config */ - - -/* UBOOT Facotry usb/sdcard burning config */ - -/* net */ -/* #define CONFIG_CMD_NET 1 */ -#define CONFIG_ETH_DESIGNWARE -#if defined(CONFIG_CMD_NET) - #define CONFIG_DESIGNWARE_ETH 1 - #define CONFIG_PHYLIB 1 - #define CONFIG_NET_MULTI 1 - #define CONFIG_CMD_PING 1 - #define CONFIG_CMD_DHCP 1 - #define CONFIG_CMD_RARP 1 - #define CONFIG_HOSTNAME "arm_gxbb" -#if 0 - #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ -#endif - #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ - #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ - #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ - #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ - #define CONFIG_NETMASK 255.255.255.0 -#endif /* (CONFIG_CMD_NET) */ - -#define MAC_ADDR_NEW 1 - -/* other devices */ -#define CONFIG_SHA1 1 -#define CONFIG_MD5 1 - -/* commands */ - -/*file system*/ -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_EFI_PARTITION 1 -/* #define CONFIG_MMC 1 */ -#define CONFIG_FS_FAT 1 -#define CONFIG_FS_EXT4 1 -#define CONFIG_LZO 1 - -/* Cache Definitions */ -/* #define CONFIG_SYS_DCACHE_OFF */ -/* #define CONFIG_SYS_ICACHE_OFF */ - -/* other functions */ -#define CONFIG_LIBAVB 1 -/* top hide for NBG file */ -#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000 - -#define CONFIG_CPU_ARMV8 - -//use sha2 command -#define CONFIG_CMD_SHA2 - -//use hardware sha2 -#define CONFIG_AML_HW_SHA2 - -/* #define CONFIG_MULTI_DTB 1 */ - -/* support secure boot */ -#define CONFIG_AML_SECURE_UBOOT 1 - -#if defined(CONFIG_AML_SECURE_UBOOT) - -/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */ -#define CONFIG_AML_CRYPTO_UBOOT 1 -//#define CONFIG_AML_SIGNED_UBOOT 1 -/* unify build for generate encrypted kernel image - SRC : "board/amlogic/(board)/boot.img" - DST : "fip/boot.img.encrypt" */ -/* #define CONFIG_AML_CRYPTO_IMG 1 */ - -#endif /* CONFIG_AML_SECURE_UBOOT */ - -#define CONFIG_FIP_IMG_SUPPORT 1 - -#endif -
diff --git a/board/amlogic/configs/c2_bla4_p1.h b/board/amlogic/configs/c2_bla4_p1.h deleted file mode 100644 index 5e5026e..0000000 --- a/board/amlogic/configs/c2_bla4_p1.h +++ /dev/null
@@ -1,466 +0,0 @@ - -/* - * Copyright (C) 2015 Amlogic, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -*/ - -#ifndef __BOARD_CFG_H__ -#define __BOARD_CFG_H__ - -#include <asm/arch/cpu.h> - -#define BLA4_HW_CID 0x0 - -/* UBOOT Facotry usb burning config */ -#ifndef AML_DISABLE_UPDATE_MODE -#define CONFIG_AML_V3_FACTORY_BURN 1 -#define CONFIG_AML_V3_USB_TOOl 1 -#define CONFIG_USB_GADGET_DOWNLOAD 1 -#define CONFIG_FASTBOOT_DWC_PCD 1 -#define CONFIG_USB_DEVICE_V2 1 -#endif - -/* enable command line for bringup */ -#ifdef CONFIG_ENABLE_UBOOT_CLI -#define CONFIG_CLI_ENABLED 1 -#endif - -/* - * platform power init config - */ - -#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage -#define AML_VDDEE_INIT_VOLTAGE 801 // VDDEE power up voltage -/*if CONFIG_PDVFS_ENABLE is defined, AML_VCCK_INIT_VOLTAGE will be invalid*/ -#define CONFIG_PDVFS_ENABLE - - -/* SMP Definitinos */ -#define CPU_RELEASE_ADDR secondary_boot_func - -/* Bootloader Control Block function - That is used for recovery and the bootloader to talk to each other - */ -#if 0 -#define CONFIG_BOOTLOADER_CONTROL_BLOCK -#endif - -/* Serial config */ -#define CONFIG_CONS_INDEX 2 -#define CONFIG_BAUDRATE 115200 - -/* Enable ir remote wake up for bl30 */ -#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power -#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+ -#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch- -#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power -#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04 -#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF -#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF -#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF -#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF - -/*config the default parameters for adc power key*/ -#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ -#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ - -#define CONFIG_BOOTLOADER_CONTROL_BLOCK - -#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition -#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}" -#else -#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}" -#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition - -#ifdef AML_ENABLE_PRODUCTION_MODE -#define JUDGE_MODE "echo this is production mode;" -#define CONFIG_AML_PRODUCT_MODE 1 -#ifdef CONFIG_FASTBOOT -#define CONFIG_NO_FASTBOOT_FLASHING 1 -#endif //CONFIG_FASTBOOT -#ifdef CONFIG_MESON_SERIAL -#define CONFIG_DISABLE_AML_SERIAL 1 -#endif //CONFIG_MESON_SERIAL -#define USB_BURNING_OPTION "echo productmode" -#else //AML_ENABLE_PRODUCTION_MODE -#define JUDGE_MODE "echo this is not production mode;" -#define CONFIG_CMD_BOOTD 1 -#if (defined(CONFIG_ARM) && !defined(CONFIG_ARM64)) -#define CONFIG_CMD_BOOTZ 1 -#endif //defined(CONFIG_ARM) && !defined(CONFIG_ARM64) -#ifdef CONFIG_ARM64 -#define CONFIG_CMD_BOOTI 1 -#endif //CONFIG_ARM64 -#define CONFIG_CMD_MEMORY 1 -#define CONFIG_CMD_SOURCE 1 -#ifdef CONFIG_MISC -#define CONFIG_CMD_JTAG 1 -#endif //CONFIG_MISC -#ifdef CONFIG_CMD_BOOTI -#define CONFIG_CMD_LZMADEC 1 -#define CONFIG_CMD_UNZIP 1 -#define CONFIG_LZMA 1 -#endif //CONFIG_CMD_BOOTI -#define USB_BURNING_OPTION "adnl" - -#endif //AML_ENABLE_PRODUCTION_MODE - -/* args/envs */ -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_EXTRA_ENV_SETTINGS \ - "firstboot=1\0"\ - "jtag=disable\0"\ - "loadaddr=0x00020000\0"\ - "loadaddr_kernel=0x01080000\0"\ - "loadaddr_dspa=0x06000000\0"\ - "otg_device=1\0" \ - "usb_burning=" USB_BURNING_OPTION "\0" \ - "fdt_high=0x20000000\0"\ - "EnableSelinux=enforcing\0" \ - "boot_part=boot_a\0"\ - "active_slot=_a\0"\ - "Irq_check_en=0\0"\ - "fatload_dev=usb\0"\ - "initargs="\ - "\0"\ - "upgrade_check="\ - "echo recovery_status=${recovery_status};"\ - "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\ - "run storeargs; run recovery_from_flash;"\ - "else fi;"\ - "echo upgrade_step=${upgrade_step}; "\ - "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\ - "\0"\ - "run_dspa="\ - "unzip 0x6400000 ${loadaddr_dspa};"\ - "dspset 0 1 0;dspset 0 1 1;dsprun 0 ${loadaddr_dspa}; "\ - "\0"\ - "storeargs="\ - "get_rebootmode;"\ - "get_chiptype;"\ - "get_cpu_rev;"\ - "get_ee_vol;"\ - "if test ${reboot_mode} = fastboot; then "\ - "setenv reboot_mode warm_reboot;"\ - "fi;"\ - "setenv bootargs ${initargs} otg_device=${otg_device} "\ - "gpt " \ - "androidboot.reboot_mode=${reboot_mode} "\ - "hw_id=${hw_id} "\ - "boot_ac_voltage=${boot_ac_voltage} "\ - "chip_type=${chip_type} "\ - "cpu_rev=${cpu_rev} "\ - "vddee=${vddee_voltage} "\ - "irq_check_en=${Irq_check_en} "\ - "androidboot.hardware="__stringify(BOARD_NAME)" "\ - "androidboot.bl2_boot_part=${bl2_part} "\ - "androidboot.slot_suffix=${active_slot} "\ - "androidboot.firstboot=${firstboot} jtag=${jtag}; "\ - "setenv bootargs ${bootargs};"\ - "\0"\ - "switch_bootmode="\ - "get_rebootmode;"\ - "echo reboot_mode:${reboot_mode};"\ - "if test ${reboot_mode} = factory_boot; then " \ - "setenv bootargs ${bootargs} androidboot.real_reboot_mode=${real_reboot_mode};"\ - "if imgread kernel system_b ${loadaddr_kernel}; then " \ - "bootm ${loadaddr_kernel};"\ - "fi;" \ - "else if test ${reboot_mode} = update; then "\ - "run update;"\ - "else if test ${reboot_mode} = delayed_reboot; then "\ - "delayed_reboot;"\ - "else if test ${reboot_mode} = quiescent; then "\ - "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ - "else if test ${reboot_mode} = cold_boot; then "\ - "fi;fi;fi;fi;fi;"\ - "\0" \ - "storeboot="\ - JUDGE_MODE \ - "setenv loadaddr ${loadaddr_kernel};"\ - "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ - "echo try upgrade as booting failure; run update;"\ - "\0" \ - "update="\ - /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ - "run usb_burning; "\ - "run recovery_from_udisk;"\ - "\0"\ - "recovery_from_fat_dev="\ - "setenv loadaddr ${loadaddr_kernel};"\ - "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img 0x10000000 0; then "\ - "bootm ${loadaddr};fi;"\ - "\0"\ - "recovery_from_udisk="\ - "setenv fatload_dev usb;"\ - "if usb start 0; then run recovery_from_fat_dev; fi;"\ - "\0"\ - "bcb_cmd="\ - "get_valid_slot;"\ - "\0"\ - "ddr_windowing_boot="\ - "ddr_auto_fast_boot_check 6;"\ - "\0"\ - "oqc_check="\ - "setenv test_mode false;"\ - "setenv fatload_dev usb;"\ - "if usb start 0; then "\ - "if fatload ${fatload_dev} 0 ${loadaddr} OQC.txt 0x100000 0; then "\ - "setenv test_mode true;"\ - "fi;"\ - "fi;"\ - "setenv bootargs ${bootargs} androidboot.test_mode=${test_mode};"\ - "\0"\ - "upgrade_and_oqc_key_check="\ - "if gpio input GPIOD_2; then "\ - "echo RESET KEY not pressed;"\ - "else "\ - "echo RESET KEY pressed;"\ - "setenv boot_external_image 1;"\ - "run recovery_from_udisk;"\ - "setenv boot_external_image 0;"\ - "run oqc_check;"\ - "fi;"\ - "\0"\ - "cmdline_keys="\ - "setenv usid 1234567890; setenv region_code US;"\ - "if keyman init 0x1234; then "\ - "if keyman read usid ${loadaddr} str; then fi;"\ - "if keyman read region_code ${loadaddr} str; then fi;"\ - "if keyman read mac ${loadaddr} str; then "\ - "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ - "fi;"\ - "if keyman read deviceid ${loadaddr} str; then "\ - "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ - "fi;"\ - "fi;"\ - "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\ - "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\ - "setenv serial ${usid}; setenv serial# ${usid};"\ - "\0"\ - -#ifdef CONFIG_DDR_WINDOWING_BOOT -#define CONFIG_PREBOOT \ - "run bcb_cmd; "\ - "run run_dspa; "\ - "get_hw_id;" \ - "get_boot_ac_voltage;" \ - "run storeargs;"\ - "run upgrade_and_oqc_key_check;"\ - "run ddr_windowing_boot;"\ - "run switch_bootmode;" -#else -#define CONFIG_PREBOOT \ - "run bcb_cmd; "\ - "run run_dspa; "\ - "get_hw_id;" \ - "get_boot_ac_voltage;" \ - "run storeargs;"\ - "run upgrade_and_oqc_key_check;"\ - "run switch_bootmode;" -#endif - -/* #define CONFIG_ENV_IS_NOWHERE 1 */ -#define CONFIG_ENV_SIZE (8*1024) -#define CONFIG_FIT 1 -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_ANDROID_BOOT_IMAGE 1 -#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ - -/* ATTENTION */ -/* DDR configs move to board/amlogic/[board]/firmware/timing.c */ - -/* running in sram */ -//#define UBOOT_RUN_IN_SRAM -#ifdef UBOOT_RUN_IN_SRAM -#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (256*1024) -#else -#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) -#define CONFIG_SYS_MALLOC_LEN (64*1024*1024) -#endif - -//#define CONFIG_NR_DRAM_BANKS 1 -/* ddr functions */ -#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test -#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp -#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down -#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref -#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function -#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function - -/* storage: emmc/nand/sd */ -#define CONFIG_ENV_OVERWRITE -/* #define CONFIG_CMD_SAVEENV */ -/* fixme, need fix*/ - -#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) -#error env in amlnand/mmc already be compatible; -#endif - -/* -* storage -* |---------|---------| -* | | -* emmc<--Compatible-->nand -* |-------|-------| -* | | -* MTD<-Exclusive->NFTL -* | -* |***************|***************| -* slc-nand SPI-nand SPI-nor -* (raw nand) -*/ -/* axg only support slc nand */ -/* swither for mtd nand which is for slc only. */ - - -#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC) -#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; -#endif - -#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MESON_NFC) -#error CONFIG_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; -#endif - -/* #define CONFIG_AML_SD_EMMC 1 */ -#ifdef CONFIG_AML_SD_EMMC - #define CONFIG_GENERIC_MMC 1 - #define CONFIG_CMD_MMC 1 - #define CONFIG_CMD_GPT 1 - #define CONFIG_SYS_MMC_ENV_DEV 1 - #define CONFIG_EMMC_DDR52_EN 0 - #define CONFIG_EMMC_DDR52_CLK 35000000 -#endif -#define CONFIG_PARTITIONS 1 -#if 0 -#define CONFIG_SYS_NO_FLASH 1 -#endif - -#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND - #define CONFIG_SYS_MAX_NAND_DEVICE 2 -#endif - -/* vpu */ -#define AML_VPU_CLK_LEVEL_DFT 7 - -/* osd */ -#define OSD_SCALE_ENABLE -#define AML_OSD_HIGH_VERSION - -/* USB - * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard - * Enable CONFIG_MUSB_UDD for Device functionalities. - */ -/* #define CONFIG_MUSB_UDC 1 */ -/* #define CONFIG_CMD_USB 1 */ - -#define USB_PHY2_PLL_PARAMETER_1 0x09400414 -#define USB_PHY2_PLL_PARAMETER_2 0x927e0000 -#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5 - -#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18) -#define USB_G12x_PHY_PLL_SETTING_2 (0xfff) -#define USB_G12x_PHY_PLL_SETTING_3 (0x78000) -#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004) -#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c) - -#define AML_TXLX_USB 1 -#define AML_USB_V2 1 -#define USB_GENERAL_BIT 3 -#define USB_PHY21_BIT 4 - -/* UBOOT fastboot config */ - - -/* UBOOT Facotry usb/sdcard burning config */ - -/* net */ -/* #define CONFIG_CMD_NET 1 */ -#define CONFIG_ETH_DESIGNWARE -#if defined(CONFIG_CMD_NET) - #define CONFIG_DESIGNWARE_ETH 1 - #define CONFIG_PHYLIB 1 - #define CONFIG_NET_MULTI 1 - #define CONFIG_CMD_PING 1 - #define CONFIG_CMD_DHCP 1 - #define CONFIG_CMD_RARP 1 - #define CONFIG_HOSTNAME "arm_gxbb" -#if 0 - #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ -#endif - #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ - #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ - #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ - #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ - #define CONFIG_NETMASK 255.255.255.0 -#endif /* (CONFIG_CMD_NET) */ - -#define MAC_ADDR_NEW 1 - -/* other devices */ -#define CONFIG_SHA1 1 -#define CONFIG_MD5 1 - -/* commands */ - -/*file system*/ -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_EFI_PARTITION 1 -/* #define CONFIG_MMC 1 */ -#define CONFIG_FS_FAT 1 -#define CONFIG_FS_EXT4 1 -#define CONFIG_LZO 1 - -/* Cache Definitions */ -/* #define CONFIG_SYS_DCACHE_OFF */ -/* #define CONFIG_SYS_ICACHE_OFF */ - -/* other functions */ -#define CONFIG_LIBAVB 1 -/* top hide for NBG file */ -#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000 - -#define CONFIG_CPU_ARMV8 - -//use sha2 command -#define CONFIG_CMD_SHA2 - -//use hardware sha2 -#define CONFIG_AML_HW_SHA2 - -/* #define CONFIG_MULTI_DTB 1 */ - -/* support secure boot */ -#define CONFIG_AML_SECURE_UBOOT 1 - -#if defined(CONFIG_AML_SECURE_UBOOT) - -/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */ -#define CONFIG_AML_CRYPTO_UBOOT 1 -//#define CONFIG_AML_SIGNED_UBOOT 1 -/* unify build for generate encrypted kernel image - SRC : "board/amlogic/(board)/boot.img" - DST : "fip/boot.img.encrypt" */ -/* #define CONFIG_AML_CRYPTO_IMG 1 */ - -#endif /* CONFIG_AML_SECURE_UBOOT */ - -#define CONFIG_FIP_IMG_SUPPORT 1 - -#endif -
diff --git a/board/amlogic/configs/c2_bla4_p2.h b/board/amlogic/configs/c2_bla4_p2.h deleted file mode 100644 index 5e5026e..0000000 --- a/board/amlogic/configs/c2_bla4_p2.h +++ /dev/null
@@ -1,466 +0,0 @@ - -/* - * Copyright (C) 2015 Amlogic, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -*/ - -#ifndef __BOARD_CFG_H__ -#define __BOARD_CFG_H__ - -#include <asm/arch/cpu.h> - -#define BLA4_HW_CID 0x0 - -/* UBOOT Facotry usb burning config */ -#ifndef AML_DISABLE_UPDATE_MODE -#define CONFIG_AML_V3_FACTORY_BURN 1 -#define CONFIG_AML_V3_USB_TOOl 1 -#define CONFIG_USB_GADGET_DOWNLOAD 1 -#define CONFIG_FASTBOOT_DWC_PCD 1 -#define CONFIG_USB_DEVICE_V2 1 -#endif - -/* enable command line for bringup */ -#ifdef CONFIG_ENABLE_UBOOT_CLI -#define CONFIG_CLI_ENABLED 1 -#endif - -/* - * platform power init config - */ - -#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage -#define AML_VDDEE_INIT_VOLTAGE 801 // VDDEE power up voltage -/*if CONFIG_PDVFS_ENABLE is defined, AML_VCCK_INIT_VOLTAGE will be invalid*/ -#define CONFIG_PDVFS_ENABLE - - -/* SMP Definitinos */ -#define CPU_RELEASE_ADDR secondary_boot_func - -/* Bootloader Control Block function - That is used for recovery and the bootloader to talk to each other - */ -#if 0 -#define CONFIG_BOOTLOADER_CONTROL_BLOCK -#endif - -/* Serial config */ -#define CONFIG_CONS_INDEX 2 -#define CONFIG_BAUDRATE 115200 - -/* Enable ir remote wake up for bl30 */ -#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power -#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+ -#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch- -#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power -#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04 -#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF -#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF -#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF -#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF - -/*config the default parameters for adc power key*/ -#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ -#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ - -#define CONFIG_BOOTLOADER_CONTROL_BLOCK - -#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition -#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}" -#else -#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}" -#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition - -#ifdef AML_ENABLE_PRODUCTION_MODE -#define JUDGE_MODE "echo this is production mode;" -#define CONFIG_AML_PRODUCT_MODE 1 -#ifdef CONFIG_FASTBOOT -#define CONFIG_NO_FASTBOOT_FLASHING 1 -#endif //CONFIG_FASTBOOT -#ifdef CONFIG_MESON_SERIAL -#define CONFIG_DISABLE_AML_SERIAL 1 -#endif //CONFIG_MESON_SERIAL -#define USB_BURNING_OPTION "echo productmode" -#else //AML_ENABLE_PRODUCTION_MODE -#define JUDGE_MODE "echo this is not production mode;" -#define CONFIG_CMD_BOOTD 1 -#if (defined(CONFIG_ARM) && !defined(CONFIG_ARM64)) -#define CONFIG_CMD_BOOTZ 1 -#endif //defined(CONFIG_ARM) && !defined(CONFIG_ARM64) -#ifdef CONFIG_ARM64 -#define CONFIG_CMD_BOOTI 1 -#endif //CONFIG_ARM64 -#define CONFIG_CMD_MEMORY 1 -#define CONFIG_CMD_SOURCE 1 -#ifdef CONFIG_MISC -#define CONFIG_CMD_JTAG 1 -#endif //CONFIG_MISC -#ifdef CONFIG_CMD_BOOTI -#define CONFIG_CMD_LZMADEC 1 -#define CONFIG_CMD_UNZIP 1 -#define CONFIG_LZMA 1 -#endif //CONFIG_CMD_BOOTI -#define USB_BURNING_OPTION "adnl" - -#endif //AML_ENABLE_PRODUCTION_MODE - -/* args/envs */ -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_EXTRA_ENV_SETTINGS \ - "firstboot=1\0"\ - "jtag=disable\0"\ - "loadaddr=0x00020000\0"\ - "loadaddr_kernel=0x01080000\0"\ - "loadaddr_dspa=0x06000000\0"\ - "otg_device=1\0" \ - "usb_burning=" USB_BURNING_OPTION "\0" \ - "fdt_high=0x20000000\0"\ - "EnableSelinux=enforcing\0" \ - "boot_part=boot_a\0"\ - "active_slot=_a\0"\ - "Irq_check_en=0\0"\ - "fatload_dev=usb\0"\ - "initargs="\ - "\0"\ - "upgrade_check="\ - "echo recovery_status=${recovery_status};"\ - "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\ - "run storeargs; run recovery_from_flash;"\ - "else fi;"\ - "echo upgrade_step=${upgrade_step}; "\ - "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\ - "\0"\ - "run_dspa="\ - "unzip 0x6400000 ${loadaddr_dspa};"\ - "dspset 0 1 0;dspset 0 1 1;dsprun 0 ${loadaddr_dspa}; "\ - "\0"\ - "storeargs="\ - "get_rebootmode;"\ - "get_chiptype;"\ - "get_cpu_rev;"\ - "get_ee_vol;"\ - "if test ${reboot_mode} = fastboot; then "\ - "setenv reboot_mode warm_reboot;"\ - "fi;"\ - "setenv bootargs ${initargs} otg_device=${otg_device} "\ - "gpt " \ - "androidboot.reboot_mode=${reboot_mode} "\ - "hw_id=${hw_id} "\ - "boot_ac_voltage=${boot_ac_voltage} "\ - "chip_type=${chip_type} "\ - "cpu_rev=${cpu_rev} "\ - "vddee=${vddee_voltage} "\ - "irq_check_en=${Irq_check_en} "\ - "androidboot.hardware="__stringify(BOARD_NAME)" "\ - "androidboot.bl2_boot_part=${bl2_part} "\ - "androidboot.slot_suffix=${active_slot} "\ - "androidboot.firstboot=${firstboot} jtag=${jtag}; "\ - "setenv bootargs ${bootargs};"\ - "\0"\ - "switch_bootmode="\ - "get_rebootmode;"\ - "echo reboot_mode:${reboot_mode};"\ - "if test ${reboot_mode} = factory_boot; then " \ - "setenv bootargs ${bootargs} androidboot.real_reboot_mode=${real_reboot_mode};"\ - "if imgread kernel system_b ${loadaddr_kernel}; then " \ - "bootm ${loadaddr_kernel};"\ - "fi;" \ - "else if test ${reboot_mode} = update; then "\ - "run update;"\ - "else if test ${reboot_mode} = delayed_reboot; then "\ - "delayed_reboot;"\ - "else if test ${reboot_mode} = quiescent; then "\ - "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ - "else if test ${reboot_mode} = cold_boot; then "\ - "fi;fi;fi;fi;fi;"\ - "\0" \ - "storeboot="\ - JUDGE_MODE \ - "setenv loadaddr ${loadaddr_kernel};"\ - "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ - "echo try upgrade as booting failure; run update;"\ - "\0" \ - "update="\ - /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ - "run usb_burning; "\ - "run recovery_from_udisk;"\ - "\0"\ - "recovery_from_fat_dev="\ - "setenv loadaddr ${loadaddr_kernel};"\ - "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img 0x10000000 0; then "\ - "bootm ${loadaddr};fi;"\ - "\0"\ - "recovery_from_udisk="\ - "setenv fatload_dev usb;"\ - "if usb start 0; then run recovery_from_fat_dev; fi;"\ - "\0"\ - "bcb_cmd="\ - "get_valid_slot;"\ - "\0"\ - "ddr_windowing_boot="\ - "ddr_auto_fast_boot_check 6;"\ - "\0"\ - "oqc_check="\ - "setenv test_mode false;"\ - "setenv fatload_dev usb;"\ - "if usb start 0; then "\ - "if fatload ${fatload_dev} 0 ${loadaddr} OQC.txt 0x100000 0; then "\ - "setenv test_mode true;"\ - "fi;"\ - "fi;"\ - "setenv bootargs ${bootargs} androidboot.test_mode=${test_mode};"\ - "\0"\ - "upgrade_and_oqc_key_check="\ - "if gpio input GPIOD_2; then "\ - "echo RESET KEY not pressed;"\ - "else "\ - "echo RESET KEY pressed;"\ - "setenv boot_external_image 1;"\ - "run recovery_from_udisk;"\ - "setenv boot_external_image 0;"\ - "run oqc_check;"\ - "fi;"\ - "\0"\ - "cmdline_keys="\ - "setenv usid 1234567890; setenv region_code US;"\ - "if keyman init 0x1234; then "\ - "if keyman read usid ${loadaddr} str; then fi;"\ - "if keyman read region_code ${loadaddr} str; then fi;"\ - "if keyman read mac ${loadaddr} str; then "\ - "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ - "fi;"\ - "if keyman read deviceid ${loadaddr} str; then "\ - "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ - "fi;"\ - "fi;"\ - "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\ - "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\ - "setenv serial ${usid}; setenv serial# ${usid};"\ - "\0"\ - -#ifdef CONFIG_DDR_WINDOWING_BOOT -#define CONFIG_PREBOOT \ - "run bcb_cmd; "\ - "run run_dspa; "\ - "get_hw_id;" \ - "get_boot_ac_voltage;" \ - "run storeargs;"\ - "run upgrade_and_oqc_key_check;"\ - "run ddr_windowing_boot;"\ - "run switch_bootmode;" -#else -#define CONFIG_PREBOOT \ - "run bcb_cmd; "\ - "run run_dspa; "\ - "get_hw_id;" \ - "get_boot_ac_voltage;" \ - "run storeargs;"\ - "run upgrade_and_oqc_key_check;"\ - "run switch_bootmode;" -#endif - -/* #define CONFIG_ENV_IS_NOWHERE 1 */ -#define CONFIG_ENV_SIZE (8*1024) -#define CONFIG_FIT 1 -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_ANDROID_BOOT_IMAGE 1 -#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ - -/* ATTENTION */ -/* DDR configs move to board/amlogic/[board]/firmware/timing.c */ - -/* running in sram */ -//#define UBOOT_RUN_IN_SRAM -#ifdef UBOOT_RUN_IN_SRAM -#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (256*1024) -#else -#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) -#define CONFIG_SYS_MALLOC_LEN (64*1024*1024) -#endif - -//#define CONFIG_NR_DRAM_BANKS 1 -/* ddr functions */ -#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test -#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp -#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down -#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref -#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function -#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function - -/* storage: emmc/nand/sd */ -#define CONFIG_ENV_OVERWRITE -/* #define CONFIG_CMD_SAVEENV */ -/* fixme, need fix*/ - -#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) -#error env in amlnand/mmc already be compatible; -#endif - -/* -* storage -* |---------|---------| -* | | -* emmc<--Compatible-->nand -* |-------|-------| -* | | -* MTD<-Exclusive->NFTL -* | -* |***************|***************| -* slc-nand SPI-nand SPI-nor -* (raw nand) -*/ -/* axg only support slc nand */ -/* swither for mtd nand which is for slc only. */ - - -#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC) -#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; -#endif - -#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MESON_NFC) -#error CONFIG_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; -#endif - -/* #define CONFIG_AML_SD_EMMC 1 */ -#ifdef CONFIG_AML_SD_EMMC - #define CONFIG_GENERIC_MMC 1 - #define CONFIG_CMD_MMC 1 - #define CONFIG_CMD_GPT 1 - #define CONFIG_SYS_MMC_ENV_DEV 1 - #define CONFIG_EMMC_DDR52_EN 0 - #define CONFIG_EMMC_DDR52_CLK 35000000 -#endif -#define CONFIG_PARTITIONS 1 -#if 0 -#define CONFIG_SYS_NO_FLASH 1 -#endif - -#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND - #define CONFIG_SYS_MAX_NAND_DEVICE 2 -#endif - -/* vpu */ -#define AML_VPU_CLK_LEVEL_DFT 7 - -/* osd */ -#define OSD_SCALE_ENABLE -#define AML_OSD_HIGH_VERSION - -/* USB - * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard - * Enable CONFIG_MUSB_UDD for Device functionalities. - */ -/* #define CONFIG_MUSB_UDC 1 */ -/* #define CONFIG_CMD_USB 1 */ - -#define USB_PHY2_PLL_PARAMETER_1 0x09400414 -#define USB_PHY2_PLL_PARAMETER_2 0x927e0000 -#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5 - -#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18) -#define USB_G12x_PHY_PLL_SETTING_2 (0xfff) -#define USB_G12x_PHY_PLL_SETTING_3 (0x78000) -#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004) -#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c) - -#define AML_TXLX_USB 1 -#define AML_USB_V2 1 -#define USB_GENERAL_BIT 3 -#define USB_PHY21_BIT 4 - -/* UBOOT fastboot config */ - - -/* UBOOT Facotry usb/sdcard burning config */ - -/* net */ -/* #define CONFIG_CMD_NET 1 */ -#define CONFIG_ETH_DESIGNWARE -#if defined(CONFIG_CMD_NET) - #define CONFIG_DESIGNWARE_ETH 1 - #define CONFIG_PHYLIB 1 - #define CONFIG_NET_MULTI 1 - #define CONFIG_CMD_PING 1 - #define CONFIG_CMD_DHCP 1 - #define CONFIG_CMD_RARP 1 - #define CONFIG_HOSTNAME "arm_gxbb" -#if 0 - #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ -#endif - #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ - #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ - #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ - #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ - #define CONFIG_NETMASK 255.255.255.0 -#endif /* (CONFIG_CMD_NET) */ - -#define MAC_ADDR_NEW 1 - -/* other devices */ -#define CONFIG_SHA1 1 -#define CONFIG_MD5 1 - -/* commands */ - -/*file system*/ -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_EFI_PARTITION 1 -/* #define CONFIG_MMC 1 */ -#define CONFIG_FS_FAT 1 -#define CONFIG_FS_EXT4 1 -#define CONFIG_LZO 1 - -/* Cache Definitions */ -/* #define CONFIG_SYS_DCACHE_OFF */ -/* #define CONFIG_SYS_ICACHE_OFF */ - -/* other functions */ -#define CONFIG_LIBAVB 1 -/* top hide for NBG file */ -#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000 - -#define CONFIG_CPU_ARMV8 - -//use sha2 command -#define CONFIG_CMD_SHA2 - -//use hardware sha2 -#define CONFIG_AML_HW_SHA2 - -/* #define CONFIG_MULTI_DTB 1 */ - -/* support secure boot */ -#define CONFIG_AML_SECURE_UBOOT 1 - -#if defined(CONFIG_AML_SECURE_UBOOT) - -/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */ -#define CONFIG_AML_CRYPTO_UBOOT 1 -//#define CONFIG_AML_SIGNED_UBOOT 1 -/* unify build for generate encrypted kernel image - SRC : "board/amlogic/(board)/boot.img" - DST : "fip/boot.img.encrypt" */ -/* #define CONFIG_AML_CRYPTO_IMG 1 */ - -#endif /* CONFIG_AML_SECURE_UBOOT */ - -#define CONFIG_FIP_IMG_SUPPORT 1 - -#endif -
diff --git a/board/amlogic/configs/c2_xua4_bx.h b/board/amlogic/configs/c2_xua4_bx.h deleted file mode 100644 index 28a3c78..0000000 --- a/board/amlogic/configs/c2_xua4_bx.h +++ /dev/null
@@ -1,474 +0,0 @@ - -/* - * Copyright (C) 2015 Amlogic, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -*/ - -#ifndef __BOARD_CFG_H__ -#define __BOARD_CFG_H__ - -#include <asm/arch/cpu.h> - -#define XUA4_HW_CID 0x1 - -/* UBOOT Facotry usb burning config */ -#ifndef AML_DISABLE_UPDATE_MODE -#define CONFIG_AML_V3_FACTORY_BURN 1 -#define CONFIG_AML_V3_USB_TOOl 1 -#define CONFIG_USB_GADGET_DOWNLOAD 1 -#define CONFIG_FASTBOOT_DWC_PCD 1 -#define CONFIG_USB_DEVICE_V2 1 -#endif - -/* enable command line for bringup */ -#ifdef CONFIG_ENABLE_UBOOT_CLI -#define CONFIG_CLI_ENABLED 1 -#endif - -/* - * platform power init config - */ - -#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage -#define AML_VDDEE_INIT_VOLTAGE 801 // VDDEE power up voltage -/*if CONFIG_PDVFS_ENABLE is defined, AML_VCCK_INIT_VOLTAGE will be invalid*/ -#define CONFIG_PDVFS_ENABLE - - -/* SMP Definitinos */ -#define CPU_RELEASE_ADDR secondary_boot_func - -/* Bootloader Control Block function - That is used for recovery and the bootloader to talk to each other - */ -#if 0 -#define CONFIG_BOOTLOADER_CONTROL_BLOCK -#endif - -/* Serial config */ -#define CONFIG_CONS_INDEX 2 -#define CONFIG_BAUDRATE 115200 - -/* Enable ir remote wake up for bl30 */ -#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power -#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+ -#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch- -#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power -#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04 -#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF -#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF -#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF -#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF - -/*config the default parameters for adc power key*/ -#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ -#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ - -#define CONFIG_BOOTLOADER_CONTROL_BLOCK - -#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition -#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}" -#else -#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}" -#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition - -#ifdef AML_ENABLE_PRODUCTION_MODE -#define JUDGE_MODE "echo this is production mode;" -#define CONFIG_AML_PRODUCT_MODE 1 -#ifdef CONFIG_FASTBOOT -#define CONFIG_NO_FASTBOOT_FLASHING 1 -#endif //CONFIG_FASTBOOT -#ifdef CONFIG_MESON_SERIAL -#define CONFIG_DISABLE_AML_SERIAL 1 -#endif //CONFIG_MESON_SERIAL -#define USB_BURNING_OPTION "echo productmode" -#else //AML_ENABLE_PRODUCTION_MODE -#define JUDGE_MODE "echo this is not production mode;" -#define CONFIG_CMD_BOOTD 1 -#if (defined(CONFIG_ARM) && !defined(CONFIG_ARM64)) -#define CONFIG_CMD_BOOTZ 1 -#endif //defined(CONFIG_ARM) && !defined(CONFIG_ARM64) -#ifdef CONFIG_ARM64 -#define CONFIG_CMD_BOOTI 1 -#endif //CONFIG_ARM64 -#define CONFIG_CMD_MEMORY 1 -#define CONFIG_CMD_SOURCE 1 -#ifdef CONFIG_MISC -#define CONFIG_CMD_JTAG 1 -#endif //CONFIG_MISC -#ifdef CONFIG_CMD_BOOTI -#define CONFIG_CMD_LZMADEC 1 -#define CONFIG_CMD_UNZIP 1 -#define CONFIG_LZMA 1 -#endif //CONFIG_CMD_BOOTI -#define USB_BURNING_OPTION "adnl" - -#endif //AML_ENABLE_PRODUCTION_MODE - -/* args/envs */ -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_EXTRA_ENV_SETTINGS \ - "firstboot=1\0"\ - "jtag=disable\0"\ - "loadaddr=0x00020000\0"\ - "loadaddr_kernel=0x01080000\0"\ - "loadaddr_dspa=0x06000000\0"\ - "otg_device=1\0" \ - "usb_burning=" USB_BURNING_OPTION "\0" \ - "fdt_high=0x20000000\0"\ - "EnableSelinux=enforcing\0" \ - "boot_part=boot_a\0"\ - "active_slot=_a\0"\ - "Irq_check_en=0\0"\ - "fatload_dev=usb\0"\ - "initargs="\ - "\0"\ - "upgrade_check="\ - "echo recovery_status=${recovery_status};"\ - "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\ - "run storeargs; run recovery_from_flash;"\ - "else fi;"\ - "echo upgrade_step=${upgrade_step}; "\ - "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\ - "\0"\ - "run_dspa="\ - "unzip 0x6400000 ${loadaddr_dspa};"\ - "dspset 0 1 0;dspset 0 1 1;dsprun 0 ${loadaddr_dspa}; "\ - "\0"\ - "storeargs="\ - "get_rebootmode;"\ - "get_chiptype;"\ - "get_cpu_rev;"\ - "get_ee_vol;"\ - "if test ${reboot_mode} = fastboot; then "\ - "setenv reboot_mode warm_reboot;"\ - "fi;"\ - "setenv bootargs ${initargs} otg_device=${otg_device} "\ - "gpt " \ - "androidboot.reboot_mode=${reboot_mode} "\ - "hw_id=${hw_id} "\ - "boot_ac_voltage=${boot_ac_voltage} "\ - "chip_type=${chip_type} "\ - "cpu_rev=${cpu_rev} "\ - "vddee=${vddee_voltage} "\ - "irq_check_en=${Irq_check_en} "\ - "androidboot.hardware="__stringify(BOARD_NAME)" "\ - "androidboot.bl2_boot_part=${bl2_part} "\ - "androidboot.slot_suffix=${active_slot} "\ - "androidboot.firstboot=${firstboot} jtag=${jtag}; "\ - "setenv bootargs ${bootargs};"\ - "\0"\ - "switch_bootmode="\ - "get_rebootmode;"\ - "echo reboot_mode:${reboot_mode};"\ - "if test ${reboot_mode} = factory_boot; then " \ - "musb bc;" \ - "setenv bootargs ${bootargs} androidboot.charger_type=${charger_type};"\ - "setenv bootargs ${bootargs} androidboot.real_reboot_mode=${real_reboot_mode};"\ - "if imgread kernel system_b ${loadaddr_kernel}; then " \ - "bootm ${loadaddr_kernel};"\ - "fi;" \ - "else if test ${reboot_mode} = update; then "\ - "run update;"\ - "else if test ${reboot_mode} = delayed_reboot; then "\ - "delayed_reboot;"\ - "else if test ${reboot_mode} = quiescent; then "\ - "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ - "else if test ${reboot_mode} = cold_boot; then "\ - "fi;fi;fi;fi;fi;"\ - "\0" \ - "storeboot="\ - JUDGE_MODE \ - "setenv loadaddr ${loadaddr_kernel};"\ - "run usb_bc_check;"\ - "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ - "echo try upgrade as booting failure; run update;"\ - "\0" \ - "update="\ - /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ - "run usb_burning; "\ - "run recovery_from_udisk;"\ - "\0"\ - "recovery_from_fat_dev="\ - "setenv loadaddr ${loadaddr_kernel};"\ - "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img 0x10000000 0; then "\ - "bootm ${loadaddr};fi;"\ - "\0"\ - "recovery_from_udisk="\ - "setenv fatload_dev usb;"\ - "if usb start 0; then run recovery_from_fat_dev; fi;"\ - "\0"\ - "bcb_cmd="\ - "get_valid_slot;"\ - "\0"\ - "ddr_windowing_boot="\ - "ddr_auto_fast_boot_check 6;"\ - "\0"\ - "usb_bc_check=" \ - "musb bc;" \ - "charger_detect_boot;" \ - "setenv bootargs ${bootargs} androidboot.charger_type=${charger_type};"\ - "\0" \ - "oqc_check="\ - "setenv test_mode false;"\ - "setenv fatload_dev usb;"\ - "if usb start 0; then "\ - "if fatload ${fatload_dev} 0 ${loadaddr} OQC.txt 0x100000 0; then "\ - "setenv test_mode true;"\ - "fi;"\ - "fi;"\ - "setenv bootargs ${bootargs} androidboot.test_mode=${test_mode};"\ - "\0"\ - "upgrade_and_oqc_key_check="\ - "if gpio input GPIOD_2; then "\ - "echo RESET KEY not pressed;"\ - "else "\ - "echo RESET KEY pressed;"\ - "setenv boot_external_image 1;"\ - "run recovery_from_udisk;"\ - "setenv boot_external_image 0;"\ - "run oqc_check;"\ - "fi;"\ - "\0"\ - "cmdline_keys="\ - "setenv usid 1234567890; setenv region_code US;"\ - "if keyman init 0x1234; then "\ - "if keyman read usid ${loadaddr} str; then fi;"\ - "if keyman read region_code ${loadaddr} str; then fi;"\ - "if keyman read mac ${loadaddr} str; then "\ - "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ - "fi;"\ - "if keyman read deviceid ${loadaddr} str; then "\ - "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ - "fi;"\ - "fi;"\ - "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\ - "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\ - "setenv serial ${usid}; setenv serial# ${usid};"\ - "\0"\ - -#ifdef CONFIG_DDR_WINDOWING_BOOT -#define CONFIG_PREBOOT \ - "run bcb_cmd; "\ - "run run_dspa; "\ - "get_hw_id;" \ - "get_boot_ac_voltage;" \ - "run storeargs;"\ - "run upgrade_and_oqc_key_check;"\ - "run ddr_windowing_boot;"\ - "run switch_bootmode;" -#else -#define CONFIG_PREBOOT \ - "run bcb_cmd; "\ - "run run_dspa; "\ - "get_hw_id;" \ - "get_boot_ac_voltage;" \ - "run storeargs;"\ - "run upgrade_and_oqc_key_check;"\ - "run switch_bootmode;" -#endif - -/* #define CONFIG_ENV_IS_NOWHERE 1 */ -#define CONFIG_ENV_SIZE (8*1024) -#define CONFIG_FIT 1 -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_ANDROID_BOOT_IMAGE 1 -#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ - -/* ATTENTION */ -/* DDR configs move to board/amlogic/[board]/firmware/timing.c */ - -/* running in sram */ -//#define UBOOT_RUN_IN_SRAM -#ifdef UBOOT_RUN_IN_SRAM -#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (256*1024) -#else -#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) -#define CONFIG_SYS_MALLOC_LEN (64*1024*1024) -#endif - -//#define CONFIG_NR_DRAM_BANKS 1 -/* ddr functions */ -#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test -#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp -#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down -#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref -#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function -#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function - -/* storage: emmc/nand/sd */ -#define CONFIG_ENV_OVERWRITE -/* #define CONFIG_CMD_SAVEENV */ -/* fixme, need fix*/ - -#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) -#error env in amlnand/mmc already be compatible; -#endif - -/* -* storage -* |---------|---------| -* | | -* emmc<--Compatible-->nand -* |-------|-------| -* | | -* MTD<-Exclusive->NFTL -* | -* |***************|***************| -* slc-nand SPI-nand SPI-nor -* (raw nand) -*/ -/* axg only support slc nand */ -/* swither for mtd nand which is for slc only. */ - - -#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC) -#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; -#endif - -#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MESON_NFC) -#error CONFIG_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; -#endif - -/* #define CONFIG_AML_SD_EMMC 1 */ -#ifdef CONFIG_AML_SD_EMMC - #define CONFIG_GENERIC_MMC 1 - #define CONFIG_CMD_MMC 1 - #define CONFIG_CMD_GPT 1 - #define CONFIG_SYS_MMC_ENV_DEV 1 - #define CONFIG_EMMC_DDR52_EN 0 - #define CONFIG_EMMC_DDR52_CLK 35000000 -#endif -#define CONFIG_PARTITIONS 1 -#if 0 -#define CONFIG_SYS_NO_FLASH 1 -#endif - -#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND - #define CONFIG_SYS_MAX_NAND_DEVICE 2 -#endif - -/* vpu */ -#define AML_VPU_CLK_LEVEL_DFT 7 - -/* osd */ -#define OSD_SCALE_ENABLE -#define AML_OSD_HIGH_VERSION - -/* USB - * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard - * Enable CONFIG_MUSB_UDD for Device functionalities. - */ -/* #define CONFIG_MUSB_UDC 1 */ -/* #define CONFIG_CMD_USB 1 */ - -#define USB_PHY2_PLL_PARAMETER_1 0x09400414 -#define USB_PHY2_PLL_PARAMETER_2 0x927e0000 -#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5 - -#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18) -#define USB_G12x_PHY_PLL_SETTING_2 (0xfff) -#define USB_G12x_PHY_PLL_SETTING_3 (0x78000) -#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004) -#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c) - -#define AML_TXLX_USB 1 -#define AML_USB_V2 1 -#define USB_GENERAL_BIT 3 -#define USB_PHY21_BIT 4 - -/* UBOOT fastboot config */ - - -/* UBOOT Facotry usb/sdcard burning config */ - -/* net */ -/* #define CONFIG_CMD_NET 1 */ -#define CONFIG_ETH_DESIGNWARE -#if defined(CONFIG_CMD_NET) - #define CONFIG_DESIGNWARE_ETH 1 - #define CONFIG_PHYLIB 1 - #define CONFIG_NET_MULTI 1 - #define CONFIG_CMD_PING 1 - #define CONFIG_CMD_DHCP 1 - #define CONFIG_CMD_RARP 1 - #define CONFIG_HOSTNAME "arm_gxbb" -#if 0 - #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ -#endif - #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ - #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ - #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ - #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ - #define CONFIG_NETMASK 255.255.255.0 -#endif /* (CONFIG_CMD_NET) */ - -#define MAC_ADDR_NEW 1 - -/* other devices */ -#define CONFIG_SHA1 1 -#define CONFIG_MD5 1 - -/* commands */ - -/*file system*/ -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_EFI_PARTITION 1 -/* #define CONFIG_MMC 1 */ -#define CONFIG_FS_FAT 1 -#define CONFIG_FS_EXT4 1 -#define CONFIG_LZO 1 - -/* Cache Definitions */ -/* #define CONFIG_SYS_DCACHE_OFF */ -/* #define CONFIG_SYS_ICACHE_OFF */ - -/* other functions */ -#define CONFIG_LIBAVB 1 -/* top hide for NBG file */ -#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000 - -#define CONFIG_CPU_ARMV8 - -//use sha2 command -#define CONFIG_CMD_SHA2 - -//use hardware sha2 -#define CONFIG_AML_HW_SHA2 - -/* #define CONFIG_MULTI_DTB 1 */ - -/* support secure boot */ -#define CONFIG_AML_SECURE_UBOOT 1 - -#if defined(CONFIG_AML_SECURE_UBOOT) - -/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */ -#define CONFIG_AML_CRYPTO_UBOOT 1 -//#define CONFIG_AML_SIGNED_UBOOT 1 -/* unify build for generate encrypted kernel image - SRC : "board/amlogic/(board)/boot.img" - DST : "fip/boot.img.encrypt" */ -/* #define CONFIG_AML_CRYPTO_IMG 1 */ - -#endif /* CONFIG_AML_SECURE_UBOOT */ - -#define CONFIG_FIP_IMG_SUPPORT 1 - -#endif -
diff --git a/board/amlogic/configs/c2_xua4_p1.h b/board/amlogic/configs/c2_xua4_p1.h deleted file mode 100644 index 28a3c78..0000000 --- a/board/amlogic/configs/c2_xua4_p1.h +++ /dev/null
@@ -1,474 +0,0 @@ - -/* - * Copyright (C) 2015 Amlogic, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -*/ - -#ifndef __BOARD_CFG_H__ -#define __BOARD_CFG_H__ - -#include <asm/arch/cpu.h> - -#define XUA4_HW_CID 0x1 - -/* UBOOT Facotry usb burning config */ -#ifndef AML_DISABLE_UPDATE_MODE -#define CONFIG_AML_V3_FACTORY_BURN 1 -#define CONFIG_AML_V3_USB_TOOl 1 -#define CONFIG_USB_GADGET_DOWNLOAD 1 -#define CONFIG_FASTBOOT_DWC_PCD 1 -#define CONFIG_USB_DEVICE_V2 1 -#endif - -/* enable command line for bringup */ -#ifdef CONFIG_ENABLE_UBOOT_CLI -#define CONFIG_CLI_ENABLED 1 -#endif - -/* - * platform power init config - */ - -#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage -#define AML_VDDEE_INIT_VOLTAGE 801 // VDDEE power up voltage -/*if CONFIG_PDVFS_ENABLE is defined, AML_VCCK_INIT_VOLTAGE will be invalid*/ -#define CONFIG_PDVFS_ENABLE - - -/* SMP Definitinos */ -#define CPU_RELEASE_ADDR secondary_boot_func - -/* Bootloader Control Block function - That is used for recovery and the bootloader to talk to each other - */ -#if 0 -#define CONFIG_BOOTLOADER_CONTROL_BLOCK -#endif - -/* Serial config */ -#define CONFIG_CONS_INDEX 2 -#define CONFIG_BAUDRATE 115200 - -/* Enable ir remote wake up for bl30 */ -#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power -#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+ -#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch- -#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power -#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04 -#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF -#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF -#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF -#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF - -/*config the default parameters for adc power key*/ -#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ -#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ - -#define CONFIG_BOOTLOADER_CONTROL_BLOCK - -#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition -#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}" -#else -#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}" -#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition - -#ifdef AML_ENABLE_PRODUCTION_MODE -#define JUDGE_MODE "echo this is production mode;" -#define CONFIG_AML_PRODUCT_MODE 1 -#ifdef CONFIG_FASTBOOT -#define CONFIG_NO_FASTBOOT_FLASHING 1 -#endif //CONFIG_FASTBOOT -#ifdef CONFIG_MESON_SERIAL -#define CONFIG_DISABLE_AML_SERIAL 1 -#endif //CONFIG_MESON_SERIAL -#define USB_BURNING_OPTION "echo productmode" -#else //AML_ENABLE_PRODUCTION_MODE -#define JUDGE_MODE "echo this is not production mode;" -#define CONFIG_CMD_BOOTD 1 -#if (defined(CONFIG_ARM) && !defined(CONFIG_ARM64)) -#define CONFIG_CMD_BOOTZ 1 -#endif //defined(CONFIG_ARM) && !defined(CONFIG_ARM64) -#ifdef CONFIG_ARM64 -#define CONFIG_CMD_BOOTI 1 -#endif //CONFIG_ARM64 -#define CONFIG_CMD_MEMORY 1 -#define CONFIG_CMD_SOURCE 1 -#ifdef CONFIG_MISC -#define CONFIG_CMD_JTAG 1 -#endif //CONFIG_MISC -#ifdef CONFIG_CMD_BOOTI -#define CONFIG_CMD_LZMADEC 1 -#define CONFIG_CMD_UNZIP 1 -#define CONFIG_LZMA 1 -#endif //CONFIG_CMD_BOOTI -#define USB_BURNING_OPTION "adnl" - -#endif //AML_ENABLE_PRODUCTION_MODE - -/* args/envs */ -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_EXTRA_ENV_SETTINGS \ - "firstboot=1\0"\ - "jtag=disable\0"\ - "loadaddr=0x00020000\0"\ - "loadaddr_kernel=0x01080000\0"\ - "loadaddr_dspa=0x06000000\0"\ - "otg_device=1\0" \ - "usb_burning=" USB_BURNING_OPTION "\0" \ - "fdt_high=0x20000000\0"\ - "EnableSelinux=enforcing\0" \ - "boot_part=boot_a\0"\ - "active_slot=_a\0"\ - "Irq_check_en=0\0"\ - "fatload_dev=usb\0"\ - "initargs="\ - "\0"\ - "upgrade_check="\ - "echo recovery_status=${recovery_status};"\ - "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\ - "run storeargs; run recovery_from_flash;"\ - "else fi;"\ - "echo upgrade_step=${upgrade_step}; "\ - "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\ - "\0"\ - "run_dspa="\ - "unzip 0x6400000 ${loadaddr_dspa};"\ - "dspset 0 1 0;dspset 0 1 1;dsprun 0 ${loadaddr_dspa}; "\ - "\0"\ - "storeargs="\ - "get_rebootmode;"\ - "get_chiptype;"\ - "get_cpu_rev;"\ - "get_ee_vol;"\ - "if test ${reboot_mode} = fastboot; then "\ - "setenv reboot_mode warm_reboot;"\ - "fi;"\ - "setenv bootargs ${initargs} otg_device=${otg_device} "\ - "gpt " \ - "androidboot.reboot_mode=${reboot_mode} "\ - "hw_id=${hw_id} "\ - "boot_ac_voltage=${boot_ac_voltage} "\ - "chip_type=${chip_type} "\ - "cpu_rev=${cpu_rev} "\ - "vddee=${vddee_voltage} "\ - "irq_check_en=${Irq_check_en} "\ - "androidboot.hardware="__stringify(BOARD_NAME)" "\ - "androidboot.bl2_boot_part=${bl2_part} "\ - "androidboot.slot_suffix=${active_slot} "\ - "androidboot.firstboot=${firstboot} jtag=${jtag}; "\ - "setenv bootargs ${bootargs};"\ - "\0"\ - "switch_bootmode="\ - "get_rebootmode;"\ - "echo reboot_mode:${reboot_mode};"\ - "if test ${reboot_mode} = factory_boot; then " \ - "musb bc;" \ - "setenv bootargs ${bootargs} androidboot.charger_type=${charger_type};"\ - "setenv bootargs ${bootargs} androidboot.real_reboot_mode=${real_reboot_mode};"\ - "if imgread kernel system_b ${loadaddr_kernel}; then " \ - "bootm ${loadaddr_kernel};"\ - "fi;" \ - "else if test ${reboot_mode} = update; then "\ - "run update;"\ - "else if test ${reboot_mode} = delayed_reboot; then "\ - "delayed_reboot;"\ - "else if test ${reboot_mode} = quiescent; then "\ - "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ - "else if test ${reboot_mode} = cold_boot; then "\ - "fi;fi;fi;fi;fi;"\ - "\0" \ - "storeboot="\ - JUDGE_MODE \ - "setenv loadaddr ${loadaddr_kernel};"\ - "run usb_bc_check;"\ - "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ - "echo try upgrade as booting failure; run update;"\ - "\0" \ - "update="\ - /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ - "run usb_burning; "\ - "run recovery_from_udisk;"\ - "\0"\ - "recovery_from_fat_dev="\ - "setenv loadaddr ${loadaddr_kernel};"\ - "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img 0x10000000 0; then "\ - "bootm ${loadaddr};fi;"\ - "\0"\ - "recovery_from_udisk="\ - "setenv fatload_dev usb;"\ - "if usb start 0; then run recovery_from_fat_dev; fi;"\ - "\0"\ - "bcb_cmd="\ - "get_valid_slot;"\ - "\0"\ - "ddr_windowing_boot="\ - "ddr_auto_fast_boot_check 6;"\ - "\0"\ - "usb_bc_check=" \ - "musb bc;" \ - "charger_detect_boot;" \ - "setenv bootargs ${bootargs} androidboot.charger_type=${charger_type};"\ - "\0" \ - "oqc_check="\ - "setenv test_mode false;"\ - "setenv fatload_dev usb;"\ - "if usb start 0; then "\ - "if fatload ${fatload_dev} 0 ${loadaddr} OQC.txt 0x100000 0; then "\ - "setenv test_mode true;"\ - "fi;"\ - "fi;"\ - "setenv bootargs ${bootargs} androidboot.test_mode=${test_mode};"\ - "\0"\ - "upgrade_and_oqc_key_check="\ - "if gpio input GPIOD_2; then "\ - "echo RESET KEY not pressed;"\ - "else "\ - "echo RESET KEY pressed;"\ - "setenv boot_external_image 1;"\ - "run recovery_from_udisk;"\ - "setenv boot_external_image 0;"\ - "run oqc_check;"\ - "fi;"\ - "\0"\ - "cmdline_keys="\ - "setenv usid 1234567890; setenv region_code US;"\ - "if keyman init 0x1234; then "\ - "if keyman read usid ${loadaddr} str; then fi;"\ - "if keyman read region_code ${loadaddr} str; then fi;"\ - "if keyman read mac ${loadaddr} str; then "\ - "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ - "fi;"\ - "if keyman read deviceid ${loadaddr} str; then "\ - "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ - "fi;"\ - "fi;"\ - "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\ - "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\ - "setenv serial ${usid}; setenv serial# ${usid};"\ - "\0"\ - -#ifdef CONFIG_DDR_WINDOWING_BOOT -#define CONFIG_PREBOOT \ - "run bcb_cmd; "\ - "run run_dspa; "\ - "get_hw_id;" \ - "get_boot_ac_voltage;" \ - "run storeargs;"\ - "run upgrade_and_oqc_key_check;"\ - "run ddr_windowing_boot;"\ - "run switch_bootmode;" -#else -#define CONFIG_PREBOOT \ - "run bcb_cmd; "\ - "run run_dspa; "\ - "get_hw_id;" \ - "get_boot_ac_voltage;" \ - "run storeargs;"\ - "run upgrade_and_oqc_key_check;"\ - "run switch_bootmode;" -#endif - -/* #define CONFIG_ENV_IS_NOWHERE 1 */ -#define CONFIG_ENV_SIZE (8*1024) -#define CONFIG_FIT 1 -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_ANDROID_BOOT_IMAGE 1 -#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ - -/* ATTENTION */ -/* DDR configs move to board/amlogic/[board]/firmware/timing.c */ - -/* running in sram */ -//#define UBOOT_RUN_IN_SRAM -#ifdef UBOOT_RUN_IN_SRAM -#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (256*1024) -#else -#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) -#define CONFIG_SYS_MALLOC_LEN (64*1024*1024) -#endif - -//#define CONFIG_NR_DRAM_BANKS 1 -/* ddr functions */ -#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test -#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp -#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down -#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref -#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function -#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function - -/* storage: emmc/nand/sd */ -#define CONFIG_ENV_OVERWRITE -/* #define CONFIG_CMD_SAVEENV */ -/* fixme, need fix*/ - -#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) -#error env in amlnand/mmc already be compatible; -#endif - -/* -* storage -* |---------|---------| -* | | -* emmc<--Compatible-->nand -* |-------|-------| -* | | -* MTD<-Exclusive->NFTL -* | -* |***************|***************| -* slc-nand SPI-nand SPI-nor -* (raw nand) -*/ -/* axg only support slc nand */ -/* swither for mtd nand which is for slc only. */ - - -#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC) -#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; -#endif - -#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MESON_NFC) -#error CONFIG_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; -#endif - -/* #define CONFIG_AML_SD_EMMC 1 */ -#ifdef CONFIG_AML_SD_EMMC - #define CONFIG_GENERIC_MMC 1 - #define CONFIG_CMD_MMC 1 - #define CONFIG_CMD_GPT 1 - #define CONFIG_SYS_MMC_ENV_DEV 1 - #define CONFIG_EMMC_DDR52_EN 0 - #define CONFIG_EMMC_DDR52_CLK 35000000 -#endif -#define CONFIG_PARTITIONS 1 -#if 0 -#define CONFIG_SYS_NO_FLASH 1 -#endif - -#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND - #define CONFIG_SYS_MAX_NAND_DEVICE 2 -#endif - -/* vpu */ -#define AML_VPU_CLK_LEVEL_DFT 7 - -/* osd */ -#define OSD_SCALE_ENABLE -#define AML_OSD_HIGH_VERSION - -/* USB - * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard - * Enable CONFIG_MUSB_UDD for Device functionalities. - */ -/* #define CONFIG_MUSB_UDC 1 */ -/* #define CONFIG_CMD_USB 1 */ - -#define USB_PHY2_PLL_PARAMETER_1 0x09400414 -#define USB_PHY2_PLL_PARAMETER_2 0x927e0000 -#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5 - -#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18) -#define USB_G12x_PHY_PLL_SETTING_2 (0xfff) -#define USB_G12x_PHY_PLL_SETTING_3 (0x78000) -#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004) -#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c) - -#define AML_TXLX_USB 1 -#define AML_USB_V2 1 -#define USB_GENERAL_BIT 3 -#define USB_PHY21_BIT 4 - -/* UBOOT fastboot config */ - - -/* UBOOT Facotry usb/sdcard burning config */ - -/* net */ -/* #define CONFIG_CMD_NET 1 */ -#define CONFIG_ETH_DESIGNWARE -#if defined(CONFIG_CMD_NET) - #define CONFIG_DESIGNWARE_ETH 1 - #define CONFIG_PHYLIB 1 - #define CONFIG_NET_MULTI 1 - #define CONFIG_CMD_PING 1 - #define CONFIG_CMD_DHCP 1 - #define CONFIG_CMD_RARP 1 - #define CONFIG_HOSTNAME "arm_gxbb" -#if 0 - #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ -#endif - #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ - #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ - #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ - #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ - #define CONFIG_NETMASK 255.255.255.0 -#endif /* (CONFIG_CMD_NET) */ - -#define MAC_ADDR_NEW 1 - -/* other devices */ -#define CONFIG_SHA1 1 -#define CONFIG_MD5 1 - -/* commands */ - -/*file system*/ -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_EFI_PARTITION 1 -/* #define CONFIG_MMC 1 */ -#define CONFIG_FS_FAT 1 -#define CONFIG_FS_EXT4 1 -#define CONFIG_LZO 1 - -/* Cache Definitions */ -/* #define CONFIG_SYS_DCACHE_OFF */ -/* #define CONFIG_SYS_ICACHE_OFF */ - -/* other functions */ -#define CONFIG_LIBAVB 1 -/* top hide for NBG file */ -#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000 - -#define CONFIG_CPU_ARMV8 - -//use sha2 command -#define CONFIG_CMD_SHA2 - -//use hardware sha2 -#define CONFIG_AML_HW_SHA2 - -/* #define CONFIG_MULTI_DTB 1 */ - -/* support secure boot */ -#define CONFIG_AML_SECURE_UBOOT 1 - -#if defined(CONFIG_AML_SECURE_UBOOT) - -/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */ -#define CONFIG_AML_CRYPTO_UBOOT 1 -//#define CONFIG_AML_SIGNED_UBOOT 1 -/* unify build for generate encrypted kernel image - SRC : "board/amlogic/(board)/boot.img" - DST : "fip/boot.img.encrypt" */ -/* #define CONFIG_AML_CRYPTO_IMG 1 */ - -#endif /* CONFIG_AML_SECURE_UBOOT */ - -#define CONFIG_FIP_IMG_SUPPORT 1 - -#endif -
diff --git a/board/amlogic/defconfigs/c2_2rs4_p1_defconfig b/board/amlogic/defconfigs/c2_2rs4_p1_defconfig deleted file mode 100644 index 0ae47f0..0000000 --- a/board/amlogic/defconfigs/c2_2rs4_p1_defconfig +++ /dev/null
@@ -1,113 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MESON=y -CONFIG_SYS_TEXT_BASE=0x00000000 -CONFIG_MESON_C2=y -# CONFIG_PXP_EMULATOR is not set -CONFIG_AML_TSENSOR=y -CONFIG_AML_TSENSOR_COOL=y -CONFIG_NEED_BL32=y -CONFIG_C2_2RS4_P1=y -CONFIG_DEBUG_UART_BASE=0xfe001c00 -CONFIG_DEBUG_UART_CLOCK=24000000 -CONFIG_DEBUG_UART=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTCOMMAND="run storeboot" -CONFIG_BOARD_LATE_INIT=y -# CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_SYS_PROMPT="c2_2rs4_p1# " -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_IMI is not set -CONFIG_CMD_CLKMSR=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_MMC=y -CONFIG_CMD_MTD=y -CONFIG_AML_STORAGE=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_SARADC=y -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_MISC is not set -CONFIG_CMD_MTDPARTS=y -CONFIG_AML_STORAGE=y -CONFIG_CMD_RSVMEM=y -CONFIG_CMD_WATCHDOG=y -CONFIG_CMD_JTAG=y -CONFIG_AML_PARTITION=y -CONFIG_OF_CONTROL=y -CONFIG_OF_EMBED=y -CONFIG_DEFAULT_DEVICE_TREE="meson-c2-c325x-2rs4" -# CONFIG_REGMAP is not set -CONFIG_ADC=y -CONFIG_SARADC_MESON=y -CONFIG_SARADC_MESON_C2=y -CONFIG_CLK=y -CONFIG_CLK_MESON=y -CONFIG_CLK_MESON_C2=y -CONFIG_USB_FUNCTION_FASTBOOT=n -CONFIG_DM_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_MESON=y -CONFIG_MISC=y -CONFIG_DM_MMC=y -CONFIG_MMC_HS200_SUPPORT=y -CONFIG_MMC_MESON_GX=y -CONFIG_MTD=y -CONFIG_AML_MTDPART=y -CONFIG_NAND=y -CONFIG_DM_SPI_FLASH=y -CONFIG_PHY=y -CONFIG_AML_USB3_PHY=y -CONFIG_AML_USB2_PHY=y -CONFIG_PINCTRL=y -CONFIG_PINCONF=y -CONFIG_PINCTRL_MESON_C2=y -CONFIG_DM_REGULATOR=y -CONFIG_DEBUG_UART_MESON=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_DEBUG_UART_SKIP_INIT=y -CONFIG_MESON_SERIAL=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_AML_SPIFCV2=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_AML_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e -CONFIG_WDT=y -CONFIG_WDT_MESON=y -CONFIG_AML_DRIVER=y -CONFIG_AML_MEDIA=y -CONFIG_EFUSE=y -CONFIG_SHA1=y -CONFIG_SHA256=y -CONFIG_OF_LIBFDT_OVERLAY=n -CONFIG_SECURE_POWER_CONTROL=y -CONFIG_AML_GPT=y -CONFIG_AML_REMOVE_BOOTLOADER_PARTITION=y -CONFIG_IMG_SECURE_CHECK_SZ=66060288 -CONFIG_CMD_FACTORY_BOOT=y -CONFIG_CMD_REBOOT=y -CONFIG_AML_RPMB_DISABLE=y -CONFIG_CMD_BOOTCTOL_AVB=y -CONFIG_G_AB_SYSTEM=y -CONFIG_LZ4=y -CONFIG_CMD_UNZIP=y -CONFIG_CMD_GET_CHIPTYPE=y -CONFIG_I2C_REGULATOR=n -CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY=y -CONFIG_SCHUMACHER_SSR=n -# CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_BOOTZ is not set -# CONFIG_CMD_BOOTI is not set -# CONFIG_CMD_MEMORY is not set -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_JTAG is not set -CONFIG_LOGLEVEL=7
diff --git a/board/amlogic/defconfigs/c2_2rs4_p2_defconfig b/board/amlogic/defconfigs/c2_2rs4_p2_defconfig deleted file mode 100644 index 8d3b994..0000000 --- a/board/amlogic/defconfigs/c2_2rs4_p2_defconfig +++ /dev/null
@@ -1,113 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MESON=y -CONFIG_SYS_TEXT_BASE=0x00000000 -CONFIG_MESON_C2=y -# CONFIG_PXP_EMULATOR is not set -CONFIG_AML_TSENSOR=y -CONFIG_AML_TSENSOR_COOL=y -CONFIG_NEED_BL32=y -CONFIG_C2_2RS4_P2=y -CONFIG_DEBUG_UART_BASE=0xfe001c00 -CONFIG_DEBUG_UART_CLOCK=24000000 -CONFIG_DEBUG_UART=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTCOMMAND="run storeboot" -CONFIG_BOARD_LATE_INIT=y -# CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_SYS_PROMPT="c2_2rs4_p2# " -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_IMI is not set -CONFIG_CMD_CLKMSR=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_MMC=y -CONFIG_CMD_MTD=y -CONFIG_AML_STORAGE=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_SARADC=y -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_MISC is not set -CONFIG_CMD_MTDPARTS=y -CONFIG_AML_STORAGE=y -CONFIG_CMD_RSVMEM=y -CONFIG_CMD_WATCHDOG=y -CONFIG_CMD_JTAG=y -CONFIG_AML_PARTITION=y -CONFIG_OF_CONTROL=y -CONFIG_OF_EMBED=y -CONFIG_DEFAULT_DEVICE_TREE="meson-c2-c325x-2rs4" -# CONFIG_REGMAP is not set -CONFIG_ADC=y -CONFIG_SARADC_MESON=y -CONFIG_SARADC_MESON_C2=y -CONFIG_CLK=y -CONFIG_CLK_MESON=y -CONFIG_CLK_MESON_C2=y -CONFIG_USB_FUNCTION_FASTBOOT=n -CONFIG_DM_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_MESON=y -CONFIG_MISC=y -CONFIG_DM_MMC=y -CONFIG_MMC_HS200_SUPPORT=y -CONFIG_MMC_MESON_GX=y -CONFIG_MTD=y -CONFIG_AML_MTDPART=y -CONFIG_NAND=y -CONFIG_DM_SPI_FLASH=y -CONFIG_PHY=y -CONFIG_AML_USB3_PHY=y -CONFIG_AML_USB2_PHY=y -CONFIG_PINCTRL=y -CONFIG_PINCONF=y -CONFIG_PINCTRL_MESON_C2=y -CONFIG_DM_REGULATOR=y -CONFIG_DEBUG_UART_MESON=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_DEBUG_UART_SKIP_INIT=y -CONFIG_MESON_SERIAL=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_AML_SPIFCV2=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_AML_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e -CONFIG_WDT=y -CONFIG_WDT_MESON=y -CONFIG_AML_DRIVER=y -CONFIG_AML_MEDIA=y -CONFIG_EFUSE=y -CONFIG_SHA1=y -CONFIG_SHA256=y -CONFIG_OF_LIBFDT_OVERLAY=n -CONFIG_SECURE_POWER_CONTROL=y -CONFIG_AML_GPT=y -CONFIG_AML_REMOVE_BOOTLOADER_PARTITION=y -CONFIG_IMG_SECURE_CHECK_SZ=66060288 -CONFIG_CMD_FACTORY_BOOT=y -CONFIG_CMD_REBOOT=y -CONFIG_AML_RPMB_DISABLE=y -CONFIG_CMD_BOOTCTOL_AVB=y -CONFIG_G_AB_SYSTEM=y -CONFIG_LZ4=y -CONFIG_CMD_UNZIP=y -CONFIG_CMD_GET_CHIPTYPE=y -CONFIG_I2C_REGULATOR=n -CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY=y -CONFIG_SCHUMACHER_SSR=n -# CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_BOOTZ is not set -# CONFIG_CMD_BOOTI is not set -# CONFIG_CMD_MEMORY is not set -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_JTAG is not set -CONFIG_LOGLEVEL=7
diff --git a/board/amlogic/defconfigs/c2_bla4_bx_defconfig b/board/amlogic/defconfigs/c2_bla4_bx_defconfig deleted file mode 100644 index ec1246a..0000000 --- a/board/amlogic/defconfigs/c2_bla4_bx_defconfig +++ /dev/null
@@ -1,117 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MESON=y -CONFIG_SYS_TEXT_BASE=0x00000000 -CONFIG_MESON_C2=y -# CONFIG_PXP_EMULATOR is not set -CONFIG_AML_TSENSOR=y -CONFIG_AML_TSENSOR_COOL=y -CONFIG_NEED_BL32=y -CONFIG_C2_BLA4_BX=y -CONFIG_DEBUG_UART_BASE=0xfe001c00 -CONFIG_DEBUG_UART_CLOCK=24000000 -CONFIG_DEBUG_UART=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTCOMMAND="run storeboot" -CONFIG_BOARD_LATE_INIT=y -# CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_SYS_PROMPT="c2_bla4_bx# " -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_IMI is not set -CONFIG_CMD_CLKMSR=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_MMC=y -CONFIG_CMD_MTD=y -CONFIG_AML_STORAGE=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_SARADC=y -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_MISC is not set -CONFIG_CMD_MTDPARTS=y -CONFIG_AML_STORAGE=y -CONFIG_CMD_RSVMEM=y -CONFIG_CMD_WATCHDOG=y -CONFIG_CMD_JTAG=y -CONFIG_AML_PARTITION=y -CONFIG_OF_CONTROL=y -CONFIG_OF_EMBED=y -CONFIG_DEFAULT_DEVICE_TREE="meson-c2-c325x-bla4" -# CONFIG_REGMAP is not set -CONFIG_ADC=y -CONFIG_SARADC_MESON=y -CONFIG_SARADC_MESON_C2=y -CONFIG_CLK=y -CONFIG_CLK_MESON=y -CONFIG_CLK_MESON_C2=y -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_DM_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_MESON=y -CONFIG_MISC=y -CONFIG_DM_MMC=y -CONFIG_MMC_HS200_SUPPORT=y -CONFIG_MMC_MESON_GX=y -CONFIG_MTD=y -CONFIG_AML_MTDPART=y -CONFIG_NAND=y -CONFIG_DM_SPI_FLASH=y -CONFIG_PHY=y -CONFIG_AML_USB3_PHY=y -CONFIG_AML_USB2_PHY=y -CONFIG_PINCTRL=y -CONFIG_PINCONF=y -CONFIG_PINCTRL_MESON_C2=y -CONFIG_DM_REGULATOR=y -CONFIG_DEBUG_UART_MESON=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_DEBUG_UART_SKIP_INIT=y -CONFIG_MESON_SERIAL=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_AML_SPIFCV2=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_AML_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e -CONFIG_WDT=y -CONFIG_WDT_MESON=y -CONFIG_AML_DRIVER=y -CONFIG_AML_MEDIA=y -CONFIG_EFUSE=y -CONFIG_SHA1=y -CONFIG_SHA256=y -CONFIG_OF_LIBFDT_OVERLAY=n -CONFIG_SECURE_POWER_CONTROL=y -CONFIG_AML_GPT=y -CONFIG_AML_REMOVE_BOOTLOADER_PARTITION=y -CONFIG_IMG_SECURE_CHECK_SZ=66060288 -CONFIG_CMD_FACTORY_BOOT=y -CONFIG_CMD_REBOOT=y -CONFIG_AML_RPMB_DISABLE=y -CONFIG_CMD_BOOTCTOL_AVB=y -CONFIG_G_AB_SYSTEM=y -CONFIG_LZ4=y -CONFIG_CMD_UNZIP=y -CONFIG_CMD_GET_CHIPTYPE=y -CONFIG_I2C_REGULATOR=n -CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY=y -CONFIG_SCHUMACHER_SSR=n -# CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_BOOTZ is not set -# CONFIG_CMD_BOOTI is not set -# CONFIG_CMD_MEMORY is not set -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_JTAG is not set -CONFIG_LOGLEVEL=7 -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=1 -CONFIG_CMD_SAVEENV=y -CONFIG_ENV_IS_IN_STORAGE=y
diff --git a/board/amlogic/defconfigs/c2_bla4_p0_defconfig b/board/amlogic/defconfigs/c2_bla4_p0_defconfig deleted file mode 100644 index 5027107..0000000 --- a/board/amlogic/defconfigs/c2_bla4_p0_defconfig +++ /dev/null
@@ -1,113 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MESON=y -CONFIG_SYS_TEXT_BASE=0x00000000 -CONFIG_MESON_C2=y -# CONFIG_PXP_EMULATOR is not set -CONFIG_AML_TSENSOR=y -CONFIG_AML_TSENSOR_COOL=y -CONFIG_NEED_BL32=y -CONFIG_C2_BLA4_P0=y -CONFIG_DEBUG_UART_BASE=0xfe001c00 -CONFIG_DEBUG_UART_CLOCK=24000000 -CONFIG_DEBUG_UART=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTCOMMAND="run storeboot" -CONFIG_BOARD_LATE_INIT=y -# CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_SYS_PROMPT="c2_bla4_p0# " -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_IMI is not set -CONFIG_CMD_CLKMSR=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_MMC=y -CONFIG_CMD_MTD=y -CONFIG_AML_STORAGE=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_SARADC=y -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_MISC is not set -CONFIG_CMD_MTDPARTS=y -CONFIG_AML_STORAGE=y -CONFIG_CMD_RSVMEM=y -CONFIG_CMD_WATCHDOG=y -CONFIG_CMD_JTAG=y -CONFIG_AML_PARTITION=y -CONFIG_OF_CONTROL=y -CONFIG_OF_EMBED=y -CONFIG_DEFAULT_DEVICE_TREE="meson-c2-c325x-bla4" -# CONFIG_REGMAP is not set -CONFIG_ADC=y -CONFIG_SARADC_MESON=y -CONFIG_SARADC_MESON_C2=y -CONFIG_CLK=y -CONFIG_CLK_MESON=y -CONFIG_CLK_MESON_C2=y -CONFIG_USB_FUNCTION_FASTBOOT=n -CONFIG_DM_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_MESON=y -CONFIG_MISC=y -CONFIG_DM_MMC=y -CONFIG_MMC_HS200_SUPPORT=y -CONFIG_MMC_MESON_GX=y -CONFIG_MTD=y -CONFIG_AML_MTDPART=y -CONFIG_NAND=y -CONFIG_DM_SPI_FLASH=y -CONFIG_PHY=y -CONFIG_AML_USB3_PHY=y -CONFIG_AML_USB2_PHY=y -CONFIG_PINCTRL=y -CONFIG_PINCONF=y -CONFIG_PINCTRL_MESON_C2=y -CONFIG_DM_REGULATOR=y -CONFIG_DEBUG_UART_MESON=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_DEBUG_UART_SKIP_INIT=y -CONFIG_MESON_SERIAL=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_AML_SPIFCV2=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_AML_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e -CONFIG_WDT=y -CONFIG_WDT_MESON=y -CONFIG_AML_DRIVER=y -CONFIG_AML_MEDIA=y -CONFIG_EFUSE=y -CONFIG_SHA1=y -CONFIG_SHA256=y -CONFIG_OF_LIBFDT_OVERLAY=n -CONFIG_SECURE_POWER_CONTROL=y -CONFIG_AML_GPT=y -CONFIG_AML_REMOVE_BOOTLOADER_PARTITION=y -CONFIG_IMG_SECURE_CHECK_SZ=66060288 -CONFIG_CMD_FACTORY_BOOT=y -CONFIG_CMD_REBOOT=y -CONFIG_AML_RPMB_DISABLE=y -CONFIG_CMD_BOOTCTOL_AVB=y -CONFIG_G_AB_SYSTEM=y -CONFIG_LZ4=y -CONFIG_CMD_UNZIP=y -CONFIG_CMD_GET_CHIPTYPE=y -CONFIG_I2C_REGULATOR=n -CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY=y -CONFIG_SCHUMACHER_SSR=n -# CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_BOOTZ is not set -# CONFIG_CMD_BOOTI is not set -# CONFIG_CMD_MEMORY is not set -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_JTAG is not set -CONFIG_LOGLEVEL=7
diff --git a/board/amlogic/defconfigs/c2_bla4_p1_defconfig b/board/amlogic/defconfigs/c2_bla4_p1_defconfig deleted file mode 100644 index fcc5978..0000000 --- a/board/amlogic/defconfigs/c2_bla4_p1_defconfig +++ /dev/null
@@ -1,117 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MESON=y -CONFIG_SYS_TEXT_BASE=0x00000000 -CONFIG_MESON_C2=y -# CONFIG_PXP_EMULATOR is not set -CONFIG_AML_TSENSOR=y -CONFIG_AML_TSENSOR_COOL=y -CONFIG_NEED_BL32=y -CONFIG_C2_BLA4_P1=y -CONFIG_DEBUG_UART_BASE=0xfe001c00 -CONFIG_DEBUG_UART_CLOCK=24000000 -CONFIG_DEBUG_UART=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTCOMMAND="run storeboot" -CONFIG_BOARD_LATE_INIT=y -# CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_SYS_PROMPT="c2_bla4_p1# " -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_IMI is not set -CONFIG_CMD_CLKMSR=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_MMC=y -CONFIG_CMD_MTD=y -CONFIG_AML_STORAGE=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_SARADC=y -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_MISC is not set -CONFIG_CMD_MTDPARTS=y -CONFIG_AML_STORAGE=y -CONFIG_CMD_RSVMEM=y -CONFIG_CMD_WATCHDOG=y -CONFIG_CMD_JTAG=y -CONFIG_AML_PARTITION=y -CONFIG_OF_CONTROL=y -CONFIG_OF_EMBED=y -CONFIG_DEFAULT_DEVICE_TREE="meson-c2-c325x-bla4" -# CONFIG_REGMAP is not set -CONFIG_ADC=y -CONFIG_SARADC_MESON=y -CONFIG_SARADC_MESON_C2=y -CONFIG_CLK=y -CONFIG_CLK_MESON=y -CONFIG_CLK_MESON_C2=y -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_DM_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_MESON=y -CONFIG_MISC=y -CONFIG_DM_MMC=y -CONFIG_MMC_HS200_SUPPORT=y -CONFIG_MMC_MESON_GX=y -CONFIG_MTD=y -CONFIG_AML_MTDPART=y -CONFIG_NAND=y -CONFIG_DM_SPI_FLASH=y -CONFIG_PHY=y -CONFIG_AML_USB3_PHY=y -CONFIG_AML_USB2_PHY=y -CONFIG_PINCTRL=y -CONFIG_PINCONF=y -CONFIG_PINCTRL_MESON_C2=y -CONFIG_DM_REGULATOR=y -CONFIG_DEBUG_UART_MESON=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_DEBUG_UART_SKIP_INIT=y -CONFIG_MESON_SERIAL=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_AML_SPIFCV2=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_AML_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e -CONFIG_WDT=y -CONFIG_WDT_MESON=y -CONFIG_AML_DRIVER=y -CONFIG_AML_MEDIA=y -CONFIG_EFUSE=y -CONFIG_SHA1=y -CONFIG_SHA256=y -CONFIG_OF_LIBFDT_OVERLAY=n -CONFIG_SECURE_POWER_CONTROL=y -CONFIG_AML_GPT=y -CONFIG_AML_REMOVE_BOOTLOADER_PARTITION=y -CONFIG_IMG_SECURE_CHECK_SZ=66060288 -CONFIG_CMD_FACTORY_BOOT=y -CONFIG_CMD_REBOOT=y -CONFIG_AML_RPMB_DISABLE=y -CONFIG_CMD_BOOTCTOL_AVB=y -CONFIG_G_AB_SYSTEM=y -CONFIG_LZ4=y -CONFIG_CMD_UNZIP=y -CONFIG_CMD_GET_CHIPTYPE=y -CONFIG_I2C_REGULATOR=n -CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY=y -CONFIG_SCHUMACHER_SSR=n -# CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_BOOTZ is not set -# CONFIG_CMD_BOOTI is not set -# CONFIG_CMD_MEMORY is not set -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_JTAG is not set -CONFIG_LOGLEVEL=7 -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=1 -CONFIG_CMD_SAVEENV=y -CONFIG_ENV_IS_IN_STORAGE=y
diff --git a/board/amlogic/defconfigs/c2_bla4_p2_defconfig b/board/amlogic/defconfigs/c2_bla4_p2_defconfig deleted file mode 100644 index 925f294..0000000 --- a/board/amlogic/defconfigs/c2_bla4_p2_defconfig +++ /dev/null
@@ -1,117 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MESON=y -CONFIG_SYS_TEXT_BASE=0x00000000 -CONFIG_MESON_C2=y -# CONFIG_PXP_EMULATOR is not set -CONFIG_AML_TSENSOR=y -CONFIG_AML_TSENSOR_COOL=y -CONFIG_NEED_BL32=y -CONFIG_C2_BLA4_P2=y -CONFIG_DEBUG_UART_BASE=0xfe001c00 -CONFIG_DEBUG_UART_CLOCK=24000000 -CONFIG_DEBUG_UART=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTCOMMAND="run storeboot" -CONFIG_BOARD_LATE_INIT=y -# CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_SYS_PROMPT="c2_bla4_p2# " -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_IMI is not set -CONFIG_CMD_CLKMSR=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_MMC=y -CONFIG_CMD_MTD=y -CONFIG_AML_STORAGE=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_SARADC=y -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_MISC is not set -CONFIG_CMD_MTDPARTS=y -CONFIG_AML_STORAGE=y -CONFIG_CMD_RSVMEM=y -CONFIG_CMD_WATCHDOG=y -CONFIG_CMD_JTAG=y -CONFIG_AML_PARTITION=y -CONFIG_OF_CONTROL=y -CONFIG_OF_EMBED=y -CONFIG_DEFAULT_DEVICE_TREE="meson-c2-c325x-bla4" -# CONFIG_REGMAP is not set -CONFIG_ADC=y -CONFIG_SARADC_MESON=y -CONFIG_SARADC_MESON_C2=y -CONFIG_CLK=y -CONFIG_CLK_MESON=y -CONFIG_CLK_MESON_C2=y -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_DM_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_MESON=y -CONFIG_MISC=y -CONFIG_DM_MMC=y -CONFIG_MMC_HS200_SUPPORT=y -CONFIG_MMC_MESON_GX=y -CONFIG_MTD=y -CONFIG_AML_MTDPART=y -CONFIG_NAND=y -CONFIG_DM_SPI_FLASH=y -CONFIG_PHY=y -CONFIG_AML_USB3_PHY=y -CONFIG_AML_USB2_PHY=y -CONFIG_PINCTRL=y -CONFIG_PINCONF=y -CONFIG_PINCTRL_MESON_C2=y -CONFIG_DM_REGULATOR=y -CONFIG_DEBUG_UART_MESON=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_DEBUG_UART_SKIP_INIT=y -CONFIG_MESON_SERIAL=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_AML_SPIFCV2=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_AML_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e -CONFIG_WDT=y -CONFIG_WDT_MESON=y -CONFIG_AML_DRIVER=y -CONFIG_AML_MEDIA=y -CONFIG_EFUSE=y -CONFIG_SHA1=y -CONFIG_SHA256=y -CONFIG_OF_LIBFDT_OVERLAY=n -CONFIG_SECURE_POWER_CONTROL=y -CONFIG_AML_GPT=y -CONFIG_AML_REMOVE_BOOTLOADER_PARTITION=y -CONFIG_IMG_SECURE_CHECK_SZ=66060288 -CONFIG_CMD_FACTORY_BOOT=y -CONFIG_CMD_REBOOT=y -CONFIG_AML_RPMB_DISABLE=y -CONFIG_CMD_BOOTCTOL_AVB=y -CONFIG_G_AB_SYSTEM=y -CONFIG_LZ4=y -CONFIG_CMD_UNZIP=y -CONFIG_CMD_GET_CHIPTYPE=y -CONFIG_I2C_REGULATOR=n -CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY=y -CONFIG_SCHUMACHER_SSR=n -# CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_BOOTZ is not set -# CONFIG_CMD_BOOTI is not set -# CONFIG_CMD_MEMORY is not set -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_JTAG is not set -CONFIG_LOGLEVEL=7 -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=1 -CONFIG_CMD_SAVEENV=y -CONFIG_ENV_IS_IN_STORAGE=y
diff --git a/board/amlogic/defconfigs/c2_xua4_bx_defconfig b/board/amlogic/defconfigs/c2_xua4_bx_defconfig deleted file mode 100644 index ce5385b..0000000 --- a/board/amlogic/defconfigs/c2_xua4_bx_defconfig +++ /dev/null
@@ -1,114 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MESON=y -CONFIG_SYS_TEXT_BASE=0x00000000 -CONFIG_MESON_C2=y -# CONFIG_PXP_EMULATOR is not set -CONFIG_AML_TSENSOR=y -CONFIG_AML_TSENSOR_COOL=y -CONFIG_NEED_BL32=y -CONFIG_C2_XUA4_BX=y -CONFIG_DEBUG_UART_BASE=0xfe001c00 -CONFIG_DEBUG_UART_CLOCK=24000000 -CONFIG_DEBUG_UART=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTCOMMAND="run storeboot" -CONFIG_BOARD_LATE_INIT=y -# CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_SYS_PROMPT="c2_xua4_bx# " -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_IMI is not set -CONFIG_CMD_CLKMSR=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_MMC=y -CONFIG_CMD_MTD=y -CONFIG_AML_STORAGE=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_SARADC=y -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_MISC is not set -CONFIG_CMD_MTDPARTS=y -CONFIG_AML_STORAGE=y -CONFIG_CMD_RSVMEM=y -CONFIG_CMD_WATCHDOG=y -CONFIG_CMD_JTAG=y -CONFIG_AML_PARTITION=y -CONFIG_OF_CONTROL=y -CONFIG_OF_EMBED=y -CONFIG_DEFAULT_DEVICE_TREE="meson-c2-c325x-xua4" -# CONFIG_REGMAP is not set -CONFIG_ADC=y -CONFIG_SARADC_MESON=y -CONFIG_SARADC_MESON_C2=y -CONFIG_CLK=y -CONFIG_CLK_MESON=y -CONFIG_CLK_MESON_C2=y -CONFIG_USB_FUNCTION_FASTBOOT=n -CONFIG_DM_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_MESON=y -CONFIG_MISC=y -CONFIG_DM_MMC=y -CONFIG_MMC_HS200_SUPPORT=y -CONFIG_MMC_MESON_GX=y -CONFIG_MTD=y -CONFIG_AML_MTDPART=y -CONFIG_NAND=y -CONFIG_DM_SPI_FLASH=y -CONFIG_PHY=y -CONFIG_AML_USB3_PHY=y -CONFIG_AML_USB2_PHY=y -CONFIG_PINCTRL=y -CONFIG_PINCONF=y -CONFIG_PINCTRL_MESON_C2=y -CONFIG_DM_REGULATOR=y -CONFIG_DEBUG_UART_MESON=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_DEBUG_UART_SKIP_INIT=y -CONFIG_MESON_SERIAL=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_AML_SPIFCV2=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_AML_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e -CONFIG_WDT=y -CONFIG_WDT_MESON=y -CONFIG_AML_DRIVER=y -CONFIG_AML_MEDIA=y -CONFIG_EFUSE=y -CONFIG_SHA1=y -CONFIG_SHA256=y -CONFIG_OF_LIBFDT_OVERLAY=n -CONFIG_SECURE_POWER_CONTROL=y -CONFIG_AML_GPT=y -CONFIG_AML_REMOVE_BOOTLOADER_PARTITION=y -CONFIG_IMG_SECURE_CHECK_SZ=66060288 -CONFIG_CMD_FACTORY_BOOT=y -CONFIG_CMD_REBOOT=y -CONFIG_AML_RPMB_DISABLE=y -CONFIG_CMD_BOOTCTOL_AVB=y -CONFIG_G_AB_SYSTEM=y -CONFIG_LZ4=y -CONFIG_CMD_UNZIP=y -CONFIG_CMD_GET_CHIPTYPE=y -CONFIG_I2C_REGULATOR=n -CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY=y -CONFIG_SCHUMACHER_SSR=n -# CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_BOOTZ is not set -# CONFIG_CMD_BOOTI is not set -# CONFIG_CMD_MEMORY is not set -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_JTAG is not set -CONFIG_LOGLEVEL=7 -CONFIG_ENABLE_CHARGER_DETECTION=y
diff --git a/board/amlogic/defconfigs/c2_xua4_p1_defconfig b/board/amlogic/defconfigs/c2_xua4_p1_defconfig deleted file mode 100644 index a1931a4..0000000 --- a/board/amlogic/defconfigs/c2_xua4_p1_defconfig +++ /dev/null
@@ -1,114 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MESON=y -CONFIG_SYS_TEXT_BASE=0x00000000 -CONFIG_MESON_C2=y -# CONFIG_PXP_EMULATOR is not set -CONFIG_AML_TSENSOR=y -CONFIG_AML_TSENSOR_COOL=y -CONFIG_NEED_BL32=y -CONFIG_C2_XUA4_P1=y -CONFIG_DEBUG_UART_BASE=0xfe001c00 -CONFIG_DEBUG_UART_CLOCK=24000000 -CONFIG_DEBUG_UART=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTCOMMAND="run storeboot" -CONFIG_BOARD_LATE_INIT=y -# CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_SYS_PROMPT="c2_xua4_p1# " -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_IMI is not set -CONFIG_CMD_CLKMSR=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_MMC=y -CONFIG_CMD_MTD=y -CONFIG_AML_STORAGE=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_SARADC=y -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_MISC is not set -CONFIG_CMD_MTDPARTS=y -CONFIG_AML_STORAGE=y -CONFIG_CMD_RSVMEM=y -CONFIG_CMD_WATCHDOG=y -CONFIG_CMD_JTAG=y -CONFIG_AML_PARTITION=y -CONFIG_OF_CONTROL=y -CONFIG_OF_EMBED=y -CONFIG_DEFAULT_DEVICE_TREE="meson-c2-c325x-xua4" -# CONFIG_REGMAP is not set -CONFIG_ADC=y -CONFIG_SARADC_MESON=y -CONFIG_SARADC_MESON_C2=y -CONFIG_CLK=y -CONFIG_CLK_MESON=y -CONFIG_CLK_MESON_C2=y -CONFIG_USB_FUNCTION_FASTBOOT=n -CONFIG_DM_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_MESON=y -CONFIG_MISC=y -CONFIG_DM_MMC=y -CONFIG_MMC_HS200_SUPPORT=y -CONFIG_MMC_MESON_GX=y -CONFIG_MTD=y -CONFIG_AML_MTDPART=y -CONFIG_NAND=y -CONFIG_DM_SPI_FLASH=y -CONFIG_PHY=y -CONFIG_AML_USB3_PHY=y -CONFIG_AML_USB2_PHY=y -CONFIG_PINCTRL=y -CONFIG_PINCONF=y -CONFIG_PINCTRL_MESON_C2=y -CONFIG_DM_REGULATOR=y -CONFIG_DEBUG_UART_MESON=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_DEBUG_UART_SKIP_INIT=y -CONFIG_MESON_SERIAL=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_AML_SPIFCV2=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_AML_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e -CONFIG_WDT=y -CONFIG_WDT_MESON=y -CONFIG_AML_DRIVER=y -CONFIG_AML_MEDIA=y -CONFIG_EFUSE=y -CONFIG_SHA1=y -CONFIG_SHA256=y -CONFIG_OF_LIBFDT_OVERLAY=n -CONFIG_SECURE_POWER_CONTROL=y -CONFIG_AML_GPT=y -CONFIG_AML_REMOVE_BOOTLOADER_PARTITION=y -CONFIG_IMG_SECURE_CHECK_SZ=66060288 -CONFIG_CMD_FACTORY_BOOT=y -CONFIG_CMD_REBOOT=y -CONFIG_AML_RPMB_DISABLE=y -CONFIG_CMD_BOOTCTOL_AVB=y -CONFIG_G_AB_SYSTEM=y -CONFIG_LZ4=y -CONFIG_CMD_UNZIP=y -CONFIG_CMD_GET_CHIPTYPE=y -CONFIG_I2C_REGULATOR=n -CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY=y -CONFIG_SCHUMACHER_SSR=n -# CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_BOOTZ is not set -# CONFIG_CMD_BOOTI is not set -# CONFIG_CMD_MEMORY is not set -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_JTAG is not set -CONFIG_LOGLEVEL=7 -CONFIG_ENABLE_CHARGER_DETECTION=y
diff --git a/build_uboot.sh b/build_uboot.sh index da14fcb..c45434f 100755 --- a/build_uboot.sh +++ b/build_uboot.sh
@@ -1,9 +1,6 @@ #!/bin/bash exec_name=$0 -dbg_flag="debug" -zircon_cfg="" -prebuilt_path="" set -o errtrace trap 'echo Fatal error: script ${exec_name} aborting at line $LINENO, command \"$BASH_COMMAND\" returned $?; exit 1' ERR @@ -14,32 +11,10 @@ echo DIR:$DIR function usage(){ - echo "Usage: ${exec_name} <board> [workspace path] [-o (prebuilt path)]" + echo "Usage: ${exec_name} <board> [workspace path]" echo "supported boards: spencer-p1/p2/b1/b3/b4, venus-p1/p2, a049-p0, bsv3-p1" } -function update_prebuilt_path() { - has_bl2_bl3x=0 - if [ -d $DIR/../bl2 ] && [ -d $DIR/../bl31 ] && [ -d $DIR/../bl32 ]; then - has_bl2_bl3x=1 - fi - - if [ "$has_bl2_bl3x" == "0" ]; then - default_prebuilt_path=${workspace_path}/vendor/amlogic/${product}/prebuilt/bootloader/blx - if [ -d ${default_prebuilt_path} ]; then - prebuilt_path=${default_prebuilt_path} - echo "use prebuilt from ${prebuilt_path}" - fi - fi - - if [ -z "$prebuilt_path" ]; then - prebuilt_path=fip/${soc_family_name} - echo "unspecified prebuilt path, will use local prebuilt ${prebuilt_path}" - fi - - echo "current prebuilt path: ${prebuilt_path}" -} - function building_uboot(){ soc_family_name=$1 local_name=$2 @@ -48,24 +23,20 @@ cfg_suffix=$6 config=${local_name}_${rev}${cfg_suffix} - product=`echo ${board} | cut -d "-" -f1` echo "building u-boot for ${board}" - update_prebuilt_path - ./mk ${config} --board_name $board_name --bl2 ${prebuilt_path}/bl2.bin --bl30 ${prebuilt_path}/bl30.bin --bl31 ${prebuilt_path}/bl31.img --bl32 ${prebuilt_path}/bl32.img $5 + ./mk ${config} --board_name $board_name --bl2 fip/${soc_family_name}/bl2.bin --bl30 fip/${soc_family_name}/bl30.bin --bl31 fip/${soc_family_name}/bl31.img --bl32 fip/${soc_family_name}/bl32.img $5 # make T=1 to use latest git commit time as build timestamp. echo "mk done\n" + product=`echo ${board} | cut -d "-" -f1` if [ ! -z $workspace_path ]; then mkdir -p ${workspace_path}/vendor/amlogic/${product}/prebuilt/bootloader/ if [ "$product" == "spencer" ] || \ [ "$product" == "venus" ] || \ [ "$product" == "a049" ] || \ - [ "$product" == "bsv3" ] || \ - [ "$product" == "bla4" ] || \ - [ "$product" == "2rs4" ] || \ - [ "$product" == "xua4" ]; then + [ "$product" == "bsv3" ]; then # Copy bl2 and bl3x images for bootloader signing under eureka source. cp fip/build/bl2_new.bin \ ${workspace_path}/vendor/amlogic/${product}/prebuilt/bootloader/bl2_new.bin.${board} @@ -111,36 +82,15 @@ readonly cross_compile_t32=$DIR/../amlogic/linaro/gcc-arm-none-eabi-6-2017-q2-update/bin/arm-none-eabi- readonly vendor_amlogic=$DIR/../vendor/amlogic -shift -if [ -n "$workspace_path" ]; then - shift +dbg_flag="debug" +zircon_cfg="" + +if [ "$3" = "release" -o "$4" = "release" ]; then + dbg_flag="release" +elif [ "$4" = "zircon" -o "$5" = "zircon" ]; then + zircon_cfg="_zircon" fi -for arg in "$@" -do - case $arg in - -d) - shift - ;; - release) - dbg_flag="release" - shift - ;; - zircon) - zircon_cfg="_zircon" - shift - ;; - -o) - shift - if [ -n "$1" ]; then - prebuilt_path=$1 - shift - else - echo "Error: -o option requires an argument." - exit 1 - fi - ;; - esac -done + export ENABLE_UBOOT_UPDATE=1 export ENABLE_UBOOT_CLI=1 @@ -185,30 +135,6 @@ bsv3-p1) building_uboot c2 c2_bsv3 p1 $board $dbg_flag ;; - bla4-p0) - building_uboot c2 c2_bla4 p0 $board $dbg_flag - ;; - bla4-p1) - building_uboot c2 c2_bla4 p1 $board $dbg_flag - ;; - bla4-p2) - building_uboot c2 c2_bla4 p2 $board $dbg_flag - ;; - bla4-b1) - building_uboot c2 c2_bla4 bx $board $dbg_flag - ;; - 2rs4-p1) - building_uboot c2 c2_2rs4 p1 $board $dbg_flag - ;; - 2rs4-p2) - building_uboot c2 c2_2rs4 p2 $board $dbg_flag - ;; - xua4-p1) - building_uboot c2 c2_xua4 p1 $board $dbg_flag - ;; - xua4-b1) - building_uboot c2 c2_xua4 bx $board $dbg_flag - ;; *) echo "unknown board: $board" exit 1
diff --git a/common/Makefile b/common/Makefile index a27b419..c56ef68 100644 --- a/common/Makefile +++ b/common/Makefile
@@ -140,11 +140,5 @@ obj-$(CONFIG_AVB_VERIFY) += avb_verify.o obj-$(CONFIG_MDUMP_COMPRESS) += ramdump.o -ifeq ($(CONFIG_LED_AW2026), y) -obj-y += leds-aw2026.o -else ifeq ($(CONFIG_LED_AW210XX), y) -obj-y += leds-aw210xx.o -else obj-y += led.o -endif obj-${CONFIG_SCHUMACHER_SSR} += ssr.o
diff --git a/common/leds-aw2026.c b/common/leds-aw2026.c deleted file mode 100644 index d8e67f7..0000000 --- a/common/leds-aw2026.c +++ /dev/null
@@ -1,207 +0,0 @@ -#include <amlogic/leds-aw2026.h> -#include <dm.h> - -#define CAL_FILENAME "led_calibration_LUT.txt" -#define AW2026_MAX_CURRENT AW2026_LED_3_1875mA - -// Copied from -// https://eureka-partner-review.googlesource.com/c/amlogic/u-boot/+/149113 -// Reads "led_calibration_LUT.txt" from the factory partition. -// Forwards errors, returns 0 on success. -int get_cal_string(char *buf, int len) -{ - int ret; - loff_t len_read; - const loff_t seek = 21; - - ret = fs_set_blk_dev("mmc", "1:4", FS_TYPE_EXT); - if (ret) { - pr_err("LED: fs_set_blk_dev error=%d\n", ret); - return ret; - } - // Leave space for terminator - ret = fs_read(CAL_FILENAME, buf, seek, len - 1, - &len_read); - if (ret) { - pr_err("LED: fs_read error=%d\n", ret); - return ret; - } - // fs_read does not add a null terminator - buf[len_read] = '\0'; - - return 0; -} - -// Copied from -// https://eureka-partner-review.googlesource.com/c/amlogic/u-boot/+/149113 -// Gets calibration settings for the status LED: -// pwm_r, pwm_g, pwm_b, current_r, current_g, current_b -// On failure, |settings| is not modified. -void get_cal_settings(unsigned int *settings, const char color_header[]) -{ - int i; - unsigned long settings_[N_CAL_SETTINGS]; - - // Max length to cover all color lines - // 9 colors * (color_name + ":4095:" + xxx[,|;|\n] * 6) - // 9 * (14 + 6 + 4 * 6 ) - const unsigned int max_chars = 396; - // Add one for null terminator - char buf[max_chars]; - - if (get_cal_string(&buf, max_chars)) - return; - - const char *p, *p_next; - - p = strstr(buf, color_header); - if (!p) { - pr_err("LED: \"%s\" not found in cal file segment: %s\n", - color_header, buf); - return; - } - p += strlen(color_header); - - for (i = 0; i < N_CAL_SETTINGS; ++i) { - unsigned long value = simple_strtoul(p, &p_next, 10); - - if (value > 255) { - pr_err("LED: value %d is too large: %lu\n", - settings_[i]); - return; - } - settings_[i] = value; - - // Skip check that |p_next| is valid on last iteration - if (i == 5) - break; - // Is there not a separator, or not another number - if ((*p_next != ',' && *p_next != ';') || - !isdigit(p_next[1])) { - // Is this the first current - if (i == 3) { - // One current instead of RGB current - settings_[4] = value; - settings_[5] = value; - break; - } - // Invalid - pr_err("LED calibration file is malformed\n"); - return; - } - - p = p_next + 1; - } - - for (i = 0; i < N_CAL_SETTINGS; ++i) - settings[i] = (unsigned int)settings_[i]; -} - -void reg_write(struct udevice *led_devp, int reg, int mask, int val) { - int old_val; - int new_val; - - old_val = dm_i2c_reg_read(led_devp, reg); - if (old_val < 0) { - pr_err("LED: read %d reg failed\n", reg); - return; - } - new_val = (old_val & ~mask) | (val & mask); - dm_i2c_reg_write(led_devp, reg, new_val); -} - -void sys_led_init(enum LED_ANIMATION led_animation) -{ -#ifdef CONFIG_SYS_I2C_MESON - int ret; - struct udevice *led_devp = NULL; - ret = i2c_get_chip_for_busnum(I2C_BUS_NUM, I2C_LED_REG, 1, &led_devp); - if (ret) { - pr_err("LED: i2c get bus fail\n"); - return; - } - - reg_write(led_devp, AW2026_REG_RSTIDR, AW2026_LED_RSTIDR_MASK, - AW2026_LED_RSTIDR_RESET); - reg_write(led_devp, AW2026_REG_GCR, AW2026_LED_CHIPEN_MASK, - AW2026_LED_CHIP_ENABLE); - reg_write(led_devp, AW2026_REG_IMAX, AW2026_LED_IMX_MASK, - AW2026_MAX_CURRENT); - reg_write(led_devp, AW2026_REG_LEDCTR, AW2026_LED_PWMLOG_MASK, - AW2026_LED_PWMLOG_LEANER); - reg_write(led_devp, AW2026_REG_LEDEN, AW2026_LED_LEDEN_MASK, - AW2026_LED_LEDEN_TURN_ON_ALL); - - switch(led_animation) { - case WHITE: - turn_on_white_led(led_devp); - break; - case YELLOW: - turn_on_yellow_led(led_devp); - break; - case BLINK_YELLOW: - blink_yellow_led(led_devp); - break; - default: - pr_err("LED: unknown led animation\n"); - } -#endif // CONFIG_SYS_I2C_MESON -} - -void turn_on_white_led(struct udevice *led_devp) { - unsigned int cal_settings[N_CAL_SETTINGS] = - {128, 0, 128, 100, 100, 100}; - int i; - get_cal_settings(&cal_settings, "white:0:"); - for(i = 0; i < 3; ++i) { - reg_write(led_devp, AW2026_REG_LCFG1 + i, AW2026_LED_LEDMD_MASK, - AW2026_LED_ON_MODE); - reg_write(led_devp, AW2026_REG_PWM1 + i, AW2026_LED_PWM_MASK, - cal_settings[i]); - reg_write(led_devp, AW2026_REG_ILED1 + i, AW2026_LED_ILED_MASK, - cal_settings[3+i]); - } -} - -void turn_on_yellow_led(struct udevice *led_devp) { - unsigned int cal_settings[N_CAL_SETTINGS] = - {255, 255, 255, 0xff, 0xef, 0}; - int i; - get_cal_settings(&cal_settings, "amber:0:"); - for(i = 0; i < 3; ++i) { - reg_write(led_devp, AW2026_REG_LCFG1 + i, AW2026_LED_LEDMD_MASK, - AW2026_LED_ON_MODE); - reg_write(led_devp, AW2026_REG_PWM1 + i, AW2026_LED_PWM_MASK, - cal_settings[i]); - reg_write(led_devp, AW2026_REG_ILED1 + i, AW2026_LED_ILED_MASK, - cal_settings[3+i]); - } -} - -void blink_yellow_led(struct udevice *led_devp) { - int i; - int val; - - turn_on_yellow_led(led_devp); - - for(i = 0; i < 3; ++i) { - reg_write(led_devp, AW2026_REG_PAT1_T1 + i * PAT_FIELD_NUMBER, - AW2026_LED_PAT_TRISE_MASK, 0x0); - reg_write(led_devp, AW2026_REG_PAT1_T2 + i * PAT_FIELD_NUMBER, - AW2026_LED_PAT_TFALL_MASK, 0x0); - reg_write(led_devp, AW2026_REG_PAT1_T1 + i * PAT_FIELD_NUMBER, - AW2026_LED_PAT_TON_MASK, - AW2026_LED_PAT_ON_1SEC); - reg_write(led_devp, AW2026_REG_PAT1_T2 + i * PAT_FIELD_NUMBER, - AW2026_LED_PAT_TOFF_MASK, - AW2026_LED_PAT_OFF_1SEC); - reg_write(led_devp, AW2026_REG_PAT1_T4 + i * PAT_FIELD_NUMBER, - AW2026_LED_PAT_CTR_MASK, - AW2026_LED_PAT_CTR_INF_LOOP); - reg_write(led_devp, AW2026_REG_LCFG1 + i, - AW2026_LED_LEDMD_MASK, - AW2026_LED_BLINK_MODE); - } - reg_write(led_devp, AW2026_REG_PATRUN, AW2026_LED_PATRUN_MASK, - AW2026_LED_PATRUN_START_ALL); -}
diff --git a/common/leds-aw210xx.c b/common/leds-aw210xx.c deleted file mode 100644 index b51dd1e..0000000 --- a/common/leds-aw210xx.c +++ /dev/null
@@ -1,248 +0,0 @@ -#include <amlogic/leds-aw210xx.h> -#include <dm.h> - -#define CAL_FILENAME "led_calibration_LUT.txt" - -// Copied from -// https://eureka-partner-review.googlesource.com/c/amlogic/u-boot/+/149113 -// Reads "led_calibration_LUT.txt" from the factory partition. -// Forwards errors, returns 0 on success. -int get_cal_string(char *buf, int len) -{ - int ret; - loff_t len_read; - const loff_t seek = 21; - - ret = fs_set_blk_dev("mmc", "1:4", FS_TYPE_EXT); - if (ret) { - pr_err("LED: fs_set_blk_dev error=%d\n", ret); - return ret; - } - // Leave space for terminator - ret = fs_read(CAL_FILENAME, buf, seek, len - 1, - &len_read); - if (ret) { - pr_err("LED: fs_read error=%d\n", ret); - return ret; - } - // fs_read does not add a null terminator - buf[len_read] = '\0'; - - return 0; -} - -// Copied from -// https://eureka-partner-review.googlesource.com/c/amlogic/u-boot/+/149113 -// Gets calibration settings for the status LED: -// pwm_r, pwm_g, pwm_b, current_r, current_g, current_b -// On failure, |settings| is not modified. -void get_cal_settings(unsigned int *settings, const char color_header[]) -{ - int i; - unsigned long settings_[N_CAL_SETTINGS]; - - // Max length to cover all color lines - // 9 colors * (color_name + ":4095:" + xxx[,|;|\n] * 6) - // 9 * (14 + 6 + 4 * 6 ) - const unsigned int max_chars = 396; - // Add one for null terminator - char buf[max_chars]; - - if (get_cal_string(&buf, max_chars)) - return; - - const char *p, *p_next; - - p = strstr(buf, color_header); - if (!p) { - pr_err("LED: \"%s\" not found in cal file segment: %s\n", - color_header, buf); - return; - } - p += strlen(color_header); - - for (i = 0; i < N_CAL_SETTINGS; ++i) { - unsigned long value = simple_strtoul(p, &p_next, 10); - - if (value > 255) { - pr_err("LED: value %d is too large: %lu\n", - settings_[i]); - return; - } - settings_[i] = value; - - // Skip check that |p_next| is valid on last iteration - if (i == 5) - break; - // Is there not a separator, or not another number - if ((*p_next != ',' && *p_next != ';') || - !isdigit(p_next[1])) { - // Is this the first current - if (i == 3) { - // One current instead of RGB current - settings_[4] = value; - settings_[5] = value; - break; - } - // Invalid - pr_err("LED calibration file is malformed\n"); - return; - } - - p = p_next + 1; - } - - for (i = 0; i < N_CAL_SETTINGS; ++i) - settings[i] = (unsigned int)settings_[i]; -} - -void reg_write(struct udevice *led_devp, int reg, int mask, int val) { - int old_val; - int new_val; - - old_val = dm_i2c_reg_read(led_devp, reg); - if (old_val < 0) { - pr_err("LED: read %d reg failed\n", reg); - return; - } - new_val = (old_val & ~mask) | (val & mask); - dm_i2c_reg_write(led_devp, reg, new_val); -} - -void sys_led_init(enum LED_ANIMATION led_animation) -{ -#ifdef CONFIG_SYS_I2C_MESON - int ret; - struct udevice *led_devp = NULL; - ret = i2c_get_chip_for_busnum(I2C_BUS_NUM, I2C_LED_REG, 1, &led_devp); - if (ret) { - pr_err("LED: i2c get bus fail\n"); - return; - } - - reg_write(led_devp, AW210XX_REG_RESET, AW210XX_RESET_MASK, - AW210XX_RESET_CHIP); - reg_write(led_devp, AW210XX_REG_GCR, AW210XX_BIT_CHIPEN_MASK, - AW210XX_BIT_CHIPEN_ENABLE); - reg_write(led_devp, AW210XX_REG_GCR, AW210XX_BIT_APSE_MASK, - AW210XX_BIT_APSE_ENABLE); - reg_write(led_devp, AW210XX_REG_GCCR, AW210XX_GLOBAL_CURRENT_MASK, - AW210xx_MAX_CURRENT); - reg_write(led_devp, AW210XX_REG_PHCR, AW210XX_PDE_MASK, - AW210XX_PDE_ENABLE); - - switch(led_animation) { - case WHITE: - turn_on_white_led(led_devp); - break; - case YELLOW: - turn_on_yellow_led(led_devp); - break; - case BLINK_YELLOW: - blink_yellow_led(led_devp); - break; - default: - pr_err("LED: unknown led animation\n"); - } -#endif // CONFIG_SYS_I2C_MESON -} - -void turn_on_white_led(struct udevice *led_devp) { - unsigned int cal_settings[N_CAL_SETTINGS] = - {128, 0, 128, 100, 100, 100}; - int i; - get_cal_settings(&cal_settings, "white:255:"); - // HW design: LED7 is blue, LED8 is red, LED9 is green - // Calibration file is: R,G,B - for(i = 0; i < 3; ++i) { - if (i == 2) { - // blue led - reg_write(led_devp, AW210XX_REG_SL06, AW210XX_SLXX_MASK, - cal_settings[3+i]); - reg_write(led_devp, AW210XX_REG_BR06L, - AW210XX_BRXX_MASK, cal_settings[i]); - } { - // red led and green led - reg_write(led_devp, AW210XX_REG_SL07 + i, - AW210XX_SLXX_MASK, cal_settings[3+i]); - reg_write(led_devp, AW210XX_REG_BR07L + i*2, - AW210XX_BRXX_MASK, cal_settings[i]); - } - } - reg_write(led_devp, AW210XX_REG_UPDATE, AW210XX_UPDATE_MASK, - AW210XX_UPDATE_ENABLE); -} - -void turn_on_yellow_led(struct udevice *led_devp) { - unsigned int cal_settings[N_CAL_SETTINGS] = - {255, 255, 255, 0xff, 0xef, 0}; - int i; - - get_cal_settings(&cal_settings, "amber:255:"); - // HW design: LED7 is blue, LED8 is red, LED9 is green - // Calibration file is: R,G,B - for(i = 0; i < 3; ++i) { - if (i == 2) { - // blue led - reg_write(led_devp, AW210XX_REG_SL06, AW210XX_SLXX_MASK, - cal_settings[3+i]); - reg_write(led_devp, AW210XX_REG_BR06L, - AW210XX_BRXX_MASK, cal_settings[i]); - } else { - // red led and green led - reg_write(led_devp, AW210XX_REG_SL07 + i, - AW210XX_SLXX_MASK, cal_settings[3+i]); - reg_write(led_devp, AW210XX_REG_BR07L + i*2, - AW210XX_BRXX_MASK, cal_settings[i]); - } - } - reg_write(led_devp, AW210XX_REG_UPDATE, AW210XX_UPDATE_MASK, - AW210XX_UPDATE_ENABLE); -} - -void blink_yellow_led(struct udevice *led_devp) { - unsigned int cal_settings[N_CAL_SETTINGS] = - {255, 255, 255, 0xff, 0xef, 0}; - int i; - - reg_write(led_devp, AW210XX_REG_GCFG, AW210XX_GE_MASK, - AW210XX_GE2_SET); - reg_write(led_devp, AW210XX_REG_ABMCFG, AW210XX_PATCFG_MASK, - AW210XX_PATE_ENABLE | AW210XX_PATMD_AUTO); - reg_write(led_devp, AW210XX_REG_ABMT0, AW210XX_PAT_RISE_MASK, - AW210XX_PAT_RISE_TIME); - reg_write(led_devp, AW210XX_REG_ABMT1, AW210XX_PAT_FALL_MASK, - AW210XX_PAT_FALL_TIME); - reg_write(led_devp, AW210XX_REG_ABMT0, AW210XX_PAT_ON_MASK, - AW210XX_PAT_ON_TIME); - reg_write(led_devp, AW210XX_REG_ABMT1, AW210XX_PAT_OFF_MASK, - AW210XX_PAT_OFF_TIME); - - get_cal_settings(&cal_settings, "amber:255:"); - // HW design: LED7 is blue, LED8 is red, LED9 is green - // datasheet: in group mode - // GSLR: for ledx(x=1,4,7) - // GSLG: for ledx(x=2,5,8) - // GSLB: for ledx(x=3,6,9) - for(i = 0; i < 3; ++i) { - if (i == 2) { - // blue led - reg_write(led_devp, AW210XX_REG_GSLR, AW210XX_SLXX_MASK, - cal_settings[3+i]); - } else { - // red led and green led - reg_write(led_devp, AW210XX_REG_GSLG + i, - AW210XX_SLXX_MASK, cal_settings[3+i]); - } - } - - // set brightness range - reg_write(led_devp, AW210XX_REG_GBRH, AW210XX_BRXX_MASK, - AW210xx_MAX_BRIGHTNESS); - reg_write(led_devp, AW210XX_REG_GBRL, AW210XX_BRXX_MASK, - AW210xx_MIN_BRIGHTNESS); - - // start run - reg_write(led_devp, AW210XX_REG_ABMGO, AW210XX_PAT_RUN_MASK, - AW210XX_PAT_RUN); -}
diff --git a/drivers/fastboot/fb_command.c b/drivers/fastboot/fb_command.c index ad55a7c..0037cc8 100644 --- a/drivers/fastboot/fb_command.c +++ b/drivers/fastboot/fb_command.c
@@ -724,7 +724,7 @@ sprintf(lock_d, "%d%d%d0%d%d%d0", info->version_major, info->version_minor, info->unlock_ability, info->lock_state, info->lock_critical_state, info->lock_bootloader); printf("lock_d state: %s\n", lock_d); env_set("lock", lock_d); - run_command("saveenv;", 0); + run_command("defenv_reserv; saveenv;", 0); free(info); return; }
diff --git a/drivers/fastboot/fb_mmc.c b/drivers/fastboot/fb_mmc.c index 7f085d9..8847fa5 100644 --- a/drivers/fastboot/fb_mmc.c +++ b/drivers/fastboot/fb_mmc.c
@@ -140,7 +140,6 @@ * * @return Boot image header sectors count or 0 on error */ -typedef struct andr_img_hdr boot_img_hdr_t; static lbaint_t fb_mmc_get_boot_header(struct blk_desc *dev_desc, disk_partition_t *info, boot_img_hdr_t *hdr,
diff --git a/drivers/mmc/aml_emmc_partition.c b/drivers/mmc/aml_emmc_partition.c index c6ca618..96faadb 100755 --- a/drivers/mmc/aml_emmc_partition.c +++ b/drivers/mmc/aml_emmc_partition.c
@@ -32,12 +32,7 @@ #endif /* debug info*/ #define CONFIG_MPT_DEBUG (0) - -#ifdef AML_ENABLE_PRODUCTION_MODE #define GPT_PRIORITY (1) -#else -#define GPT_PRIORITY (0) -#endif #ifdef CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY #define FALSE 0
diff --git a/fip/c2/aml_ddr.fw b/fip/c2/aml_ddr.fw index 32b9d3c..826c0c5 100644 --- a/fip/c2/aml_ddr.fw +++ b/fip/c2/aml_ddr.fw Binary files differ
diff --git a/fip/c2/bl2.bin b/fip/c2/bl2.bin deleted file mode 100755 index 91bf131..0000000 --- a/fip/c2/bl2.bin +++ /dev/null Binary files differ
diff --git a/fip/c2/bl31.img b/fip/c2/bl31.img deleted file mode 100644 index 1c42a7c..0000000 --- a/fip/c2/bl31.img +++ /dev/null Binary files differ
diff --git a/fip/c2/bl32.img b/fip/c2/bl32.img deleted file mode 100644 index 467e425..0000000 --- a/fip/c2/bl32.img +++ /dev/null Binary files differ
diff --git a/include/amlogic/leds-aw2026.h b/include/amlogic/leds-aw2026.h deleted file mode 100644 index a79a005..0000000 --- a/include/amlogic/leds-aw2026.h +++ /dev/null
@@ -1,75 +0,0 @@ -#ifndef LEDS_AW2026_H_ -#define LEDS_AW2026_H_ - -#include <common.h> - -#ifdef CONFIG_SYS_I2C_MESON -#include <i2c.h> -#include <dt-bindings/i2c/meson-i2c.h> -#include <fs.h> -#endif - -#define N_CAL_SETTINGS 6 -#define I2C_BUS_NUM 3 -#define I2C_LED_REG 0x64 -#define PAT_FIELD_NUMBER 5 - -#define AW2026_REG_RSTIDR 0x00 -#define AW2026_REG_GCR 0x01 -#define AW2026_REG_IMAX 0x03 -#define AW2026_REG_LCFG1 0x04 -#define AW2026_REG_LEDEN 0x07 -#define AW2026_REG_LEDCTR 0x08 -#define AW2026_REG_PATRUN 0x09 -#define AW2026_REG_ILED1 0x10 -#define AW2026_REG_PWM1 0x1C -#define AW2026_REG_PAT1_T1 0x30 -#define AW2026_REG_PAT1_T2 0x31 -#define AW2026_REG_PAT1_T4 0x33 - -#define AW2026_LED_RSTIDR_MASK 0xff -#define AW2026_LED_RSTIDR_RESET 0x55 - -#define AW2026_LED_LEDMD_MASK 0b1 -#define AW2026_LED_ON_MODE 0x00 -#define AW2026_LED_BLINK_MODE 0x01 - -#define AW2026_LED_CHIPEN_MASK 0b1 -#define AW2026_LED_CHIP_ENABLE 0x01 - -#define AW2026_LED_IMX_MASK 0b11 -#define AW2026_LED_3_1875mA 0x00 -#define AW2026_LED_6_375mA 0x01 -#define AW2026_LED_12_75mA 0x02 -#define AW2026_LED_25_5mA 0x03 - -#define AW2026_LED_PWMLOG_MASK 0b11 -#define AW2026_LED_PWMLOG_LEANER 0b11 - -#define AW2026_LED_LEDEN_MASK 0b111 -#define AW2026_LED_LEDEN_TURN_ON_ALL 0b111 - -#define AW2026_LED_PWM_MASK 0xff - -#define AW2026_LED_ILED_MASK 0xff - -#define AW2026_LED_PAT_TRISE_MASK 0xf0 - -#define AW2026_LED_PAT_TFALL_MASK 0xf0 - -#define AW2026_LED_PAT_TON_MASK 0x0f -#define AW2026_LED_PAT_ON_1SEC 0b0110 - -#define AW2026_LED_PAT_TOFF_MASK 0x0f -#define AW2026_LED_PAT_OFF_1SEC 0b0110 - -#define AW2026_LED_PAT_CTR_MASK 0x80 -#define AW2026_LED_PAT_CTR_INF_LOOP 0x0 - -#define AW2026_LED_PATRUN_MASK 0b111 -#define AW2026_LED_PATRUN_START_ALL 0b111 - -enum LED_ANIMATION { WHITE, YELLOW, BLINK_YELLOW }; -void sys_led_init(enum LED_ANIMATION led_animation); - -#endif // LEDS_AW2026_H_
diff --git a/include/amlogic/leds-aw210xx.h b/include/amlogic/leds-aw210xx.h deleted file mode 100644 index be33ccb..0000000 --- a/include/amlogic/leds-aw210xx.h +++ /dev/null
@@ -1,158 +0,0 @@ -#ifndef LEDS_AW2026_H_ -#define LEDS_AW2026_H_ - -#include <common.h> - -#ifdef CONFIG_SYS_I2C_MESON -#include <i2c.h> -#include <dt-bindings/i2c/meson-i2c.h> -#include <fs.h> -#endif - -#define N_CAL_SETTINGS 6 -#define I2C_BUS_NUM 4 -#define I2C_LED_REG 0x20 - -/***************************************************** -* register about led mode -*****************************************************/ -#define AW210XX_REG_GCR (0x20) -#define AW210XX_REG_BR00L (0x21) -#define AW210XX_REG_BR00H (0x22) -#define AW210XX_REG_BR01L (0x23) -#define AW210XX_REG_BR01H (0x24) -#define AW210XX_REG_BR02L (0x25) -#define AW210XX_REG_BR02H (0x26) -#define AW210XX_REG_BR03L (0x27) -#define AW210XX_REG_BR03H (0x28) -#define AW210XX_REG_BR04L (0x29) -#define AW210XX_REG_BR04H (0x2A) -#define AW210XX_REG_BR05L (0x2B) -#define AW210XX_REG_BR05H (0x2C) -#define AW210XX_REG_BR06L (0x2D) -#define AW210XX_REG_BR06H (0x2E) -#define AW210XX_REG_BR07L (0x2F) -#define AW210XX_REG_BR07H (0x30) -#define AW210XX_REG_BR08L (0x31) -#define AW210XX_REG_BR08H (0x32) -#define AW210XX_REG_BR09L (0x33) -#define AW210XX_REG_BR09H (0x34) -#define AW210XX_REG_BR10L (0x35) -#define AW210XX_REG_BR10H (0x36) -#define AW210XX_REG_BR11L (0x37) -#define AW210XX_REG_BR11H (0x38) -#define AW210XX_REG_BR12L (0x39) -#define AW210XX_REG_BR12H (0x3A) -#define AW210XX_REG_BR13L (0x3B) -#define AW210XX_REG_BR13H (0x3C) -#define AW210XX_REG_BR14L (0x3D) -#define AW210XX_REG_BR14H (0x3E) -#define AW210XX_REG_BR15L (0x3F) -#define AW210XX_REG_BR15H (0x40) -#define AW210XX_REG_BR16L (0x41) -#define AW210XX_REG_BR16H (0x42) -#define AW210XX_REG_BR17L (0x43) -#define AW210XX_REG_BR17H (0x44) -#define AW210XX_REG_UPDATE (0x45) -#define AW210XX_REG_SL00 (0x46) -#define AW210XX_REG_SL01 (0x47) -#define AW210XX_REG_SL02 (0x48) -#define AW210XX_REG_SL03 (0x49) -#define AW210XX_REG_SL04 (0x4A) -#define AW210XX_REG_SL05 (0x4B) -#define AW210XX_REG_SL06 (0x4C) -#define AW210XX_REG_SL07 (0x4D) -#define AW210XX_REG_SL09 (0x4F) -#define AW210XX_REG_SL10 (0x50) -#define AW210XX_REG_SL11 (0x51) -#define AW210XX_REG_SL12 (0x52) -#define AW210XX_REG_SL13 (0x53) -#define AW210XX_REG_SL14 (0x54) -#define AW210XX_REG_SL15 (0x55) -#define AW210XX_REG_SL16 (0x56) -#define AW210XX_REG_SL17 (0x57) -#define AW210XX_REG_GCCR (0x58) -#define AW210XX_REG_PHCR (0x59) -#define AW210XX_REG_OSDCR (0x5A) -#define AW210XX_REG_OSST0 (0x5B) -#define AW210XX_REG_OSST1 (0x5C) -#define AW210XX_REG_OSST2 (0x5D) -#define AW210XX_REG_OTCR (0x5E) -#define AW210XX_REG_SSCR (0x5F) -#define AW210XX_REG_UVCR (0x60) -#define AW210XX_REG_GCR2 (0x61) -#define AW210XX_REG_GCR3 (0x62) -#define AW210XX_REG_RESET (0x70) -#define AW210XX_REG_ABMCFG (0x80) -#define AW210XX_REG_ABMGO (0x81) -#define AW210XX_REG_ABMT0 (0x82) -#define AW210XX_REG_ABMT1 (0x83) -#define AW210XX_REG_ABMT2 (0x84) -#define AW210XX_REG_ABMT3 (0x85) -#define AW210XX_REG_GBRH (0x86) -#define AW210XX_REG_GBRL (0x87) -#define AW210XX_REG_GSLR (0x88) -#define AW210XX_REG_GSLG (0x89) -#define AW210XX_REG_GSLB (0x8A) -#define AW210XX_REG_GCFG (0x8B) - -/***************************************************** - * define register Detail -*****************************************************/ -#define AW210XX_BIT_APSE_MASK (1 << 7) -#define AW210XX_BIT_APSE_ENABLE (1 << 7) -#define AW210XX_BIT_APSE_DISENA (0 << 7) -#define AW210XX_BIT_CHIPEN_MASK (1 << 0) -#define AW210XX_BIT_CHIPEN_ENABLE (1 << 0) -#define AW210XX_BIT_CHIPEN_DISENA (0 << 0) - -#define AW210XX_UPDATE_ENABLE (0x0) -#define AW210XX_UPDATE_MASK (0xff) -#define AW210XX_PDE_ENABLE (1 << 7) -#define AW210XX_PDE_MASK (1 << 7) -#define AW210XX_GE2_SET (1 << 2) -#define AW210XX_GE_MASK (0x7) -#define AW210XX_PATE_ENABLE (1 << 0) -#define AW210XX_PATMD_AUTO (1 << 1) -#define AW210XX_PATCFG_MASK (0x3) -#define AW210XX_PAT_RISE_TIME (0x0) -#define AW210XX_PAT_RISE_MASK (0xf << 4) -#define AW210XX_PAT_ON_TIME (0x6) -#define AW210XX_PAT_ON_MASK (0xf) -#define AW210XX_PAT_FALL_TIME (0x0) -#define AW210XX_PAT_FALL_MASK (0xf << 4) -#define AW210XX_PAT_OFF_TIME (0x6) -#define AW210XX_PAT_OFF_MASK (0xf) -#define AW210XX_PAT_RUN (0x1) -#define AW210XX_PAT_RUN_MASK (0x1) - - -#define AW210XX_RESET_MASK 0xff -#define AW210XX_GLOBAL_CURRENT_MASK 0xff -#define AW210XX_SLXX_MASK 0xff -#define AW210XX_BRXX_MASK 0xff - -/***************************************************** - * define register data -*****************************************************/ -#define AW210XX_RESET_CHIP (0x00) -#define AW210XX_UPDATE_BR_SL (0x00) -#define AW210XX_GROUP_ENABLE (0x38) -#define AW210XX_GROUP_DISABLE (0x40) -#define AW210XX_GLOBAL_DEFAULT_SET (0x66) -#define AW210XX_GBRH_DEFAULT_SET (0x60) -#define AW210XX_GBRL_DEFAULT_SET (0x00) -#define AW210XX_ABMT0_SET (0x99) -#define AW210XX_ABMT1_SET (0x99) -#define AW210XX_ABMT2_SET (0x00) -#define AW210XX_ABMT3_SET (0x00) -#define AW210XX_ABMCFG_SET (0x03) -#define AW210XX_ABMGO_SET (0x01) -#define AW210xx_MAX_CURRENT (0xff) -#define AW210xx_MAX_BRIGHTNESS (0xff) -#define AW210xx_MIN_BRIGHTNESS (0x0) - -enum LED_ANIMATION { WHITE, YELLOW, BLINK_YELLOW }; -void sys_led_init(enum LED_ANIMATION led_animation); - -#endif // LEDS_AW2026_H_