| // SPDX-License-Identifier: GPL-2.0+ |
| /* |
| * Copyright 2017-2018 NXP |
| */ |
| |
| /dts-v1/; |
| |
| #include "fsl-imx8qxp.dtsi" |
| |
| / { |
| model = "Freescale i.MX8QXP MEK"; |
| compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; |
| |
| chosen { |
| bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; |
| stdout-path = &lpuart0; |
| }; |
| |
| reg_usdhc2_vmmc: regulator-usdhc2-vmmc { |
| compatible = "regulator-fixed"; |
| regulator-name = "SD1_SPWR"; |
| regulator-min-microvolt = <3000000>; |
| regulator-max-microvolt = <3000000>; |
| gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>; |
| off-on-delay = <3480>; |
| enable-active-high; |
| }; |
| }; |
| |
| &iomuxc { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_hog>; |
| |
| imx8qxp-mek { |
| pinctrl_hog: hoggrp { |
| fsl,pins = < |
| SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0x0600004c |
| SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 |
| >; |
| }; |
| |
| pinctrl_ioexp_rst: ioexp-rst-grp { |
| fsl,pins = < |
| SC_P_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021 |
| >; |
| }; |
| |
| pinctrl_fec1: fec1grp { |
| fsl,pins = < |
| SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000048 |
| SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000048 |
| SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000048 |
| SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000048 |
| SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000048 |
| SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000048 |
| SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000048 |
| SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000048 |
| SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000048 |
| SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000048 |
| SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000048 |
| SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000048 |
| SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000048 |
| SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000048 |
| >; |
| }; |
| |
| pinctrl_fec2: fec2grp { |
| fsl,pins = < |
| SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x06000048 |
| SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x06000048 |
| SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x06000048 |
| SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x06000048 |
| SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x06000048 |
| SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x06000048 |
| SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x06000048 |
| SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x06000048 |
| SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x06000048 |
| SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x06000048 |
| SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x06000048 |
| SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x06000048 |
| >; |
| }; |
| |
| pinctrl_lpi2c1: lpi2c1grp { |
| fsl,pins = < |
| SC_P_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021 |
| SC_P_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 |
| >; |
| }; |
| |
| pinctrl_lpuart0: lpuart0grp { |
| fsl,pins = < |
| SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 |
| SC_P_UART0_TX_ADMA_UART0_TX 0x06000020 |
| >; |
| }; |
| |
| pinctrl_usdhc1: usdhc1grp { |
| fsl,pins = < |
| SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 |
| SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 |
| SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 |
| SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 |
| SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 |
| SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 |
| SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 |
| SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 |
| SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 |
| SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 |
| SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 |
| >; |
| }; |
| |
| pinctrl_usdhc2_gpio: usdhc2gpiogrp { |
| fsl,pins = < |
| SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000021 |
| SC_P_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021 |
| SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021 |
| >; |
| }; |
| |
| pinctrl_usdhc2: usdhc2grp { |
| fsl,pins = < |
| SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 |
| SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 |
| SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 |
| SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 |
| SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 |
| SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 |
| SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 |
| >; |
| }; |
| }; |
| }; |
| |
| &A35_0 { |
| u-boot,dm-pre-reloc; |
| }; |
| |
| &lpuart0 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_lpuart0>; |
| status = "okay"; |
| }; |
| |
| &i2c1 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>; |
| status = "okay"; |
| |
| i2cswitch@71 { |
| compatible = "nxp,pca9646"; |
| reg = <0x71>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; |
| |
| bb_i2c1: i2c@0 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0>; |
| }; |
| |
| mfi_i2c1: i2c@1 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x1>; |
| }; |
| |
| i2cexp1_i2c1: i2c@2 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x2>; |
| }; |
| |
| i2cexp2_i2c1: i2c@3 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x3>; |
| |
| pca9557_a: gpio@1a { |
| compatible = "nxp,pca9557"; |
| reg = <0x1a>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| pca9557_b: gpio@1d { |
| compatible = "nxp,pca9557"; |
| reg = <0x1d>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| }; |
| }; |
| }; |
| |
| &usdhc1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usdhc1>; |
| bus-width = <8>; |
| non-removable; |
| status = "okay"; |
| }; |
| |
| &usdhc2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; |
| bus-width = <4>; |
| cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; |
| wp-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; |
| vmmc-supply = <®_usdhc2_vmmc>; |
| status = "okay"; |
| }; |
| |
| &fec1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_fec1>; |
| phy-mode = "rgmii"; |
| phy-handle = <ðphy0>; |
| fsl,ar8031-phy-fixup; |
| fsl,magic-packet; |
| status = "okay"; |
| phy-reset-gpios = <&pca9557_a 4 GPIO_ACTIVE_LOW>; |
| phy-reset-duration = <10>; |
| |
| mdio { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ethphy0: ethernet-phy@0 { |
| compatible = "ethernet-phy-ieee802.3-c22"; |
| reg = <0>; |
| }; |
| ethphy1: ethernet-phy@1 { |
| compatible = "ethernet-phy-ieee802.3-c22"; |
| reg = <1>; |
| }; |
| }; |
| }; |
