| /* |
| * Copyright (c) 2016 Endless Computers, Inc. |
| * Author: Carlo Caione <carlo@endlessm.com> |
| * |
| * This file is dual-licensed: you can use it either under the terms |
| * of the GPL or the X11 license, at your option. Note that this dual |
| * licensing only applies to this file, and not this project as a |
| * whole. |
| * |
| * a) This library is free software; you can redistribute it and/or |
| * modify it under the terms of the GNU General Public License as |
| * published by the Free Software Foundation; either version 2 of the |
| * License, or (at your option) any later version. |
| * |
| * This library is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * Or, alternatively, |
| * |
| * b) Permission is hereby granted, free of charge, to any person |
| * obtaining a copy of this software and associated documentation |
| * files (the "Software"), to deal in the Software without |
| * restriction, including without limitation the rights to use, |
| * copy, modify, merge, publish, distribute, sublicense, and/or |
| * sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following |
| * conditions: |
| * |
| * The above copyright notice and this permission notice shall be |
| * included in all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
| * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
| * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
| * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| */ |
| |
| #include "meson-a-series.dtsi" |
| #include <dt-bindings/gpio/meson-a1-gpio.h> |
| #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h> |
| |
| / { |
| compatible = "amlogic,meson-a1"; |
| |
| vpu { |
| compatible = "amlogic, vpu-g12a"; |
| status = "okay"; |
| /*clocks = <&clkc CLKID_VAPB_MUX>, |
| * <&clkc CLKID_VPU_INTR>, |
| * <&clkc CLKID_VPU_P0_COMP>, |
| * <&clkc CLKID_VPU_P1_COMP>, |
| * <&clkc CLKID_VPU_MUX>; |
| *clock-names = "vapb_clk", |
| * "vpu_intr_gate", |
| * "vpu_clk0", |
| * "vpu_clk1", |
| * "vpu_clk"; |
| */ |
| clk_level = <7>; |
| /* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */ |
| /* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */ |
| }; |
| |
| meson-fb { |
| status = "okay"; |
| logo_addr = "0x7f800000"; |
| }; |
| }; |
| |
| ðmac { |
| reg = <0x0 0xff3f0000 0x0 0x10000 |
| 0x0 0xff634540 0x0 0x8>; |
| |
| // clocks = <&clkc CLKID_ETH_CORE>, |
| // <&clkc CLKID_FCLK_DIV2>, |
| // <&clkc CLKID_MPLL2>; |
| // clock-names = "stmmaceth", "clkin0", "clkin1"; |
| |
| mdio0: mdio { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "snps,dwmac-mdio"; |
| }; |
| }; |
| |
| &cbus { |
| pinctrl_periphs: pinctrl@0400 { |
| compatible = "amlogic,meson-a1-periphs-pinctrl"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| gpio: bank@0400 { |
| reg = <0x0 0x0400 0x0 0x003c>, |
| <0x0 0x0480 0x0 0x0118>; |
| reg-names = "mux", |
| "gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pinctrl_periphs 0 0 63>; |
| }; |
| }; |
| }; |
| |
| &periphs { |
| |
| eth-phy-mux { |
| compatible = "mdio-mux-mmioreg", "mdio-mux"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0 0x15c 0x0 0x4>; |
| mux-mask = <0xffffffff>; |
| mdio-parent-bus = <&mdio0>; |
| |
| internal_mdio: mdio@e40908ff { |
| reg = <0xe40908ff>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| internal_phy: ethernet-phy@8 { |
| compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22"; |
| reg = <8>; |
| max-speed = <100>; |
| }; |
| }; |
| |
| external_mdio: mdio@2009087f { |
| reg = <0x2009087f>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| }; |
| }; |
| |
| &saradc { |
| compatible = "amlogic,meson-g12a-saradc", "amlogic,meson-saradc"; |
| clocks = <&xtal>, |
| <&clkc CLKID_SARADC_MUX>, |
| <&clkc CLKID_SARADC_DIV>, |
| <&clkc CLKID_SAR_ADC_GATE>; |
| clock-names = "xtal", "adc_mux", "adc_div", "adc_gate"; |
| }; |
| |
| &sd_emmc_a { |
| /* |
| clocks = <&clkc CLKID_SD_EMMC_A>, |
| <&xtal>, |
| <&clkc CLKID_FCLK_DIV2>; |
| clock-names = "core", "clkin0", "clkin1"; |
| */ |
| }; |
| |
| &sd_emmc_b { |
| /* |
| clocks = <&clkc CLKID_FCLK_DIV2>, |
| <&xtal>, |
| <&clkc CLKID_SD_EMMC_B_P0_MUX>, |
| <&clkc CLKID_SD_EMMC_B_P0_DIV>, |
| <&clkc CLKID_SD_EMMC_B_P0_GATE>, |
| <&clkc CLKID_SD_EMMC_B>; |
| clock-names = "clkin", "clkin1", "clkin2", "clkin3", "clkin4", "core"; |
| */ |
| }; |
| |
| &sd_emmc_c { |
| /* |
| clocks = <&clkc CLKID_FCLK_DIV2>, |
| <&xtal>, |
| <&clkc CLKID_SD_EMMC_C_P0_MUX>, |
| <&clkc CLKID_SD_EMMC_C_P0_DIV>, |
| <&clkc CLKID_SD_EMMC_C_P0_GATE>, |
| <&clkc CLKID_SD_EMMC_C>; |
| clock-names = "clkin", "clkin1", "clkin2", "clkin3", "clkin4", "core"; |
| */ |
| }; |
| |
| &nand { |
| /* |
| clocks = <&clkc CLKID_FCLK_DIV2>, |
| <&clkc CLKID_SD_EMMC_C_P0_MUX>, |
| <&clkc CLKID_SD_EMMC_C_P0_DIV>, |
| <&clkc CLKID_SD_EMMC_C_P0_GATE>; |
| clock-names = "clkin", "clkin1", "clkin2", "clkin3";*/ |
| /*amlogic,mmc-syscon = <&sd_emmc_c>;*/ |
| }; |
| |
| &spicc0 { |
| clocks = <&clkc CLKID_SPICC_A_DIV>, <&clkc CLKID_SPICC_A_GATE>; |
| clock-names = "async", "async-gate"; |
| assigned-clocks = <&clkc CLKID_SPICC_A_MUX>, <&clkc CLKID_SPICC_A_DIV>; |
| assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>; |
| assigned-clock-rates = <0>, <200000000>; |
| /* =PM_SPICC, no set for power on already */ |
| /* pm-id = <22>; */ |
| }; |
| |
| &pinctrl_periphs { |
| jtag_a_pins:jtag_a_pin { |
| mux { |
| groups = "jtag_a_clk", |
| "jtag_a_tms", |
| "jtag_a_tdi", |
| "jtag_a_tdo"; |
| function = "jtag_a"; |
| }; |
| }; |
| |
| swd_a_pins:swd_a_pin { |
| mux { |
| groups = "swclk", |
| "swdio"; |
| function = "sw"; |
| }; |
| }; |
| |
| i2c0_master_pins1:i2c0_pins1 { |
| mux { |
| groups = "i2c_a_scl_f11", |
| "i2c_a_sda_f12"; |
| function = "i2c_a"; |
| bias-pull-up; |
| drive-strength = <3>; |
| }; |
| }; |
| |
| i2c0_master_pins2:i2c0_pins2 { |
| mux { |
| groups = "i2c_a_scl_f9", |
| "i2c_a_sda_f10"; |
| function = "i2c_a"; |
| bias-pull-up; |
| drive-strength = <3>; |
| }; |
| }; |
| |
| i2c1_master_pins1:i2c1_pins1 { |
| mux { |
| groups = "i2c_b_sda_x", |
| "i2c_b_scl_x"; |
| function = "i2c_b"; |
| bias-pull-up; |
| drive-strength = <3>; |
| }; |
| }; |
| |
| i2c1_master_pins2:i2c1_pins2 { |
| mux { |
| groups = "i2c_b_sda_a", |
| "i2c_b_scl_a"; |
| function = "i2c_b"; |
| bias-pull-up; |
| drive-strength = <3>; |
| }; |
| }; |
| |
| i2c2_master_pins1:i2c2_pins1 { |
| mux { |
| groups = "i2c_c_scl_x0", |
| "i2c_c_sda_x1"; |
| function = "i2c_c"; |
| bias-pull-up; |
| drive-strength = <3>; |
| }; |
| }; |
| |
| i2c2_master_pins2:i2c2_pins2 { |
| mux { |
| groups = "i2c_c_scl_x15", |
| "i2c_c_sda_x16"; |
| function = "i2c_c"; |
| bias-pull-up; |
| drive-strength = <3>; |
| }; |
| }; |
| |
| i2c2_master_pins3:i2c2_pins3 { |
| mux { |
| groups = "i2c_c_scl_a4", |
| "i2c_c_sda_a5"; |
| function = "i2c_c"; |
| bias-pull-up; |
| drive-strength = <3>; |
| }; |
| }; |
| |
| i2c2_master_pins4:i2c2_pins4 { |
| mux { |
| groups = "i2c_c_scl_a8", |
| "i2c_c_sda_a9"; |
| function = "i2c_c"; |
| bias-pull-up; |
| drive-strength = <3>; |
| }; |
| }; |
| |
| i2c3_master_pins1:i2c3_pins1 { |
| mux { |
| groups = "i2c_d_scl_x", |
| "i2c_d_sda_x"; |
| function = "i2c_d"; |
| bias-pull-up; |
| drive-strength = <3>; |
| }; |
| }; |
| |
| i2c3_master_pins2:i2c3_pins2 { |
| mux { |
| groups = "i2c_d_scl_f", |
| "i2c_d_sda_f"; |
| function = "i2c_d"; |
| bias-pull-up; |
| drive-strength = <3>; |
| }; |
| }; |
| |
| spifc_pins: spifc_pins { |
| mux { |
| groups = "spif_mo", |
| "spif_mi", |
| "spif_clk", |
| "spif_cs", |
| "spif_hold_n", |
| "spif_wp_n"; |
| function = "spif"; |
| drive-strength = <3>; |
| }; |
| }; |
| |
| spicc0_pins_a: spicc0_pins_a { |
| mux { |
| groups = "spi_a_mosi_a", |
| "spi_a_miso_a", |
| "spi_a_sclk_a"; |
| function = "spi_a"; |
| drive-strength = <2>; |
| }; |
| }; |
| |
| pwm_a_pins1: pwm_a_pins1 { |
| mux { |
| groups = "pwm_a_x6"; |
| function = "pwm_a"; |
| }; |
| }; |
| |
| pwm_a_pins2: pwm_a_pins2 { |
| mux { |
| groups = "pwm_a_x7"; |
| function = "pwm_a"; |
| }; |
| }; |
| |
| pwm_a_pins3: pwm_a_pins3 { |
| mux { |
| groups = "pwm_a_f10"; |
| function = "pwm_a"; |
| }; |
| }; |
| |
| pwm_a_pins4: pwm_a_pins4 { |
| mux { |
| groups = "pwm_a_f6"; |
| function = "pwm_a"; |
| }; |
| }; |
| |
| pwm_a_pins5: pwm_a_pins5 { |
| mux { |
| groups = "pwm_a_a"; |
| function = "pwm_a"; |
| }; |
| }; |
| |
| pwm_b_pins1: pwm_b_pins1 { |
| mux { |
| groups = "pwm_b_x"; |
| function = "pwm_b"; |
| }; |
| }; |
| |
| pwm_b_pins2: pwm_b_pins2 { |
| mux { |
| groups = "pwm_b_f"; |
| function = "pwm_b"; |
| }; |
| }; |
| |
| pwm_b_pins3: pwm_b_pins3 { |
| mux { |
| groups = "pwm_b_a"; |
| function = "pwm_b"; |
| }; |
| }; |
| |
| pwm_c_pins1: pwm_c_pins1 { |
| mux { |
| groups = "pwm_c_x"; |
| function = "pwm_c"; |
| }; |
| }; |
| |
| pwm_c_pins2: pwm_c_pins2 { |
| mux { |
| groups = "pwm_c_f3"; |
| function = "pwm_c"; |
| }; |
| }; |
| |
| pwm_c_pins3: pwm_c_pins3 { |
| mux { |
| groups = "pwm_c_f8"; |
| function = "pwm_c"; |
| }; |
| }; |
| |
| pwm_c_pins3: pwm_c_pins3 { |
| mux { |
| groups = "pwm_c_f8"; |
| function = "pwm_c"; |
| }; |
| }; |
| |
| pwm_c_pins4: pwm_c_pins4 { |
| mux { |
| groups = "pwm_c_a"; |
| function = "pwm_c"; |
| }; |
| }; |
| |
| pwm_d_pins1: pwm_d_pins1 { |
| mux { |
| groups = "pwm_d_x15"; |
| function = "pwm_d"; |
| }; |
| }; |
| |
| pwm_d_pins2: pwm_d_pins2 { |
| mux { |
| groups = "pwm_d_x13"; |
| function = "pwm_d"; |
| }; |
| }; |
| |
| pwm_d_pins3: pwm_d_pins3 { |
| mux { |
| groups = "pwm_d_x10"; |
| function = "pwm_d"; |
| }; |
| }; |
| |
| pwm_d_pins4: pwm_d_pins4 { |
| mux { |
| groups = "pwm_d_f"; |
| function = "pwm_d"; |
| }; |
| }; |
| |
| pwm_e_pins1: pwm_e_pins1 { |
| mux { |
| groups = "pwm_e_p"; |
| function = "pwm_e"; |
| }; |
| }; |
| |
| pwm_e_pins2: pwm_e_pins2 { |
| mux { |
| groups = "pwm_e_x16"; |
| function = "pwm_e"; |
| }; |
| }; |
| |
| pwm_e_pins3: pwm_e_pins3 { |
| mux { |
| groups = "pwm_e_x14"; |
| function = "pwm_e"; |
| }; |
| }; |
| |
| pwm_e_pins4: pwm_e_pins4 { |
| mux { |
| groups = "pwm_e_x2"; |
| function = "pwm_e"; |
| }; |
| }; |
| |
| pwm_e_pins5: pwm_e_pins5 { |
| mux { |
| groups = "pwm_e_f"; |
| function = "pwm_e"; |
| }; |
| }; |
| |
| pwm_e_pins6: pwm_e_pins6 { |
| mux { |
| groups = "pwm_e_a"; |
| function = "pwm_e"; |
| }; |
| }; |
| |
| pwm_f_pins1: pwm_f_pins1 { |
| mux { |
| groups = "pwm_f_b"; |
| function = "pwm_f"; |
| }; |
| }; |
| |
| pwm_f_pins2: pwm_f_pins2 { |
| mux { |
| groups = "pwm_f_x"; |
| function = "pwm_f"; |
| }; |
| }; |
| |
| pwm_f_pins3: pwm_f_pins3 { |
| mux { |
| groups = "pwm_f_f4"; |
| function = "pwm_f"; |
| }; |
| }; |
| |
| pwm_f_pins4: pwm_f_pins4 { |
| mux { |
| groups = "pwm_f_f12"; |
| function = "pwm_f"; |
| }; |
| }; |
| }; |